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burrbullburrbull
committed
P4: JPEG+INT
1 parent a00cb2d commit 131bce6

36 files changed

+3219
-4042
lines changed

‎esp32p4/src/i3c_mst.rs

+6-6
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@ pub struct RegisterBlock {
1212
int_clr: INT_CLR,
1313
int_raw: INT_RAW,
1414
int_st: INT_ST,
15-
int_st_ena: INT_ST_ENA,
15+
int_ena: INT_ENA,
1616
_reserved10: [u8; 0x04],
1717
reset_ctrl: RESET_CTRL,
1818
buffer_status_level: BUFFER_STATUS_LEVEL,
@@ -92,8 +92,8 @@ impl RegisterBlock {
9292
}
9393
#[doc = "0x3c - The Interrupt status will be updated in INTR_STATUS register if corresponding Status Enable bit set."]
9494
#[inline(always)]
95-
pub const fn int_st_ena(&self) -> &INT_ST_ENA {
96-
&self.int_st_ena
95+
pub const fn int_ena(&self) -> &INT_ENA {
96+
&self.int_ena
9797
}
9898
#[doc = "0x44 - NA"]
9999
#[inline(always)]
@@ -262,10 +262,10 @@ pub mod int_raw;
262262
pub type INT_ST = crate::Reg<int_st::INT_ST_SPEC>;
263263
#[doc = "NA"]
264264
pub mod int_st;
265-
#[doc = "INT_ST_ENA (rw) register accessor: The Interrupt status will be updated in INTR_STATUS register if corresponding Status Enable bit set.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_st_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st_ena`] module"]
266-
pub type INT_ST_ENA = crate::Reg<int_st_ena::INT_ST_ENA_SPEC>;
265+
#[doc = "INT_ENA (rw) register accessor: The Interrupt status will be updated in INTR_STATUS register if corresponding Status Enable bit set.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"]
266+
pub type INT_ENA = crate::Reg<int_ena::INT_ENA_SPEC>;
267267
#[doc = "The Interrupt status will be updated in INTR_STATUS register if corresponding Status Enable bit set."]
268-
pub mod int_st_ena;
268+
pub mod int_ena;
269269
#[doc = "RESET_CTRL (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reset_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reset_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reset_ctrl`] module"]
270270
pub type RESET_CTRL = crate::Reg<reset_ctrl::RESET_CTRL_SPEC>;
271271
#[doc = "NA"]

‎esp32p4/src/i3c_mst/int_clr.rs

+65-65
Original file line numberDiff line numberDiff line change
@@ -1,37 +1,37 @@
11
#[doc = "Register `INT_CLR` writer"]
22
pub type W = crate::W<INT_CLR_SPEC>;
3-
#[doc = "Field `TX_DATA_BUF_THLD_INT_CLR` writer - NA"]
4-
pub type TX_DATA_BUF_THLD_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
5-
#[doc = "Field `RX_DATA_BUF_THLD_INT_CLR` writer - NA"]
6-
pub type RX_DATA_BUF_THLD_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
7-
#[doc = "Field `IBI_STATUS_THLD_INT_CLR` writer - NA"]
8-
pub type IBI_STATUS_THLD_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
9-
#[doc = "Field `CMD_BUF_EMPTY_THLD_INT_CLR` writer - NA"]
10-
pub type CMD_BUF_EMPTY_THLD_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
11-
#[doc = "Field `RESP_READY_INT_CLR` writer - NA"]
12-
pub type RESP_READY_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
13-
#[doc = "Field `NXT_CMD_REQ_ERR_INT_CLR` writer - NA"]
14-
pub type NXT_CMD_REQ_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
15-
#[doc = "Field `TRANSFER_ERR_INT_CLR` writer - NA"]
16-
pub type TRANSFER_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
17-
#[doc = "Field `TRANSFER_COMPLETE_INT_CLR` writer - NA"]
18-
pub type TRANSFER_COMPLETE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
19-
#[doc = "Field `COMMAND_DONE_INT_CLR` writer - NA"]
20-
pub type COMMAND_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
21-
#[doc = "Field `DETECT_START_INT_CLR` writer - NA"]
22-
pub type DETECT_START_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
23-
#[doc = "Field `RESP_BUF_OVF_INT_CLR` writer - NA"]
24-
pub type RESP_BUF_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
25-
#[doc = "Field `IBI_DATA_BUF_OVF_INT_CLR` writer - NA"]
26-
pub type IBI_DATA_BUF_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
27-
#[doc = "Field `IBI_STATUS_BUF_OVF_INT_CLR` writer - NA"]
28-
pub type IBI_STATUS_BUF_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
29-
#[doc = "Field `IBI_HANDLE_DONE_INT_CLR` writer - NA"]
30-
pub type IBI_HANDLE_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
31-
#[doc = "Field `IBI_DETECT_INT_CLR` writer - NA"]
32-
pub type IBI_DETECT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
33-
#[doc = "Field `CMD_CCC_MISMATCH_INT_CLR` writer - NA"]
34-
pub type CMD_CCC_MISMATCH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
3+
#[doc = "Field `TX_DATA_BUF_THLD` writer - NA"]
4+
pub type TX_DATA_BUF_THLD_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5+
#[doc = "Field `RX_DATA_BUF_THLD` writer - NA"]
6+
pub type RX_DATA_BUF_THLD_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7+
#[doc = "Field `IBI_STATUS_THLD` writer - NA"]
8+
pub type IBI_STATUS_THLD_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9+
#[doc = "Field `CMD_BUF_EMPTY_THLD` writer - NA"]
10+
pub type CMD_BUF_EMPTY_THLD_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11+
#[doc = "Field `RESP_READY` writer - NA"]
12+
pub type RESP_READY_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13+
#[doc = "Field `NXT_CMD_REQ_ERR` writer - NA"]
14+
pub type NXT_CMD_REQ_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
15+
#[doc = "Field `TRANSFER_ERR` writer - NA"]
16+
pub type TRANSFER_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
17+
#[doc = "Field `TRANSFER_COMPLETE` writer - NA"]
18+
pub type TRANSFER_COMPLETE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
19+
#[doc = "Field `COMMAND_DONE` writer - NA"]
20+
pub type COMMAND_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
21+
#[doc = "Field `DETECT_START` writer - NA"]
22+
pub type DETECT_START_W<'a, REG> = crate::BitWriter1C<'a, REG>;
23+
#[doc = "Field `RESP_BUF_OVF` writer - NA"]
24+
pub type RESP_BUF_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
25+
#[doc = "Field `IBI_DATA_BUF_OVF` writer - NA"]
26+
pub type IBI_DATA_BUF_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
27+
#[doc = "Field `IBI_STATUS_BUF_OVF` writer - NA"]
28+
pub type IBI_STATUS_BUF_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
29+
#[doc = "Field `IBI_HANDLE_DONE` writer - NA"]
30+
pub type IBI_HANDLE_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
31+
#[doc = "Field `IBI_DETECT` writer - NA"]
32+
pub type IBI_DETECT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
33+
#[doc = "Field `CMD_CCC_MISMATCH` writer - NA"]
34+
pub type CMD_CCC_MISMATCH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
3535
#[cfg(feature = "impl-register-debug")]
3636
impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
3737
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
@@ -42,98 +42,98 @@ impl W {
4242
#[doc = "Bit 0 - NA"]
4343
#[inline(always)]
4444
#[must_use]
45-
pub fn tx_data_buf_thld_int_clr(&mut self) -> TX_DATA_BUF_THLD_INT_CLR_W<INT_CLR_SPEC> {
46-
TX_DATA_BUF_THLD_INT_CLR_W::new(self, 0)
45+
pub fn tx_data_buf_thld(&mut self) -> TX_DATA_BUF_THLD_W<INT_CLR_SPEC> {
46+
TX_DATA_BUF_THLD_W::new(self, 0)
4747
}
4848
#[doc = "Bit 1 - NA"]
4949
#[inline(always)]
5050
#[must_use]
51-
pub fn rx_data_buf_thld_int_clr(&mut self) -> RX_DATA_BUF_THLD_INT_CLR_W<INT_CLR_SPEC> {
52-
RX_DATA_BUF_THLD_INT_CLR_W::new(self, 1)
51+
pub fn rx_data_buf_thld(&mut self) -> RX_DATA_BUF_THLD_W<INT_CLR_SPEC> {
52+
RX_DATA_BUF_THLD_W::new(self, 1)
5353
}
5454
#[doc = "Bit 2 - NA"]
5555
#[inline(always)]
5656
#[must_use]
57-
pub fn ibi_status_thld_int_clr(&mut self) -> IBI_STATUS_THLD_INT_CLR_W<INT_CLR_SPEC> {
58-
IBI_STATUS_THLD_INT_CLR_W::new(self, 2)
57+
pub fn ibi_status_thld(&mut self) -> IBI_STATUS_THLD_W<INT_CLR_SPEC> {
58+
IBI_STATUS_THLD_W::new(self, 2)
5959
}
6060
#[doc = "Bit 3 - NA"]
6161
#[inline(always)]
6262
#[must_use]
63-
pub fn cmd_buf_empty_thld_int_clr(&mut self) -> CMD_BUF_EMPTY_THLD_INT_CLR_W<INT_CLR_SPEC> {
64-
CMD_BUF_EMPTY_THLD_INT_CLR_W::new(self, 3)
63+
pub fn cmd_buf_empty_thld(&mut self) -> CMD_BUF_EMPTY_THLD_W<INT_CLR_SPEC> {
64+
CMD_BUF_EMPTY_THLD_W::new(self, 3)
6565
}
6666
#[doc = "Bit 4 - NA"]
6767
#[inline(always)]
6868
#[must_use]
69-
pub fn resp_ready_int_clr(&mut self) -> RESP_READY_INT_CLR_W<INT_CLR_SPEC> {
70-
RESP_READY_INT_CLR_W::new(self, 4)
69+
pub fn resp_ready(&mut self) -> RESP_READY_W<INT_CLR_SPEC> {
70+
RESP_READY_W::new(self, 4)
7171
}
7272
#[doc = "Bit 5 - NA"]
7373
#[inline(always)]
7474
#[must_use]
75-
pub fn nxt_cmd_req_err_int_clr(&mut self) -> NXT_CMD_REQ_ERR_INT_CLR_W<INT_CLR_SPEC> {
76-
NXT_CMD_REQ_ERR_INT_CLR_W::new(self, 5)
75+
pub fn nxt_cmd_req_err(&mut self) -> NXT_CMD_REQ_ERR_W<INT_CLR_SPEC> {
76+
NXT_CMD_REQ_ERR_W::new(self, 5)
7777
}
7878
#[doc = "Bit 6 - NA"]
7979
#[inline(always)]
8080
#[must_use]
81-
pub fn transfer_err_int_clr(&mut self) -> TRANSFER_ERR_INT_CLR_W<INT_CLR_SPEC> {
82-
TRANSFER_ERR_INT_CLR_W::new(self, 6)
81+
pub fn transfer_err(&mut self) -> TRANSFER_ERR_W<INT_CLR_SPEC> {
82+
TRANSFER_ERR_W::new(self, 6)
8383
}
8484
#[doc = "Bit 7 - NA"]
8585
#[inline(always)]
8686
#[must_use]
87-
pub fn transfer_complete_int_clr(&mut self) -> TRANSFER_COMPLETE_INT_CLR_W<INT_CLR_SPEC> {
88-
TRANSFER_COMPLETE_INT_CLR_W::new(self, 7)
87+
pub fn transfer_complete(&mut self) -> TRANSFER_COMPLETE_W<INT_CLR_SPEC> {
88+
TRANSFER_COMPLETE_W::new(self, 7)
8989
}
9090
#[doc = "Bit 8 - NA"]
9191
#[inline(always)]
9292
#[must_use]
93-
pub fn command_done_int_clr(&mut self) -> COMMAND_DONE_INT_CLR_W<INT_CLR_SPEC> {
94-
COMMAND_DONE_INT_CLR_W::new(self, 8)
93+
pub fn command_done(&mut self) -> COMMAND_DONE_W<INT_CLR_SPEC> {
94+
COMMAND_DONE_W::new(self, 8)
9595
}
9696
#[doc = "Bit 9 - NA"]
9797
#[inline(always)]
9898
#[must_use]
99-
pub fn detect_start_int_clr(&mut self) -> DETECT_START_INT_CLR_W<INT_CLR_SPEC> {
100-
DETECT_START_INT_CLR_W::new(self, 9)
99+
pub fn detect_start(&mut self) -> DETECT_START_W<INT_CLR_SPEC> {
100+
DETECT_START_W::new(self, 9)
101101
}
102102
#[doc = "Bit 10 - NA"]
103103
#[inline(always)]
104104
#[must_use]
105-
pub fn resp_buf_ovf_int_clr(&mut self) -> RESP_BUF_OVF_INT_CLR_W<INT_CLR_SPEC> {
106-
RESP_BUF_OVF_INT_CLR_W::new(self, 10)
105+
pub fn resp_buf_ovf(&mut self) -> RESP_BUF_OVF_W<INT_CLR_SPEC> {
106+
RESP_BUF_OVF_W::new(self, 10)
107107
}
108108
#[doc = "Bit 11 - NA"]
109109
#[inline(always)]
110110
#[must_use]
111-
pub fn ibi_data_buf_ovf_int_clr(&mut self) -> IBI_DATA_BUF_OVF_INT_CLR_W<INT_CLR_SPEC> {
112-
IBI_DATA_BUF_OVF_INT_CLR_W::new(self, 11)
111+
pub fn ibi_data_buf_ovf(&mut self) -> IBI_DATA_BUF_OVF_W<INT_CLR_SPEC> {
112+
IBI_DATA_BUF_OVF_W::new(self, 11)
113113
}
114114
#[doc = "Bit 12 - NA"]
115115
#[inline(always)]
116116
#[must_use]
117-
pub fn ibi_status_buf_ovf_int_clr(&mut self) -> IBI_STATUS_BUF_OVF_INT_CLR_W<INT_CLR_SPEC> {
118-
IBI_STATUS_BUF_OVF_INT_CLR_W::new(self, 12)
117+
pub fn ibi_status_buf_ovf(&mut self) -> IBI_STATUS_BUF_OVF_W<INT_CLR_SPEC> {
118+
IBI_STATUS_BUF_OVF_W::new(self, 12)
119119
}
120120
#[doc = "Bit 13 - NA"]
121121
#[inline(always)]
122122
#[must_use]
123-
pub fn ibi_handle_done_int_clr(&mut self) -> IBI_HANDLE_DONE_INT_CLR_W<INT_CLR_SPEC> {
124-
IBI_HANDLE_DONE_INT_CLR_W::new(self, 13)
123+
pub fn ibi_handle_done(&mut self) -> IBI_HANDLE_DONE_W<INT_CLR_SPEC> {
124+
IBI_HANDLE_DONE_W::new(self, 13)
125125
}
126126
#[doc = "Bit 14 - NA"]
127127
#[inline(always)]
128128
#[must_use]
129-
pub fn ibi_detect_int_clr(&mut self) -> IBI_DETECT_INT_CLR_W<INT_CLR_SPEC> {
130-
IBI_DETECT_INT_CLR_W::new(self, 14)
129+
pub fn ibi_detect(&mut self) -> IBI_DETECT_W<INT_CLR_SPEC> {
130+
IBI_DETECT_W::new(self, 14)
131131
}
132132
#[doc = "Bit 15 - NA"]
133133
#[inline(always)]
134134
#[must_use]
135-
pub fn cmd_ccc_mismatch_int_clr(&mut self) -> CMD_CCC_MISMATCH_INT_CLR_W<INT_CLR_SPEC> {
136-
CMD_CCC_MISMATCH_INT_CLR_W::new(self, 15)
135+
pub fn cmd_ccc_mismatch(&mut self) -> CMD_CCC_MISMATCH_W<INT_CLR_SPEC> {
136+
CMD_CCC_MISMATCH_W::new(self, 15)
137137
}
138138
}
139139
#[doc = "NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
@@ -145,7 +145,7 @@ impl crate::RegisterSpec for INT_CLR_SPEC {
145145
impl crate::Writable for INT_CLR_SPEC {
146146
type Safety = crate::Unsafe;
147147
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
148-
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
148+
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff;
149149
}
150150
#[doc = "`reset()` method sets INT_CLR to value 0"]
151151
impl crate::Resettable for INT_CLR_SPEC {

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