Update PACs, remove xtensa/riscv features

Author: bugadani

esp-hal-embassy/Cargo.toml

@@ -50,6 +50,3 @@ integrated-timers = ["embassy-executor?/integrated-timers"]
 
 [lints.rust]
 unexpected_cfgs = "allow"
-
-[patch.crates-io]
-xtensa-lx = { path = "../xtensa-lx" }

esp-hal/Cargo.toml

@@ -44,30 +44,32 @@ nb                       = "1.1.0"
 paste                    = "1.0.15"
 portable-atomic          = { version = "1.9.0", default-features = false }
 procmacros               = { version = "0.14.0", features = ["enum-dispatch", "interrupt", "ram"], package = "esp-hal-procmacros", path = "../esp-hal-procmacros" }
-riscv                    = { version = "0.11.1", optional = true }
 strum                    = { version = "0.26.3", default-features = false, features = ["derive"] }
 void                     = { version = "1.0.2", default-features = false }
 usb-device               = { version = "0.3.2", optional = true }
 rand_core                = "0.6.4"
 ufmt-write               = "0.1.0"
-xtensa-lx                = { version = "0.9.0", optional = true }
 
 # IMPORTANT:
 # Each supported device MUST have its PAC included below along with a
 # corresponding feature.
-esp32   = { version = "0.33.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "80ed3b5", features = ["critical-section", "rt"], optional = true }
-esp32c2 = { version = "0.22.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "80ed3b5", features = ["critical-section", "rt"], optional = true }
-esp32c3 = { version = "0.25.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "80ed3b5", features = ["critical-section", "rt"], optional = true }
-esp32c6 = { version = "0.16.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "80ed3b5", features = ["critical-section", "rt"], optional = true }
-esp32h2 = { version = "0.12.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "80ed3b5", features = ["critical-section", "rt"], optional = true }
-esp32s2 = { version = "0.24.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "80ed3b5", features = ["critical-section", "rt"], optional = true }
-esp32s3 = { version = "0.28.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "80ed3b5", features = ["critical-section", "rt"], optional = true }
+esp32   = { version = "0.33.0", git = "https://github.com/esp-rs/esp-pacs", rev = "2d9fb24a7077aea7b071e2dfb63d81764957b1e9", features = ["critical-section", "rt"], optional = true }
+esp32c2 = { version = "0.22.0", git = "https://github.com/esp-rs/esp-pacs", rev = "2d9fb24a7077aea7b071e2dfb63d81764957b1e9", features = ["critical-section", "rt"], optional = true }
+esp32c3 = { version = "0.25.0", git = "https://github.com/esp-rs/esp-pacs", rev = "2d9fb24a7077aea7b071e2dfb63d81764957b1e9", features = ["critical-section", "rt"], optional = true }
+esp32c6 = { version = "0.16.0", git = "https://github.com/esp-rs/esp-pacs", rev = "2d9fb24a7077aea7b071e2dfb63d81764957b1e9", features = ["critical-section", "rt"], optional = true }
+esp32h2 = { version = "0.12.0", git = "https://github.com/esp-rs/esp-pacs", rev = "2d9fb24a7077aea7b071e2dfb63d81764957b1e9", features = ["critical-section", "rt"], optional = true }
+esp32s2 = { version = "0.24.0", git = "https://github.com/esp-rs/esp-pacs", rev = "2d9fb24a7077aea7b071e2dfb63d81764957b1e9", features = ["critical-section", "rt"], optional = true }
+esp32s3 = { version = "0.28.0", git = "https://github.com/esp-rs/esp-pacs", rev = "2d9fb24a7077aea7b071e2dfb63d81764957b1e9", features = ["critical-section", "rt"], optional = true }
 
 [target.'cfg(target_arch = "riscv32")'.dependencies]
-esp-riscv-rt = { version = "0.9.0", path = "../esp-riscv-rt" }
+riscv            = { version = "0.11.1" }
+esp-riscv-rt     = { version = "0.9.0", path = "../esp-riscv-rt" }
+critical-section = { version = "1.1.3", features = ["restore-state-u8"] }
 
 [target.'cfg(target_arch = "xtensa")'.dependencies]
-xtensa-lx-rt = { version = "0.17.0", path = "../xtensa-lx-rt" }
+xtensa-lx        = { version = "0.9.0", path = "../xtensa-lx" }
+xtensa-lx-rt     = { version = "0.17.0", path = "../xtensa-lx-rt" }
+critical-section = { version = "1.1.3", features = ["restore-state-u32"] }
 
 [build-dependencies]
 basic-toml   = "0.1.9"
@@ -80,9 +82,6 @@ serde        = { version = "1.0.210", features = ["derive"] }
 [features]
 default = []
 
-riscv  = ["dep:riscv",     "critical-section/restore-state-u8"]
-xtensa = ["dep:xtensa-lx", "critical-section/restore-state-u32"]
-
 bluetooth = []
 
 usb-otg = ["dep:embassy-usb-driver", "dep:embassy-usb-synopsys-otg", "dep:esp-synopsys-usb-otg", "dep:usb-device"]
@@ -104,19 +103,19 @@ log = ["dep:log"]
 
 # Chip Support Feature Flags
 # Target the ESP32.
-esp32   = ["dep:esp32",   "xtensa", "xtensa-lx-rt/esp32"]
+esp32   = ["dep:esp32",   "xtensa-lx-rt/esp32"]
 # Target the ESP32-C2.
-esp32c2 = ["dep:esp32c2", "riscv",  "portable-atomic/unsafe-assume-single-core"]
+esp32c2 = ["dep:esp32c2", "portable-atomic/unsafe-assume-single-core"]
 # Target the ESP32-C3.
-esp32c3 = ["dep:esp32c3", "riscv",  "portable-atomic/unsafe-assume-single-core", "esp-riscv-rt/rtc-ram"]
+esp32c3 = ["dep:esp32c3", "portable-atomic/unsafe-assume-single-core", "esp-riscv-rt/rtc-ram"]
 # Target the ESP32-C6.
-esp32c6 = ["dep:esp32c6", "riscv",  "procmacros/has-lp-core", "esp-riscv-rt/rtc-ram"]
+esp32c6 = ["dep:esp32c6", "procmacros/has-lp-core", "esp-riscv-rt/rtc-ram"]
 # Target the ESP32-H2.
-esp32h2 = ["dep:esp32h2", "riscv", "esp-riscv-rt/rtc-ram"]
+esp32h2 = ["dep:esp32h2", "esp-riscv-rt/rtc-ram"]
 # Target the ESP32-S2.
-esp32s2 = ["dep:esp32s2", "xtensa", "portable-atomic/critical-section", "procmacros/has-ulp-core", "xtensa-lx-rt/esp32s2", "usb-otg"]
+esp32s2 = ["dep:esp32s2", "portable-atomic/critical-section", "procmacros/has-ulp-core", "xtensa-lx-rt/esp32s2", "usb-otg"]
 # Target the ESP32-S3.
-esp32s3 = ["dep:esp32s3", "xtensa", "procmacros/has-ulp-core", "xtensa-lx-rt/esp32s3", "usb-otg"]
+esp32s3 = ["dep:esp32s3", "procmacros/has-ulp-core", "xtensa-lx-rt/esp32s3", "usb-otg"]
 
 #! ### RISC-V Exclusive Feature Flags
 ## Move the stack to start of RAM to get zero-cost stack overflow protection
@@ -157,6 +156,3 @@ mixed_attributes_style = "allow"
 
 [lints.rust]
 unexpected_cfgs = { level = "warn", check-cfg = ['cfg(host_os, values("windows"))'] }
-
-[patch.crates-io]
-xtensa-lx = { path = "../xtensa-lx" }

esp-wifi/Cargo.toml

@@ -197,6 +197,3 @@ features = [
   "esp-hal/default",
 ]
 default-target = "riscv32imc-unknown-none-elf"
-
-[patch.crates-io]
-xtensa-lx = { path = "../xtensa-lx" }

examples/Cargo.toml

@@ -70,6 +70,3 @@ incremental      = false
 opt-level        = 3
 lto = 'fat'
 overflow-checks  = false
-
-[patch.crates-io]
-xtensa-lx = { path = "../xtensa-lx" }

hil-test/Cargo.toml

@@ -312,6 +312,3 @@ incremental      = false
 opt-level        = 3
 lto              = false # LTO (thin or fat) miscompiles some tests on RISC-V
 overflow-checks  = false
-
-[patch.crates-io]
-xtensa-lx = { path = "../xtensa-lx" }

xtensa-lx-rt/Cargo.toml

@@ -16,7 +16,7 @@ features = ["esp32"]
 document-features = "0.2.10"
 macros            = { version = "0.2.2", package = "xtensa-lx-rt-proc-macros", path = "./procmacros" }
 r0                = "1.0.0"
-xtensa-lx         = "0.9.0"
+xtensa-lx         = { version = "0.9.0", path = "../xtensa-lx" }
 
 [build-dependencies]
 anyhow          = "1.0.89"