diff --git a/esp-hal/src/aes/esp32.rs b/esp-hal/src/aes/esp32.rs
index f9920a9a4d3..dd69d4c5439 100644
--- a/esp-hal/src/aes/esp32.rs
+++ b/esp-hal/src/aes/esp32.rs
@@ -56,7 +56,7 @@ impl<'d> Aes<'d> {
     }
 
     pub(super) fn write_start(&mut self) {
-        self.aes.start().write(|w| w.start().set_bit())
+        self.aes.start().write(|w| w.start().set_bit());
     }
 
     pub(super) fn read_idle(&mut self) -> bool {
diff --git a/esp-hal/src/aes/esp32s2.rs b/esp-hal/src/aes/esp32s2.rs
index 926612821c4..ccfb6a57c5d 100644
--- a/esp-hal/src/aes/esp32s2.rs
+++ b/esp-hal/src/aes/esp32s2.rs
@@ -3,7 +3,7 @@ use crate::{
     system::{Peripheral as PeripheralEnable, PeripheralClockControl},
 };
 
-impl<'d> Aes<'d> {
+impl Aes<'_> {
     pub(super) fn init(&mut self) {
         PeripheralClockControl::enable(PeripheralEnable::Aes);
         self.write_dma(false);
@@ -18,10 +18,9 @@ impl<'d> Aes<'d> {
     }
 
     fn write_dma(&mut self, enable_dma: bool) {
-        match enable_dma {
-            true => self.aes.dma_enable().write(|w| w.dma_enable().set_bit()),
-            false => self.aes.dma_enable().write(|w| w.dma_enable().clear_bit()),
-        }
+        self.aes
+            .dma_enable()
+            .write(|w| w.dma_enable().bit(enable_dma));
     }
 
     pub(super) fn write_key(&mut self, key: &[u8]) {
@@ -67,7 +66,7 @@ impl<'d> Aes<'d> {
     }
 
     pub(super) fn write_start(&mut self) {
-        self.aes.trigger().write(|w| w.trigger().set_bit())
+        self.aes.trigger().write(|w| w.trigger().set_bit());
     }
 
     pub(super) fn read_idle(&mut self) -> bool {
diff --git a/esp-hal/src/aes/esp32s3.rs b/esp-hal/src/aes/esp32s3.rs
index 6adc108449f..447dbacd5e2 100644
--- a/esp-hal/src/aes/esp32s3.rs
+++ b/esp-hal/src/aes/esp32s3.rs
@@ -3,17 +3,16 @@ use crate::{
     system::{Peripheral as PeripheralEnable, PeripheralClockControl},
 };
 
-impl<'d> Aes<'d> {
+impl Aes<'_> {
     pub(super) fn init(&mut self) {
         PeripheralClockControl::enable(PeripheralEnable::Aes);
         self.write_dma(false);
     }
 
     fn write_dma(&mut self, enable_dma: bool) {
-        match enable_dma {
-            true => self.aes.dma_enable().write(|w| w.dma_enable().set_bit()),
-            false => self.aes.dma_enable().write(|w| w.dma_enable().clear_bit()),
-        }
+        self.aes
+            .dma_enable()
+            .write(|w| w.dma_enable().bit(enable_dma));
     }
 
     pub(super) fn write_key(&mut self, key: &[u8]) {
@@ -39,7 +38,7 @@ impl<'d> Aes<'d> {
     }
 
     pub(super) fn write_start(&mut self) {
-        self.aes.trigger().write(|w| w.trigger().set_bit())
+        self.aes.trigger().write(|w| w.trigger().set_bit());
     }
 
     pub(super) fn read_idle(&mut self) -> bool {
diff --git a/esp-hal/src/dma/gdma.rs b/esp-hal/src/dma/gdma.rs
index 769b570e278..16ab18a30a6 100644
--- a/esp-hal/src/dma/gdma.rs
+++ b/esp-hal/src/dma/gdma.rs
@@ -216,7 +216,7 @@ impl<C: GdmaChannel> InterruptAccess<DmaTxInterrupt> for ChannelTxImpl<C> {
                 };
             }
             w
-        })
+        });
     }
 
     fn is_listening(&self) -> EnumSet<DmaTxInterrupt> {
@@ -250,7 +250,7 @@ impl<C: GdmaChannel> InterruptAccess<DmaTxInterrupt> for ChannelTxImpl<C> {
                 };
             }
             w
-        })
+        });
     }
 
     fn pending_interrupts(&self) -> EnumSet<DmaTxInterrupt> {
@@ -438,7 +438,7 @@ impl<C: GdmaChannel> InterruptAccess<DmaRxInterrupt> for ChannelRxImpl<C> {
                 };
             }
             w
-        })
+        });
     }
 
     fn pending_interrupts(&self) -> EnumSet<DmaRxInterrupt> {
diff --git a/esp-hal/src/dma/pdma.rs b/esp-hal/src/dma/pdma.rs
index ab18f2387c0..e2a6b995bb2 100644
--- a/esp-hal/src/dma/pdma.rs
+++ b/esp-hal/src/dma/pdma.rs
@@ -124,7 +124,7 @@ impl<C: PdmaChannel<RegisterBlock = SpiRegisterBlock>> InterruptAccess<DmaTxInte
                 };
             }
             w
-        })
+        });
     }
 
     fn is_listening(&self) -> EnumSet<DmaTxInterrupt> {
@@ -160,7 +160,7 @@ impl<C: PdmaChannel<RegisterBlock = SpiRegisterBlock>> InterruptAccess<DmaTxInte
                 };
             }
             w
-        })
+        });
     }
 
     fn pending_interrupts(&self) -> EnumSet<DmaTxInterrupt> {
@@ -259,7 +259,7 @@ impl<C: PdmaChannel<RegisterBlock = SpiRegisterBlock>> InterruptAccess<DmaRxInte
                 };
             }
             w
-        })
+        });
     }
 
     fn is_listening(&self) -> EnumSet<DmaRxInterrupt> {
@@ -299,7 +299,7 @@ impl<C: PdmaChannel<RegisterBlock = SpiRegisterBlock>> InterruptAccess<DmaRxInte
                 };
             }
             w
-        })
+        });
     }
 
     fn pending_interrupts(&self) -> EnumSet<DmaRxInterrupt> {
@@ -535,7 +535,7 @@ impl<C: PdmaChannel<RegisterBlock = I2sRegisterBlock>> InterruptAccess<DmaTxInte
                 };
             }
             w
-        })
+        });
     }
 
     fn is_listening(&self) -> EnumSet<DmaTxInterrupt> {
@@ -592,7 +592,7 @@ impl<C: PdmaChannel<RegisterBlock = I2sRegisterBlock>> InterruptAccess<DmaTxInte
                 };
             }
             w
-        })
+        });
     }
 
     fn waker(&self) -> &'static AtomicWaker {
@@ -676,7 +676,7 @@ impl<C: PdmaChannel<RegisterBlock = I2sRegisterBlock>> InterruptAccess<DmaRxInte
                 };
             }
             w
-        })
+        });
     }
 
     fn is_listening(&self) -> EnumSet<DmaRxInterrupt> {
@@ -740,7 +740,7 @@ impl<C: PdmaChannel<RegisterBlock = I2sRegisterBlock>> InterruptAccess<DmaRxInte
                 };
             }
             w
-        })
+        });
     }
 
     fn waker(&self) -> &'static AtomicWaker {
diff --git a/esp-hal/src/i2c.rs b/esp-hal/src/i2c.rs
index 452369252f4..a02e2adbd4e 100644
--- a/esp-hal/src/i2c.rs
+++ b/esp-hal/src/i2c.rs
@@ -646,10 +646,6 @@ where
 
             w.arbitration_lost().set_bit();
             w.time_out().set_bit();
-
-            #[cfg(esp32)]
-            w.ack_err().set_bit();
-            #[cfg(not(esp32))]
             w.nack().set_bit();
 
             w
@@ -680,16 +676,10 @@ where
             return Err(Error::TimeOut);
         }
 
-        #[cfg(not(esp32))]
         if r.nack().bit_is_set() {
             return Err(Error::AckCheckFailed);
         }
 
-        #[cfg(esp32)]
-        if r.ack_err().bit_is_set() {
-            return Err(Error::AckCheckFailed);
-        }
-
         #[cfg(not(esp32))]
         if r.trans_complete().bit_is_set()
             && self
@@ -1144,17 +1134,13 @@ fn handler(regs: &RegisterBlock) {
         w.end_detect().clear_bit();
         w.trans_complete().clear_bit();
         w.arbitration_lost().clear_bit();
-        w.time_out().clear_bit()
-    });
-
-    #[cfg(not(any(esp32, esp32s2)))]
-    regs.int_ena().modify(|_, w| w.txfifo_wm().clear_bit());
+        w.time_out().clear_bit();
 
-    #[cfg(not(esp32))]
-    regs.int_ena().modify(|_, w| w.nack().clear_bit());
+        #[cfg(not(any(esp32, esp32s2)))]
+        w.txfifo_wm().clear_bit();
 
-    #[cfg(esp32)]
-    regs.int_ena().modify(|_, w| w.ack_err().clear_bit());
+        w.nack().clear_bit()
+    });
 }
 
 #[handler]
@@ -1289,7 +1275,9 @@ pub trait Instance: Peripheral<P = Self> + PeripheralMarker + Into<AnyI2c> + 'st
                 sda_register.modify(|_, w| unsafe { w.sda_filter_thres().bits(threshold) });
                 sda_register.modify(|_, w| w.sda_filter_en().set_bit());
             }
-            None => sda_register.modify(|_, w| w.sda_filter_en().clear_bit()),
+            None => {
+                sda_register.modify(|_, w| w.sda_filter_en().clear_bit());
+            }
         }
 
         match scl_threshold {
@@ -1297,7 +1285,9 @@ pub trait Instance: Peripheral<P = Self> + PeripheralMarker + Into<AnyI2c> + 'st
                 scl_register.modify(|_, w| unsafe { w.scl_filter_thres().bits(threshold) });
                 scl_register.modify(|_, w| w.scl_filter_en().set_bit());
             }
-            None => scl_register.modify(|_, w| w.scl_filter_en().clear_bit()),
+            None => {
+                scl_register.modify(|_, w| w.scl_filter_en().clear_bit());
+            }
         }
     }
 
@@ -1825,7 +1815,7 @@ pub trait Instance: Peripheral<P = Self> + PeripheralMarker + Into<AnyI2c> + 'st
                 // Handle error cases
                 let retval = if interrupts.time_out().bit_is_set() {
                     Err(Error::TimeOut)
-                } else if interrupts.ack_err().bit_is_set() {
+                } else if interrupts.nack().bit_is_set() {
                     Err(Error::AckCheckFailed)
                 } else if interrupts.arbitration_lost().bit_is_set() {
                     Err(Error::ArbitrationLost)
diff --git a/esp-hal/src/interrupt/software.rs b/esp-hal/src/interrupt/software.rs
index 8b4284f7b33..92dfb32d4fa 100644
--- a/esp-hal/src/interrupt/software.rs
+++ b/esp-hal/src/interrupt/software.rs
@@ -93,7 +93,7 @@ impl<const NUM: u8> SoftwareInterrupt<NUM> {
                 .cpu_intr_from_cpu_3()
                 .write(|w| w.cpu_intr_from_cpu_3().set_bit()),
             _ => unreachable!(),
-        }
+        };
     }
 
     /// Resets this software-interrupt
@@ -120,7 +120,7 @@ impl<const NUM: u8> SoftwareInterrupt<NUM> {
                 .cpu_intr_from_cpu_3()
                 .write(|w| w.cpu_intr_from_cpu_3().clear_bit()),
             _ => unreachable!(),
-        }
+        };
     }
 
     /// Unsafely create an instance of this peripheral out of thin air.
diff --git a/esp-hal/src/mcpwm/operator.rs b/esp-hal/src/mcpwm/operator.rs
index d2df0a68ec9..8b256ec7b26 100644
--- a/esp-hal/src/mcpwm/operator.rs
+++ b/esp-hal/src/mcpwm/operator.rs
@@ -315,7 +315,7 @@ impl<'d, PWM: PwmPeripheral, const OP: u8, const IS_A: bool> PwmPin<'d, PWM, OP,
 
         // SAFETY:
         // `bits` is a valid bit pattern
-        ch.gen((!IS_A) as usize).write(|w| unsafe { w.bits(bits) })
+        ch.gen((!IS_A) as usize).write(|w| unsafe { w.bits(bits) });
     }
 
     /// Set how a new timestamp syncs with the timer
@@ -336,7 +336,7 @@ impl<'d, PWM: PwmPeripheral, const OP: u8, const IS_A: bool> PwmPin<'d, PWM, OP,
             } else {
                 w.b_upmethod().bits(bits)
             }
-        })
+        });
     }
 
     /// Write a new timestamp.
@@ -349,16 +349,16 @@ impl<'d, PWM: PwmPeripheral, const OP: u8, const IS_A: bool> PwmPin<'d, PWM, OP,
 
         #[cfg(esp32s3)]
         if IS_A {
-            ch.cmpr_value0().write(|w| unsafe { w.a().bits(value) })
+            ch.cmpr_value0().write(|w| unsafe { w.a().bits(value) });
         } else {
-            ch.cmpr_value1().write(|w| unsafe { w.b().bits(value) })
+            ch.cmpr_value1().write(|w| unsafe { w.b().bits(value) });
         }
 
         #[cfg(any(esp32, esp32c6, esp32h2))]
         if IS_A {
-            ch.gen_tstmp_a().write(|w| unsafe { w.a().bits(value) })
+            ch.gen_tstmp_a().write(|w| unsafe { w.a().bits(value) });
         } else {
-            ch.gen_tstmp_b().write(|w| unsafe { w.b().bits(value) })
+            ch.gen_tstmp_b().write(|w| unsafe { w.b().bits(value) });
         }
     }
 
diff --git a/esp-hal/src/rsa/esp32sX.rs b/esp-hal/src/rsa/esp32sX.rs
index bbdad42cac4..588da50d318 100644
--- a/esp-hal/src/rsa/esp32sX.rs
+++ b/esp-hal/src/rsa/esp32sX.rs
@@ -27,7 +27,7 @@ impl<'d, DM: crate::Mode> Rsa<'d, DM> {
     /// When enabled rsa peripheral would generate an interrupt when a operation
     /// is finished.
     pub fn enable_disable_interrupt(&mut self, enable: bool) {
-        self.rsa.int_ena().write(|w| w.int_ena().bit(enable))
+        self.rsa.int_ena().write(|w| w.int_ena().bit(enable));
     }
 
     fn write_mode(&mut self, mode: u32) {
@@ -44,16 +44,9 @@ impl<'d, DM: crate::Mode> Rsa<'d, DM> {
     ///
     /// For more information refer to 20.3.4 of <https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf>.
     pub fn enable_disable_search_acceleration(&mut self, enable: bool) {
-        match enable {
-            true => self
-                .rsa
-                .search_enable()
-                .write(|w| w.search_enable().set_bit()),
-            false => self
-                .rsa
-                .search_enable()
-                .write(|w| w.search_enable().clear_bit()),
-        }
+        self.rsa
+            .search_enable()
+            .write(|w| w.search_enable().bit(enable));
     }
 
     /// Checks if the search functionality is enabled in the RSA hardware.
@@ -79,16 +72,9 @@ impl<'d, DM: crate::Mode> Rsa<'d, DM> {
     ///
     /// For more information refer to 20.3.4 of <https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf>.
     pub fn enable_disable_constant_time_acceleration(&mut self, enable: bool) {
-        match enable {
-            true => self
-                .rsa
-                .constant_time()
-                .write(|w| w.constant_time().clear_bit()),
-            false => self
-                .rsa
-                .constant_time()
-                .write(|w| w.constant_time().set_bit()),
-        }
+        self.rsa
+            .constant_time()
+            .write(|w| w.constant_time().bit(!enable));
     }
 
     /// Starts the modular exponentiation operation.
diff --git a/esp-hal/src/rtc_cntl/mod.rs b/esp-hal/src/rtc_cntl/mod.rs
index 987f687cb8c..71797a64a26 100644
--- a/esp-hal/src/rtc_cntl/mod.rs
+++ b/esp-hal/src/rtc_cntl/mod.rs
@@ -983,7 +983,7 @@ impl Rwdt {
                 RwdtStage::Stage3 => rtc_cntl
                     .wdtconfig4()
                     .modify(|_, w| w.wdt_stg3_hold().bits(timeout_raw)),
-            }
+            };
 
             #[cfg(any(esp32c6, esp32h2))]
             match stage {
@@ -1003,7 +1003,7 @@ impl Rwdt {
                     w.wdt_stg3_hold()
                         .bits(timeout_raw >> (1 + Efuse::get_rwdt_multiplier()))
                 }),
-            }
+            };
 
             #[cfg(not(any(esp32, esp32c6, esp32h2)))]
             match stage {
@@ -1023,7 +1023,7 @@ impl Rwdt {
                     w.wdt_stg3_hold()
                         .bits(timeout_raw >> (1 + Efuse::get_rwdt_multiplier()))
                 }),
-            }
+            };
         }
 
         self.set_write_protection(true);
@@ -1048,7 +1048,7 @@ impl Rwdt {
             RwdtStage::Stage3 => rtc_cntl
                 .wdtconfig0()
                 .modify(|_, w| unsafe { w.wdt_stg3().bits(action as u8) }),
-        }
+        };
 
         self.set_write_protection(true);
     }
diff --git a/esp-hal/src/soc/esp32s3/psram.rs b/esp-hal/src/soc/esp32s3/psram.rs
index 27067c93724..9c55f719850 100644
--- a/esp-hal/src/soc/esp32s3/psram.rs
+++ b/esp-hal/src/soc/esp32s3/psram.rs
@@ -685,7 +685,7 @@ pub(crate) mod utils {
     #[ram]
     fn psram_set_cs_timing() {
         unsafe {
-            let spi = &*crate::peripherals::SPI0::PTR;
+            let spi = crate::peripherals::SPI0::steal();
             // SPI0/1 share the cs_hold / cs_setup, cd_hold_time / cd_setup_time registers
             // for PSRAM, so we only need to set SPI0 related registers here
             spi.spi_smem_ac()
@@ -705,19 +705,17 @@ pub(crate) mod utils {
         let cs1_io: u8 = PSRAM_CS_IO;
         if cs1_io == SPI_CS1_GPIO_NUM {
             unsafe {
-                let iomux = &*esp32s3::IO_MUX::PTR;
-                iomux
+                esp32s3::IO_MUX::steal()
                     .gpio(cs1_io as usize)
-                    .modify(|_, w| w.mcu_sel().bits(FUNC_SPICS1_SPICS1))
+                    .modify(|_, w| w.mcu_sel().bits(FUNC_SPICS1_SPICS1));
             }
         } else {
             unsafe {
                 esp_rom_gpio_connect_out_signal(cs1_io, SPICS1_OUT_IDX, false, false);
 
-                let iomux = &*esp32s3::IO_MUX::PTR;
-                iomux
+                esp32s3::IO_MUX::steal()
                     .gpio(cs1_io as usize)
-                    .modify(|_, w| w.mcu_sel().bits(PIN_FUNC_GPIO))
+                    .modify(|_, w| w.mcu_sel().bits(PIN_FUNC_GPIO));
             }
         }
 
@@ -1105,7 +1103,7 @@ pub(crate) mod utils {
     // requirement
     fn config_psram_spi_phases() {
         unsafe {
-            let spi = &*crate::peripherals::SPI0::PTR;
+            let spi = crate::peripherals::SPI0::steal();
             // Config Write CMD phase for SPI0 to access PSRAM
             spi.cache_sctrl()
                 .modify(|_, w| w.cache_sram_usr_wcmd().set_bit());
@@ -1156,15 +1154,15 @@ pub(crate) mod utils {
             spi.sram_cmd().modify(|_, w| w.sdout_oct().set_bit());
             spi.sram_cmd().modify(|_, w| w.sdin_oct().set_bit());
 
-            spi.cache_sctrl().modify(|_, w| w.sram_oct().set_bit())
+            spi.cache_sctrl().modify(|_, w| w.sram_oct().set_bit());
         }
     }
 
     #[ram]
     fn spi_flash_set_rom_required_regs() {
         // Disable the variable dummy mode when doing timing tuning
-        let spi = unsafe { &*crate::peripherals::SPI1::PTR };
-        spi.ddr().modify(|_, w| w.spi_fmem_var_dummy().clear_bit())
+        let spi = unsafe { crate::peripherals::SPI1::steal() };
+        spi.ddr().modify(|_, w| w.spi_fmem_var_dummy().clear_bit());
         // STR /DTR mode setting is done every time when
         // `esp_rom_opiflash_exec_cmd` is called
         //
@@ -1174,9 +1172,7 @@ pub(crate) mod utils {
 
     #[ram]
     fn mspi_pin_init() {
-        unsafe {
-            esp_rom_opiflash_pin_config();
-        }
+        unsafe { esp_rom_opiflash_pin_config() };
         spi_timing_set_pin_drive_strength();
         // Set F4R4 board pin drive strength. TODO: IDF-3663
     }
@@ -1186,7 +1182,7 @@ pub(crate) mod utils {
         // For now, set them all to 3. Need to check after QVL test results are out.
         // TODO: IDF-3663 Set default clk
         unsafe {
-            let spi = &*crate::peripherals::SPI0::PTR;
+            let spi = crate::peripherals::SPI0::steal();
 
             spi.date()
                 .modify(|_, w| w.spi_spiclk_pad_drv_ctl_en().set_bit());
@@ -1196,10 +1192,11 @@ pub(crate) mod utils {
                 .modify(|_, w| w.spi_fmem_spiclk_fun_drv().bits(3));
 
             // Set default mspi d0 ~ d7, dqs pin drive strength
-            let pins = &[27usize, 28, 31, 32, 33, 34, 35, 36, 37];
+            let pins = [27usize, 28, 31, 32, 33, 34, 35, 36, 37];
             for pin in pins {
-                let iomux = &*esp32s3::IO_MUX::PTR;
-                iomux.gpio(*pin).modify(|_, w| w.fun_drv().bits(3))
+                esp32s3::IO_MUX::steal()
+                    .gpio(pin)
+                    .modify(|_, w| w.fun_drv().bits(3));
             }
         }
     }
@@ -1284,18 +1281,16 @@ pub(crate) mod utils {
     fn init_psram_pins() {
         // Set cs1 pin function
         unsafe {
-            let iomux = &*esp32s3::IO_MUX::PTR;
-            iomux
+            esp32s3::IO_MUX::steal()
                 .gpio(OCT_PSRAM_CS1_IO as usize)
-                .modify(|_, w| w.mcu_sel().bits(FUNC_SPICS1_SPICS1))
+                .modify(|_, w| w.mcu_sel().bits(FUNC_SPICS1_SPICS1));
         }
 
         // Set mspi cs1 drive strength
         unsafe {
-            let iomux = &*esp32s3::IO_MUX::PTR;
-            iomux
+            esp32s3::IO_MUX::steal()
                 .gpio(OCT_PSRAM_CS1_IO as usize)
-                .modify(|_, w| w.fun_drv().bits(3))
+                .modify(|_, w| w.fun_drv().bits(3));
         }
 
         // Set psram clock pin drive strength
diff --git a/esp-hal/src/timer/timg.rs b/esp-hal/src/timer/timg.rs
index 60f4a4bc127..02f1cbdcfb4 100644
--- a/esp-hal/src/timer/timg.rs
+++ b/esp-hal/src/timer/timg.rs
@@ -804,7 +804,7 @@ where
     fn set_divider(&self, divider: u16) {
         unsafe { Self::t() }
             .config()
-            .modify(|_, w| unsafe { w.divider().bits(divider) })
+            .modify(|_, w| unsafe { w.divider().bits(divider) });
     }
 }
 
@@ -1074,7 +1074,7 @@ where
                 MwdtStage::Stage3 => reg_block
                     .wdtconfig5()
                     .write(|w| w.wdt_stg3_hold().bits(timeout_raw)),
-            }
+            };
         }
 
         #[cfg(any(esp32c2, esp32c3, esp32c6))]
diff --git a/esp-hal/src/usb_serial_jtag.rs b/esp-hal/src/usb_serial_jtag.rs
index 42c82f8aacd..c94c2be6c93 100644
--- a/esp-hal/src/usb_serial_jtag.rs
+++ b/esp-hal/src/usb_serial_jtag.rs
@@ -264,7 +264,7 @@ where
     pub fn reset_rx_packet_recv_interrupt(&mut self) {
         USB_DEVICE::register_block()
             .int_clr()
-            .write(|w| w.serial_out_recv_pkt().clear_bit_by_one())
+            .write(|w| w.serial_out_recv_pkt().clear_bit_by_one());
     }
 }
 
@@ -408,7 +408,7 @@ pub trait Instance: crate::private::Sealed {
 
         Self::register_block()
             .int_clr()
-            .write(|w| w.serial_in_empty().clear_bit_by_one())
+            .write(|w| w.serial_in_empty().clear_bit_by_one());
     }
 
     /// Disable all receive interrupts for the peripheral
@@ -419,7 +419,7 @@ pub trait Instance: crate::private::Sealed {
 
         Self::register_block()
             .int_clr()
-            .write(|w| w.serial_out_recv_pkt().clear_bit_by_one())
+            .write(|w| w.serial_out_recv_pkt().clear_bit_by_one());
     }
 }