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bugadanibugadani
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Slight cleanup throughout
1 parent 3c1aba5 commit 2276a9f

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10 files changed

+44
-87
lines changed

10 files changed

+44
-87
lines changed

‎esp-hal/Cargo.toml

+13-14
Original file line numberDiff line numberDiff line change
@@ -45,13 +45,11 @@ nb = "1.1.0"
4545
paste = "1.0.15"
4646
portable-atomic = { version = "1.9.0", default-features = false }
4747
procmacros = { version = "0.15.0", features = ["enum-dispatch", "interrupt", "ram"], package = "esp-hal-procmacros", path = "../esp-hal-procmacros" }
48-
riscv = { version = "0.12.1", optional = true }
4948
strum = { version = "0.26.3", default-features = false, features = ["derive"] }
5049
void = { version = "1.0.2", default-features = false }
5150
usb-device = { version = "0.3.2", optional = true }
5251
rand_core = "0.6.4"
5352
ufmt-write = "0.1.0"
54-
xtensa-lx = { version = "0.9.0", optional = true }
5553

5654
# IMPORTANT:
5755
# Each supported device MUST have its PAC included below along with a
@@ -65,10 +63,14 @@ esp32s2 = { version = "0.25.0", features = ["critical-section", "rt"], optional
6563
esp32s3 = { version = "0.29.0", features = ["critical-section", "rt"], optional = true }
6664

6765
[target.'cfg(target_arch = "riscv32")'.dependencies]
68-
esp-riscv-rt = { version = "0.9.1", path = "../esp-riscv-rt" }
66+
riscv = { version = "0.12.1" }
67+
esp-riscv-rt = { version = "0.9.1", path = "../esp-riscv-rt" }
68+
critical-section = { version = "1.2.0", features = ["restore-state-u8"] }
6969

7070
[target.'cfg(target_arch = "xtensa")'.dependencies]
71-
xtensa-lx-rt = { version = "0.17.2", path = "../xtensa-lx-rt" }
71+
xtensa-lx = { version = "0.9.0", path = "../xtensa-lx" }
72+
xtensa-lx-rt = { version = "0.17.2", path = "../xtensa-lx-rt" }
73+
critical-section = { version = "1.2.0", features = ["restore-state-u32"] }
7274

7375
[build-dependencies]
7476
basic-toml = "0.1.9"
@@ -81,9 +83,6 @@ serde = { version = "1.0.215", features = ["derive"] }
8183
[features]
8284
default = []
8385

84-
riscv = ["dep:riscv", "critical-section/restore-state-u8"]
85-
xtensa = ["dep:xtensa-lx", "critical-section/restore-state-u32"]
86-
8786
bluetooth = []
8887

8988
usb-otg = ["dep:embassy-usb-driver", "dep:embassy-usb-synopsys-otg", "dep:esp-synopsys-usb-otg", "dep:usb-device"]
@@ -105,19 +104,19 @@ log = ["dep:log"]
105104

106105
# Chip Support Feature Flags
107106
# Target the ESP32.
108-
esp32 = ["dep:esp32", "xtensa", "xtensa-lx/spin", "xtensa-lx-rt/esp32"]
107+
esp32 = ["dep:esp32", "xtensa-lx-rt/esp32"]
109108
# Target the ESP32-C2.
110-
esp32c2 = ["dep:esp32c2", "riscv", "portable-atomic/unsafe-assume-single-core"]
109+
esp32c2 = ["dep:esp32c2", "portable-atomic/unsafe-assume-single-core"]
111110
# Target the ESP32-C3.
112-
esp32c3 = ["dep:esp32c3", "riscv", "portable-atomic/unsafe-assume-single-core", "esp-riscv-rt/rtc-ram"]
111+
esp32c3 = ["dep:esp32c3", "portable-atomic/unsafe-assume-single-core", "esp-riscv-rt/rtc-ram"]
113112
# Target the ESP32-C6.
114-
esp32c6 = ["dep:esp32c6", "riscv", "procmacros/has-lp-core", "esp-riscv-rt/rtc-ram"]
113+
esp32c6 = ["dep:esp32c6", "procmacros/has-lp-core", "esp-riscv-rt/rtc-ram"]
115114
# Target the ESP32-H2.
116-
esp32h2 = ["dep:esp32h2", "riscv", "esp-riscv-rt/rtc-ram"]
115+
esp32h2 = ["dep:esp32h2", "esp-riscv-rt/rtc-ram"]
117116
# Target the ESP32-S2.
118-
esp32s2 = ["dep:esp32s2", "xtensa", "portable-atomic/critical-section", "procmacros/has-ulp-core", "xtensa-lx-rt/esp32s2", "usb-otg"]
117+
esp32s2 = ["dep:esp32s2", "portable-atomic/critical-section", "procmacros/has-ulp-core", "xtensa-lx-rt/esp32s2", "usb-otg"]
119118
# Target the ESP32-S3.
120-
esp32s3 = ["dep:esp32s3", "xtensa", "procmacros/has-ulp-core", "xtensa-lx/spin", "xtensa-lx-rt/esp32s3", "usb-otg"]
119+
esp32s3 = ["dep:esp32s3", "procmacros/has-ulp-core", "xtensa-lx-rt/esp32s3", "usb-otg"]
121120

122121
#! ### RISC-V Exclusive Feature Flags
123122
## Move the stack to start of RAM to get zero-cost stack overflow protection

‎esp-hal/src/aes/esp32.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@ use crate::{
33
system::{Peripheral as PeripheralEnable, PeripheralClockControl},
44
};
55

6-
impl<'d> Aes<'d> {
6+
impl Aes<'_> {
77
pub(super) fn init(&mut self) {
88
PeripheralClockControl::enable(PeripheralEnable::Aes);
99
self.write_endianness(

‎esp-hal/src/aes/esp32s2.rs

+4-5
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@ use crate::{
33
system::{Peripheral as PeripheralEnable, PeripheralClockControl},
44
};
55

6-
impl<'d> Aes<'d> {
6+
impl Aes<'_> {
77
pub(super) fn init(&mut self) {
88
PeripheralClockControl::enable(PeripheralEnable::Aes);
99
self.write_dma(false);
@@ -18,10 +18,9 @@ impl<'d> Aes<'d> {
1818
}
1919

2020
fn write_dma(&mut self, enable_dma: bool) {
21-
match enable_dma {
22-
true => self.aes.dma_enable().write(|w| w.dma_enable().set_bit()),
23-
false => self.aes.dma_enable().write(|w| w.dma_enable().clear_bit()),
24-
};
21+
self.aes
22+
.dma_enable()
23+
.write(|w| w.dma_enable().bit(enable_dma));
2524
}
2625

2726
pub(super) fn write_key(&mut self, key: &[u8]) {

‎esp-hal/src/aes/esp32s3.rs

+4-5
Original file line numberDiff line numberDiff line change
@@ -3,17 +3,16 @@ use crate::{
33
system::{Peripheral as PeripheralEnable, PeripheralClockControl},
44
};
55

6-
impl<'d> Aes<'d> {
6+
impl Aes<'_> {
77
pub(super) fn init(&mut self) {
88
PeripheralClockControl::enable(PeripheralEnable::Aes);
99
self.write_dma(false);
1010
}
1111

1212
fn write_dma(&mut self, enable_dma: bool) {
13-
match enable_dma {
14-
true => self.aes.dma_enable().write(|w| w.dma_enable().set_bit()),
15-
false => self.aes.dma_enable().write(|w| w.dma_enable().clear_bit()),
16-
};
13+
self.aes
14+
.dma_enable()
15+
.write(|w| w.dma_enable().bit(enable_dma));
1716
}
1817

1918
pub(super) fn write_key(&mut self, key: &[u8]) {

‎esp-hal/src/i2c/master/mod.rs

-10
Original file line numberDiff line numberDiff line change
@@ -601,10 +601,6 @@ impl<'a> I2cFuture<'a> {
601601

602602
w.arbitration_lost().set_bit();
603603
w.time_out().set_bit();
604-
605-
#[cfg(esp32)]
606-
w.ack_err().set_bit();
607-
#[cfg(not(esp32))]
608604
w.nack().set_bit();
609605

610606
w
@@ -635,16 +631,10 @@ impl<'a> I2cFuture<'a> {
635631
return Err(Error::TimeOut);
636632
}
637633

638-
#[cfg(not(esp32))]
639634
if r.nack().bit_is_set() {
640635
return Err(Error::AckCheckFailed);
641636
}
642637

643-
#[cfg(esp32)]
644-
if r.ack_err().bit_is_set() {
645-
return Err(Error::AckCheckFailed);
646-
}
647-
648638
#[cfg(not(esp32))]
649639
if r.trans_complete().bit_is_set()
650640
&& self

‎esp-hal/src/rsa/esp32sX.rs

+6-20
Original file line numberDiff line numberDiff line change
@@ -44,16 +44,9 @@ impl<'d, DM: crate::Mode> Rsa<'d, DM> {
4444
///
4545
/// For more information refer to 20.3.4 of <https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf>.
4646
pub fn enable_disable_search_acceleration(&mut self, enable: bool) {
47-
match enable {
48-
true => self
49-
.rsa
50-
.search_enable()
51-
.write(|w| w.search_enable().set_bit()),
52-
false => self
53-
.rsa
54-
.search_enable()
55-
.write(|w| w.search_enable().clear_bit()),
56-
};
47+
self.rsa
48+
.search_enable()
49+
.write(|w| w.search_enable().bit(enable));
5750
}
5851

5952
/// Checks if the search functionality is enabled in the RSA hardware.
@@ -79,16 +72,9 @@ impl<'d, DM: crate::Mode> Rsa<'d, DM> {
7972
///
8073
/// For more information refer to 20.3.4 of <https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf>.
8174
pub fn enable_disable_constant_time_acceleration(&mut self, enable: bool) {
82-
match enable {
83-
true => self
84-
.rsa
85-
.constant_time()
86-
.write(|w| w.constant_time().clear_bit()),
87-
false => self
88-
.rsa
89-
.constant_time()
90-
.write(|w| w.constant_time().set_bit()),
91-
};
75+
self.rsa
76+
.constant_time()
77+
.write(|w| w.constant_time().bit(!enable));
9278
}
9379

9480
/// Starts the modular exponentiation operation.

‎esp-hal/src/soc/esp32s3/psram.rs

+13-18
Original file line numberDiff line numberDiff line change
@@ -685,7 +685,7 @@ pub(crate) mod utils {
685685
#[ram]
686686
fn psram_set_cs_timing() {
687687
unsafe {
688-
let spi = &*crate::peripherals::SPI0::PTR;
688+
let spi = crate::peripherals::SPI0::steal();
689689
// SPI0/1 share the cs_hold / cs_setup, cd_hold_time / cd_setup_time registers
690690
// for PSRAM, so we only need to set SPI0 related registers here
691691
spi.spi_smem_ac()
@@ -705,17 +705,15 @@ pub(crate) mod utils {
705705
let cs1_io: u8 = PSRAM_CS_IO;
706706
if cs1_io == SPI_CS1_GPIO_NUM {
707707
unsafe {
708-
let iomux = &*esp32s3::IO_MUX::PTR;
709-
iomux
708+
esp32s3::IO_MUX::steal()
710709
.gpio(cs1_io as usize)
711710
.modify(|_, w| w.mcu_sel().bits(FUNC_SPICS1_SPICS1));
712711
}
713712
} else {
714713
unsafe {
715714
esp_rom_gpio_connect_out_signal(cs1_io, SPICS1_OUT_IDX, false, false);
716715

717-
let iomux = &*esp32s3::IO_MUX::PTR;
718-
iomux
716+
esp32s3::IO_MUX::steal()
719717
.gpio(cs1_io as usize)
720718
.modify(|_, w| w.mcu_sel().bits(PIN_FUNC_GPIO));
721719
}
@@ -1105,7 +1103,7 @@ pub(crate) mod utils {
11051103
// requirement
11061104
fn config_psram_spi_phases() {
11071105
unsafe {
1108-
let spi = &*crate::peripherals::SPI0::PTR;
1106+
let spi = crate::peripherals::SPI0::steal();
11091107
// Config Write CMD phase for SPI0 to access PSRAM
11101108
spi.cache_sctrl()
11111109
.modify(|_, w| w.cache_sram_usr_wcmd().set_bit());
@@ -1163,7 +1161,7 @@ pub(crate) mod utils {
11631161
#[ram]
11641162
fn spi_flash_set_rom_required_regs() {
11651163
// Disable the variable dummy mode when doing timing tuning
1166-
let spi = unsafe { &*crate::peripherals::SPI1::PTR };
1164+
let spi = unsafe { crate::peripherals::SPI1::steal() };
11671165
spi.ddr().modify(|_, w| w.spi_fmem_var_dummy().clear_bit());
11681166
// STR /DTR mode setting is done every time when
11691167
// `esp_rom_opiflash_exec_cmd` is called
@@ -1174,9 +1172,7 @@ pub(crate) mod utils {
11741172

11751173
#[ram]
11761174
fn mspi_pin_init() {
1177-
unsafe {
1178-
esp_rom_opiflash_pin_config();
1179-
}
1175+
unsafe { esp_rom_opiflash_pin_config() };
11801176
spi_timing_set_pin_drive_strength();
11811177
// Set F4R4 board pin drive strength. TODO: IDF-3663
11821178
}
@@ -1186,7 +1182,7 @@ pub(crate) mod utils {
11861182
// For now, set them all to 3. Need to check after QVL test results are out.
11871183
// TODO: IDF-3663 Set default clk
11881184
unsafe {
1189-
let spi = &*crate::peripherals::SPI0::PTR;
1185+
let spi = crate::peripherals::SPI0::steal();
11901186

11911187
spi.date()
11921188
.modify(|_, w| w.spi_spiclk_pad_drv_ctl_en().set_bit());
@@ -1196,10 +1192,11 @@ pub(crate) mod utils {
11961192
.modify(|_, w| w.spi_fmem_spiclk_fun_drv().bits(3));
11971193

11981194
// Set default mspi d0 ~ d7, dqs pin drive strength
1199-
let pins = &[27usize, 28, 31, 32, 33, 34, 35, 36, 37];
1195+
let pins = [27usize, 28, 31, 32, 33, 34, 35, 36, 37];
12001196
for pin in pins {
1201-
let iomux = &*esp32s3::IO_MUX::PTR;
1202-
iomux.gpio(*pin).modify(|_, w| w.fun_drv().bits(3));
1197+
esp32s3::IO_MUX::steal()
1198+
.gpio(pin)
1199+
.modify(|_, w| w.fun_drv().bits(3));
12031200
}
12041201
}
12051202
}
@@ -1284,16 +1281,14 @@ pub(crate) mod utils {
12841281
fn init_psram_pins() {
12851282
// Set cs1 pin function
12861283
unsafe {
1287-
let iomux = &*esp32s3::IO_MUX::PTR;
1288-
iomux
1284+
esp32s3::IO_MUX::steal()
12891285
.gpio(OCT_PSRAM_CS1_IO as usize)
12901286
.modify(|_, w| w.mcu_sel().bits(FUNC_SPICS1_SPICS1));
12911287
}
12921288

12931289
// Set mspi cs1 drive strength
12941290
unsafe {
1295-
let iomux = &*esp32s3::IO_MUX::PTR;
1296-
iomux
1291+
esp32s3::IO_MUX::steal()
12971292
.gpio(OCT_PSRAM_CS1_IO as usize)
12981293
.modify(|_, w| w.fun_drv().bits(3));
12991294
}

‎xtensa-lx-rt/Cargo.toml

+1-1
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ bare-metal = "1.0.0"
1717
document-features = "0.2.10"
1818
macros = { version = "0.2.2", package = "xtensa-lx-rt-proc-macros", path = "./procmacros" }
1919
r0 = "1.0.0"
20-
xtensa-lx = "0.9.0"
20+
xtensa-lx = { version = "0.9.0", path = "../xtensa-lx" }
2121

2222
[build-dependencies]
2323
anyhow = "1.0.89"

‎xtensa-lx/README.md

+1-7
Original file line numberDiff line numberDiff line change
@@ -5,13 +5,7 @@
55
![Crates.io](https://img.shields.io/crates/l/xtensa-lx?labelColor=1C2C2E&style=flat-square)
66
[![Matrix](https://img.shields.io/matrix/esp-rs:matrix.org?label=join%20matrix&labelColor=1C2C2E&color=BEC5C9&logo=matrix&style=flat-square)](https://matrix.to/#/#esp-rs:matrix.org)
77

8-
Low level access to Xtensa LX processors. This crate currently supports the following CPUs:
9-
10-
| Feature | Supported CPUs |
11-
| --------- | ---------------- |
12-
| `esp32` | ESP32 (_LX6_) |
13-
| `esp32s2` | ESP32-S2 (_LX7_) |
14-
| `esp32s3` | ESP32-S3 (_LX7_) |
8+
Low level access to Xtensa LX processors.
159

1610
## [Documentation](https://docs.rs/crate/xtensa-lx)
1711

‎xtensa-lx/build.rs

+1-6
Original file line numberDiff line numberDiff line change
@@ -1,6 +1 @@
1-
use std::{env, path::PathBuf};
2-
3-
fn main() {
4-
let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap());
5-
println!("cargo:rustc-link-search={}", out_dir.display());
6-
}
1+
fn main() {}

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