diff --git a/esp-hal/CHANGELOG.md b/esp-hal/CHANGELOG.md index ac319cef4a0..02410fac40f 100644 --- a/esp-hal/CHANGELOG.md +++ b/esp-hal/CHANGELOG.md @@ -36,6 +36,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0 - Migrate AES driver to DMA move API (#3084) - Removed features `psram-quad` and `psram-octal` - replaced by `psram` and the `ESP_HAL_CONFIG_PSRAM_MODE` (`quad`/`octal`) (#3001) - The `esp_hal::time` module no longer reexports `fugit` types (#3083) +- The `system::RadioClockController` trait has been replaced by the `clock::RadioClockController` struct. (#3100) - I2C: Async functions are postfixed with `_async`, non-async functions are available in async-mode (#3056) diff --git a/esp-hal/src/clock/clocks_ll/esp32.rs b/esp-hal/src/clock/clocks_ll/esp32.rs index ec4e9cf518b..b633fe5c624 100644 --- a/esp-hal/src/clock/clocks_ll/esp32.rs +++ b/esp-hal/src/clock/clocks_ll/esp32.rs @@ -1,5 +1,6 @@ use crate::{ clock::{Clock, PllClock, XtalClock}, + peripherals::DPORT, rom::regi2c_write, }; @@ -254,90 +255,45 @@ fn esp32_update_cpu_freq(mhz: u32) { } } -use crate::{ - peripherals::DPORT, - system::{RadioClockController, RadioPeripherals}, -}; - const DPORT_WIFI_CLK_WIFI_BT_COMMON_M: u32 = 0x000003c9; const DPORT_WIFI_CLK_WIFI_EN_M: u32 = 0x00000406; const DPORT_WIFI_CLK_BT_EN_M: u32 = 0x00030800; -impl RadioClockController for crate::peripherals::RADIO_CLK { - fn enable(&mut self, peripheral: RadioPeripherals) { - match peripheral { - RadioPeripherals::Phy => enable_phy(), - RadioPeripherals::Bt => bt_clock_enable(), - RadioPeripherals::Wifi => wifi_clock_enable(), - } - } - - fn disable(&mut self, peripheral: RadioPeripherals) { - match peripheral { - RadioPeripherals::Phy => disable_phy(), - RadioPeripherals::Bt => bt_clock_disable(), - RadioPeripherals::Wifi => wifi_clock_disable(), - } - } - - fn reset_mac(&mut self) { - reset_mac(); - } - - fn init_clocks(&mut self) { - init_clocks(); - } - - fn ble_rtc_clk_init(&mut self) { - // nothing for this target - } - - fn reset_rpa(&mut self) { - // nothing for this target - } -} - -fn enable_phy() { +pub(super) fn enable_phy(enable: bool) { // `periph_ll_wifi_bt_module_enable_clk_clear_rst` - DPORT::regs() - .wifi_clk_en() - .modify(|r, w| unsafe { w.bits(r.bits() | DPORT_WIFI_CLK_WIFI_BT_COMMON_M) }); -} - -fn disable_phy() { // `periph_ll_wifi_bt_module_disable_clk_set_rst` - DPORT::regs() - .wifi_clk_en() - .modify(|r, w| unsafe { w.bits(r.bits() & !DPORT_WIFI_CLK_WIFI_BT_COMMON_M) }); -} - -fn bt_clock_enable() { - DPORT::regs() - .wifi_clk_en() - .modify(|r, w| unsafe { w.bits(r.bits() | DPORT_WIFI_CLK_BT_EN_M) }); + DPORT::regs().wifi_clk_en().modify(|r, w| unsafe { + if enable { + w.bits(r.bits() | DPORT_WIFI_CLK_WIFI_BT_COMMON_M) + } else { + w.bits(r.bits() & !DPORT_WIFI_CLK_WIFI_BT_COMMON_M) + } + }); } -fn bt_clock_disable() { - DPORT::regs() - .wifi_clk_en() - .modify(|r, w| unsafe { w.bits(r.bits() & !DPORT_WIFI_CLK_BT_EN_M) }); +pub(super) fn enable_bt(enable: bool) { + DPORT::regs().wifi_clk_en().modify(|r, w| unsafe { + if enable { + w.bits(r.bits() | DPORT_WIFI_CLK_BT_EN_M) + } else { + w.bits(r.bits() & !DPORT_WIFI_CLK_BT_EN_M) + } + }); } -fn wifi_clock_enable() { +pub(super) fn enable_wifi(enable: bool) { // `periph_ll_wifi_module_enable_clk_clear_rst` - DPORT::regs() - .wifi_clk_en() - .modify(|r, w| unsafe { w.bits(r.bits() | DPORT_WIFI_CLK_WIFI_EN_M) }); -} - -fn wifi_clock_disable() { // `periph_ll_wifi_module_disable_clk_set_rst` - DPORT::regs() - .wifi_clk_en() - .modify(|r, w| unsafe { w.bits(r.bits() & !DPORT_WIFI_CLK_WIFI_EN_M) }); + DPORT::regs().wifi_clk_en().modify(|r, w| unsafe { + if enable { + w.bits(r.bits() | DPORT_WIFI_CLK_WIFI_EN_M) + } else { + w.bits(r.bits() & !DPORT_WIFI_CLK_WIFI_EN_M) + } + }); } -fn reset_mac() { +pub(super) fn reset_mac() { const SYSTEM_MAC_RST: u8 = 1 << 2; DPORT::regs() .core_rst_en() @@ -347,7 +303,7 @@ fn reset_mac() { .modify(|r, w| unsafe { w.core_rst().bits(r.core_rst().bits() & !SYSTEM_MAC_RST) }); } -fn init_clocks() { +pub(super) fn init_clocks() { // esp-idf assumes all clocks are enabled by default, and disables the following // bits: // @@ -375,3 +331,11 @@ fn init_clocks() { .wifi_clk_en() .write(|w| unsafe { w.bits(u32::MAX) }); } + +pub(super) fn ble_rtc_clk_init() { + // nothing for this target +} + +pub(super) fn reset_rpa() { + // nothing for this target +} diff --git a/esp-hal/src/clock/clocks_ll/esp32c2.rs b/esp-hal/src/clock/clocks_ll/esp32c2.rs index e2168ca0748..bea0919c98e 100644 --- a/esp-hal/src/clock/clocks_ll/esp32c2.rs +++ b/esp-hal/src/clock/clocks_ll/esp32c2.rs @@ -2,7 +2,6 @@ use crate::{ clock::{ApbClock, Clock, CpuClock, PllClock, XtalClock}, peripherals::{APB_CTRL, MODEM_CLKRST}, rom::{regi2c_write, regi2c_write_mask}, - system::{RadioClockController, RadioPeripherals}, }; const I2C_BBPLL: u32 = 0x66; @@ -177,63 +176,29 @@ const SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M: u32 = 0x78078F; // SYSTEM_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 const SYSTEM_WIFI_CLK_EN: u32 = 0x00FB9FCF; -impl RadioClockController for crate::peripherals::RADIO_CLK { - fn enable(&mut self, peripheral: RadioPeripherals) { - match peripheral { - RadioPeripherals::Phy => enable_phy(), - RadioPeripherals::Bt => common_wifi_bt_clock_enable(), - RadioPeripherals::Wifi => common_wifi_bt_clock_enable(), - } - } - - fn disable(&mut self, peripheral: RadioPeripherals) { - match peripheral { - RadioPeripherals::Phy => disable_phy(), - RadioPeripherals::Bt => common_wifi_bt_clock_disable(), - RadioPeripherals::Wifi => common_wifi_bt_clock_disable(), - } - } - - fn reset_mac(&mut self) { - reset_mac(); - } - - fn init_clocks(&mut self) { - init_clocks(); - } - - fn ble_rtc_clk_init(&mut self) { - ble_rtc_clk_init(); - } - - fn reset_rpa(&mut self) { - reset_rpa(); - } -} - -fn enable_phy() { +pub(super) fn enable_phy(enable: bool) { // `periph_ll_wifi_bt_module_enable_clk_clear_rst` - APB_CTRL::regs() - .wifi_clk_en() - .modify(|r, w| unsafe { w.bits(r.bits() | SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M) }); -} - -fn disable_phy() { // `periph_ll_wifi_bt_module_disable_clk_set_rst` - APB_CTRL::regs() - .wifi_clk_en() - .modify(|r, w| unsafe { w.bits(r.bits() & !SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M) }); + APB_CTRL::regs().wifi_clk_en().modify(|r, w| unsafe { + if enable { + w.bits(r.bits() | SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M) + } else { + w.bits(r.bits() & !SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M) + } + }); } -fn common_wifi_bt_clock_enable() { +pub(super) fn enable_bt(_: bool) { // `periph_ll_wifi_module_enable_clk_clear_rst`, no-op + // `periph_ll_wifi_module_disable_clk_clear_rst`, no-op } -fn common_wifi_bt_clock_disable() { +pub(super) fn enable_wifi(_: bool) { + // `periph_ll_wifi_module_enable_clk_clear_rst`, no-op // `periph_ll_wifi_module_disable_clk_clear_rst`, no-op } -fn reset_mac() { +pub(super) fn reset_mac() { const SYSTEM_MAC_RST: u32 = 1 << 2; APB_CTRL::regs() .wifi_rst_en() @@ -243,7 +208,7 @@ fn reset_mac() { .modify(|r, w| unsafe { w.wifi_rst().bits(r.wifi_rst().bits() & !SYSTEM_MAC_RST) }); } -fn init_clocks() { +pub(super) fn init_clocks() { // from `esp_perip_clk_init` const SYSTEM_WIFI_CLK_UNUSED_BIT5: u32 = 1 << 5; const SYSTEM_WIFI_CLK_UNUSED_BIT12: u32 = 1 << 12; @@ -254,7 +219,7 @@ fn init_clocks() { .modify(|r, w| unsafe { w.bits(r.bits() & !WIFI_BT_SDIO_CLK | SYSTEM_WIFI_CLK_EN) }); } -fn ble_rtc_clk_init() { +pub(super) fn ble_rtc_clk_init() { let modem_clkrst = MODEM_CLKRST::regs(); modem_clkrst .modem_lp_timer_conf() @@ -282,7 +247,7 @@ fn ble_rtc_clk_init() { .modify(|_, w| w.etm_clk_sel().clear_bit()); } -fn reset_rpa() { +pub(super) fn reset_rpa() { const BLE_RPA_REST_BIT: u32 = 1 << 27; APB_CTRL::regs() .wifi_rst_en() diff --git a/esp-hal/src/clock/clocks_ll/esp32c3.rs b/esp-hal/src/clock/clocks_ll/esp32c3.rs index 29c74a90c07..57d5a6e5dd8 100644 --- a/esp-hal/src/clock/clocks_ll/esp32c3.rs +++ b/esp-hal/src/clock/clocks_ll/esp32c3.rs @@ -2,7 +2,6 @@ use crate::{ clock::{ApbClock, Clock, CpuClock, PllClock, XtalClock}, peripherals::{APB_CTRL, LPWR}, rom::{regi2c_write, regi2c_write_mask}, - system::{RadioClockController, RadioPeripherals}, }; const I2C_BBPLL: u32 = 0x66; @@ -237,63 +236,29 @@ const SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M: u32 = 0x78078F; // SYSTEM_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 const SYSTEM_WIFI_CLK_EN: u32 = 0x00FB9FCF; -impl RadioClockController for crate::peripherals::RADIO_CLK { - fn enable(&mut self, peripheral: RadioPeripherals) { - match peripheral { - RadioPeripherals::Phy => enable_phy(), - RadioPeripherals::Bt => common_wifi_bt_clock_enable(), - RadioPeripherals::Wifi => common_wifi_bt_clock_enable(), - } - } - - fn disable(&mut self, peripheral: RadioPeripherals) { - match peripheral { - RadioPeripherals::Phy => disable_phy(), - RadioPeripherals::Bt => common_wifi_bt_clock_disable(), - RadioPeripherals::Wifi => common_wifi_bt_clock_disable(), - } - } - - fn reset_mac(&mut self) { - reset_mac(); - } - - fn init_clocks(&mut self) { - init_clocks(); - } - - fn ble_rtc_clk_init(&mut self) { - // nothing for this target - } - - fn reset_rpa(&mut self) { - // nothing for this target - } -} - -fn enable_phy() { +pub(super) fn enable_phy(enable: bool) { // `periph_ll_wifi_bt_module_enable_clk_clear_rst` - APB_CTRL::regs() - .wifi_clk_en() - .modify(|r, w| unsafe { w.bits(r.bits() | SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M) }); -} - -fn disable_phy() { // `periph_ll_wifi_bt_module_disable_clk_set_rst` - APB_CTRL::regs() - .wifi_clk_en() - .modify(|r, w| unsafe { w.bits(r.bits() & !SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M) }); + APB_CTRL::regs().wifi_clk_en().modify(|r, w| unsafe { + if enable { + w.bits(r.bits() | SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M) + } else { + w.bits(r.bits() & !SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M) + } + }); } -fn common_wifi_bt_clock_enable() { +pub(super) fn enable_wifi(_: bool) { // `periph_ll_wifi_module_enable_clk_clear_rst`, no-op + // `periph_ll_wifi_module__clk_clear_rst`, no-op } -fn common_wifi_bt_clock_disable() { +pub(super) fn enable_bt(_: bool) { + // `periph_ll_wifi_module_enable_clk_clear_rst`, no-op // `periph_ll_wifi_module__clk_clear_rst`, no-op } -fn reset_mac() { +pub(super) fn reset_mac() { const SYSTEM_MAC_RST: u32 = 1 << 2; APB_CTRL::regs() .wifi_rst_en() @@ -303,7 +268,7 @@ fn reset_mac() { .modify(|r, w| unsafe { w.wifi_rst().bits(r.wifi_rst().bits() & !SYSTEM_MAC_RST) }); } -fn init_clocks() { +pub(super) fn init_clocks() { // undo the power down in base_settings (esp32c3_sleep) LPWR::regs() .dig_iso() @@ -322,3 +287,11 @@ fn init_clocks() { .wifi_clk_en() .modify(|r, w| unsafe { w.bits(r.bits() & !WIFI_BT_SDIO_CLK | SYSTEM_WIFI_CLK_EN) }); } + +pub(super) fn ble_rtc_clk_init() { + // nothing for this target +} + +pub(super) fn reset_rpa() { + // nothing for this target +} diff --git a/esp-hal/src/clock/clocks_ll/esp32c6.rs b/esp-hal/src/clock/clocks_ll/esp32c6.rs index ffc2249132f..503b31804c7 100644 --- a/esp-hal/src/clock/clocks_ll/esp32c6.rs +++ b/esp-hal/src/clock/clocks_ll/esp32c6.rs @@ -2,7 +2,6 @@ use crate::{ clock::{ApbClock, Clock, CpuClock, PllClock, XtalClock}, peripherals::{MODEM_LPCON, MODEM_SYSCON, PMU}, rtc_cntl::rtc::CpuClockSource, - system::{RadioClockController, RadioPeripherals}, }; const I2C_BBPLL: u8 = 0x66; @@ -450,43 +449,7 @@ pub(crate) fn esp32c6_bbpll_get_freq_mhz() -> u32 { CLK_LL_PLL_480M_FREQ_MHZ } -impl RadioClockController for crate::peripherals::RADIO_CLK { - fn enable(&mut self, peripheral: RadioPeripherals) { - match peripheral { - RadioPeripherals::Phy => enable_phy(true), - RadioPeripherals::Wifi => wifi_clock_enable(true), - RadioPeripherals::Bt => ble_clock_enable(true), - RadioPeripherals::Ieee802154 => ieee802154_clock_enable(true), - } - } - - fn disable(&mut self, peripheral: RadioPeripherals) { - match peripheral { - RadioPeripherals::Phy => enable_phy(false), - RadioPeripherals::Wifi => wifi_clock_enable(false), - RadioPeripherals::Bt => ble_clock_enable(false), - RadioPeripherals::Ieee802154 => ieee802154_clock_enable(false), - } - } - - fn reset_mac(&mut self) { - reset_mac(); - } - - fn init_clocks(&mut self) { - init_clocks(); - } - - fn ble_rtc_clk_init(&mut self) { - // nothing for this target (yet) - } - - fn reset_rpa(&mut self) { - // nothing for this target (yet) - } -} - -fn enable_phy(en: bool) { +pub(super) fn enable_phy(en: bool) { MODEM_LPCON::regs() .clk_conf() .modify(|_, w| w.clk_i2c_mst_en().bit(en)); @@ -495,7 +458,7 @@ fn enable_phy(en: bool) { .modify(|_, w| w.clk_i2c_mst_sel_160m().bit(en)); } -fn wifi_clock_enable(en: bool) { +pub(super) fn enable_wifi(en: bool) { MODEM_SYSCON::regs().clk_conf1().modify(|_, w| { w.clk_wifi_apb_en().bit(en); w.clk_wifimac_en().bit(en); @@ -520,7 +483,7 @@ fn wifi_clock_enable(en: bool) { }); } -fn ieee802154_clock_enable(en: bool) { +pub(super) fn enable_ieee802154(en: bool) { MODEM_SYSCON::regs().clk_conf().modify(|_, w| { w.clk_zb_apb_en().bit(en); w.clk_zb_mac_en().bit(en) @@ -549,7 +512,7 @@ fn ieee802154_clock_enable(en: bool) { .modify(|_, w| w.clk_coex_en().set_bit()); } -fn ble_clock_enable(en: bool) { +pub(super) fn enable_bt(en: bool) { MODEM_SYSCON::regs().clk_conf().modify(|_, w| { w.clk_etm_en().bit(en); w.clk_modem_sec_en().bit(en); @@ -574,11 +537,11 @@ fn ble_clock_enable(en: bool) { .modify(|_, w| w.clk_coex_en().bit(en)); } -fn reset_mac() { +pub(super) fn reset_mac() { // empty } -fn init_clocks() { +pub(super) fn init_clocks() { unsafe { let pmu = PMU::regs(); @@ -639,3 +602,11 @@ fn init_clocks() { .modify(|_, w| w.clk_wifipwr_en().set_bit()); } } + +pub(super) fn ble_rtc_clk_init() { + // nothing for this target (yet) +} + +pub(super) fn reset_rpa() { + // nothing for this target (yet) +} diff --git a/esp-hal/src/clock/clocks_ll/esp32h2.rs b/esp-hal/src/clock/clocks_ll/esp32h2.rs index 6bad0a92d22..c7e9f482cb6 100644 --- a/esp-hal/src/clock/clocks_ll/esp32h2.rs +++ b/esp-hal/src/clock/clocks_ll/esp32h2.rs @@ -1,7 +1,6 @@ use crate::{ clock::{ApbClock, Clock, CpuClock, PllClock, XtalClock}, peripherals::{LP_AON, MODEM_LPCON, MODEM_SYSCON, PCR, PMU}, - system::{RadioClockController, RadioPeripherals}, }; const I2C_BBPLL: u8 = 0x66; @@ -326,43 +325,7 @@ pub(crate) fn regi2c_write_mask(block: u8, _host_id: u8, reg_add: u8, msb: u8, l regi2c_disable_block(block); } -impl RadioClockController for crate::peripherals::RADIO_CLK { - fn enable(&mut self, peripheral: RadioPeripherals) { - match peripheral { - RadioPeripherals::Phy => enable_phy(true), - RadioPeripherals::Bt | RadioPeripherals::Ieee802154 => { - ble_ieee802154_clock_enable(true) - } - } - } - - fn disable(&mut self, peripheral: RadioPeripherals) { - match peripheral { - RadioPeripherals::Phy => enable_phy(false), - RadioPeripherals::Bt | RadioPeripherals::Ieee802154 => { - ble_ieee802154_clock_enable(false) - } - } - } - - fn reset_mac(&mut self) { - reset_mac(); - } - - fn init_clocks(&mut self) { - init_clocks(); - } - - fn ble_rtc_clk_init(&mut self) { - // nothing for this target (yet) - } - - fn reset_rpa(&mut self) { - // nothing for this target (yet) - } -} - -fn enable_phy(en: bool) { +pub(super) fn enable_phy(en: bool) { MODEM_LPCON::regs() .clk_conf() .modify(|_, w| w.clk_i2c_mst_en().bit(en)); @@ -389,11 +352,19 @@ fn ble_ieee802154_clock_enable(en: bool) { .modify(|_, w| w.clk_coex_en().bit(en)); } -fn reset_mac() { +pub(super) fn enable_bt(en: bool) { + ble_ieee802154_clock_enable(en); +} + +pub(super) fn enable_ieee802154(en: bool) { + ble_ieee802154_clock_enable(en); +} + +pub(super) fn reset_mac() { // empty } -fn init_clocks() { +pub(super) fn init_clocks() { unsafe { let pmu = PMU::regs(); @@ -418,3 +389,11 @@ fn init_clocks() { }); } } + +pub(super) fn ble_rtc_clk_init() { + // nothing for this target (yet) +} + +pub(super) fn reset_rpa() { + // nothing for this target (yet) +} diff --git a/esp-hal/src/clock/clocks_ll/esp32s2.rs b/esp-hal/src/clock/clocks_ll/esp32s2.rs index 62a07f73700..46fa4ebf431 100644 --- a/esp-hal/src/clock/clocks_ll/esp32s2.rs +++ b/esp-hal/src/clock/clocks_ll/esp32s2.rs @@ -1,8 +1,4 @@ -use crate::{ - clock::CpuClock, - peripherals::SYSCON, - system::{RadioClockController, RadioPeripherals}, -}; +use crate::{clock::CpuClock, peripherals::SYSCON}; const MHZ: u32 = 1000000; const UINT16_MAX: u32 = 0xffff; @@ -51,67 +47,31 @@ pub(crate) fn set_cpu_clock(cpu_clock_speed: CpuClock) { const DPORT_WIFI_CLK_WIFI_BT_COMMON_M: u32 = 0x000003c9; const DPORT_WIFI_CLK_WIFI_EN_M: u32 = 0x000007cf; -impl RadioClockController for crate::peripherals::RADIO_CLK { - fn enable(&mut self, peripheral: RadioPeripherals) { - match peripheral { - RadioPeripherals::Phy => enable_phy(), - RadioPeripherals::Wifi => wifi_clock_enable(), - } - } - - fn disable(&mut self, peripheral: RadioPeripherals) { - match peripheral { - RadioPeripherals::Phy => disable_phy(), - RadioPeripherals::Wifi => wifi_clock_disable(), - } - } - - fn reset_mac(&mut self) { - reset_mac(); - } - - fn init_clocks(&mut self) { - init_clocks(); - } - - fn ble_rtc_clk_init(&mut self) { - // nothing for this target - } - - fn reset_rpa(&mut self) { - // nothing for this target - } -} - -fn enable_phy() { +pub(super) fn enable_phy(enable: bool) { // `periph_ll_wifi_bt_module_enable_clk_clear_rst` - SYSCON::regs() - .wifi_clk_en() - .modify(|r, w| unsafe { w.bits(r.bits() | DPORT_WIFI_CLK_WIFI_BT_COMMON_M) }); -} - -fn disable_phy() { // `periph_ll_wifi_bt_module_disable_clk_set_rst` - SYSCON::regs() - .wifi_clk_en() - .modify(|r, w| unsafe { w.bits(r.bits() & !DPORT_WIFI_CLK_WIFI_BT_COMMON_M) }); + SYSCON::regs().wifi_clk_en().modify(|r, w| unsafe { + if enable { + w.bits(r.bits() | DPORT_WIFI_CLK_WIFI_BT_COMMON_M) + } else { + w.bits(r.bits() & !DPORT_WIFI_CLK_WIFI_BT_COMMON_M) + } + }); } -fn wifi_clock_enable() { +pub(super) fn enable_wifi(enable: bool) { // `periph_ll_wifi_module_enable_clk_clear_rst` - SYSCON::regs() - .wifi_clk_en() - .modify(|r, w| unsafe { w.bits(r.bits() | DPORT_WIFI_CLK_WIFI_EN_M) }); -} - -fn wifi_clock_disable() { // `periph_ll_wifi_module_disable_clk_set_rst` - SYSCON::regs() - .wifi_clk_en() - .modify(|r, w| unsafe { w.bits(r.bits() & !DPORT_WIFI_CLK_WIFI_EN_M) }); + SYSCON::regs().wifi_clk_en().modify(|r, w| unsafe { + if enable { + w.bits(r.bits() | DPORT_WIFI_CLK_WIFI_EN_M) + } else { + w.bits(r.bits() & !DPORT_WIFI_CLK_WIFI_EN_M) + } + }); } -fn reset_mac() { +pub(super) fn reset_mac() { const SYSTEM_MAC_RST: u32 = 1 << 2; SYSCON::regs() .wifi_rst_en() @@ -121,7 +81,7 @@ fn reset_mac() { .modify(|r, w| unsafe { w.wifi_rst().bits(r.wifi_rst().bits() & !SYSTEM_MAC_RST) }); } -fn init_clocks() { +pub(super) fn init_clocks() { const DPORT_WIFI_CLK_WIFI_EN: u32 = 0x003807cf; const DPORT_WIFI_CLK_BT_EN_M: u32 = 0x61 << 11; const DPORT_WIFI_CLK_SDIOSLAVE_EN: u32 = 1 << 4; @@ -142,3 +102,11 @@ fn init_clocks() { .wifi_clk_en() .modify(|r, w| unsafe { w.bits(r.bits() & !WIFI_BT_SDIO_CLK | DPORT_WIFI_CLK_WIFI_EN) }); } + +pub(super) fn ble_rtc_clk_init() { + // nothing for this target +} + +pub(super) fn reset_rpa() { + // nothing for this target +} diff --git a/esp-hal/src/clock/clocks_ll/esp32s3.rs b/esp-hal/src/clock/clocks_ll/esp32s3.rs index 2f3fb2eb086..20e279ddfd1 100644 --- a/esp-hal/src/clock/clocks_ll/esp32s3.rs +++ b/esp-hal/src/clock/clocks_ll/esp32s3.rs @@ -2,7 +2,6 @@ use crate::{ clock::{Clock, CpuClock}, peripherals::APB_CTRL, rom, - system::{RadioClockController, RadioPeripherals}, }; pub(crate) fn set_cpu_clock(cpu_clock_speed: CpuClock) { @@ -35,63 +34,29 @@ const SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M: u32 = 0x78078F; // SYSTEM_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 const SYSTEM_WIFI_CLK_EN: u32 = 0x00FB9FCF; -impl RadioClockController for crate::peripherals::RADIO_CLK { - fn enable(&mut self, peripheral: RadioPeripherals) { - match peripheral { - RadioPeripherals::Phy => enable_phy(), - RadioPeripherals::Bt => common_wifi_bt_clock_enable(), - RadioPeripherals::Wifi => common_wifi_bt_clock_enable(), - } - } - - fn disable(&mut self, peripheral: RadioPeripherals) { - match peripheral { - RadioPeripherals::Phy => disable_phy(), - RadioPeripherals::Bt => common_wifi_bt_clock_disable(), - RadioPeripherals::Wifi => common_wifi_bt_clock_disable(), - } - } - - fn reset_mac(&mut self) { - reset_mac(); - } - - fn init_clocks(&mut self) { - init_clocks(); - } - - fn ble_rtc_clk_init(&mut self) { - // nothing for this target - } - - fn reset_rpa(&mut self) { - // nothing for this target - } -} - -fn enable_phy() { +pub(super) fn enable_phy(enable: bool) { // `periph_ll_wifi_bt_module_enable_clk_clear_rst` - APB_CTRL::regs() - .wifi_clk_en() - .modify(|r, w| unsafe { w.bits(r.bits() | SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M) }); -} - -fn disable_phy() { // `periph_ll_wifi_bt_module_disable_clk_set_rst` - APB_CTRL::regs() - .wifi_clk_en() - .modify(|r, w| unsafe { w.bits(r.bits() & !SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M) }); + APB_CTRL::regs().wifi_clk_en().modify(|r, w| unsafe { + if enable { + w.bits(r.bits() | SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M) + } else { + w.bits(r.bits() & !SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M) + } + }); } -fn common_wifi_bt_clock_enable() { +pub(super) fn enable_bt(_: bool) { // `periph_ll_wifi_module_enable_clk_clear_rst`. does nothing + // `periph_ll_wifi_module_disable_clk_set_rst`. does nothing } -fn common_wifi_bt_clock_disable() { +pub(super) fn enable_wifi(_: bool) { + // `periph_ll_wifi_module_enable_clk_clear_rst`. does nothing // `periph_ll_wifi_module_disable_clk_set_rst`. does nothing } -fn reset_mac() { +pub(super) fn reset_mac() { const SYSTEM_MAC_RST: u32 = 1 << 2; APB_CTRL::regs() .wifi_rst_en() @@ -101,7 +66,7 @@ fn reset_mac() { .modify(|r, w| unsafe { w.bits(r.bits() & !SYSTEM_MAC_RST) }); } -fn init_clocks() { +pub(super) fn init_clocks() { const SYSTEM_WIFI_CLK_I2C_CLK_EN: u32 = 1 << 5; const SYSTEM_WIFI_CLK_UNUSED_BIT12: u32 = 1 << 12; const SYSTEM_WIFI_CLK_SDIO_HOST_EN: u32 = 1 << 13; @@ -113,3 +78,11 @@ fn init_clocks() { .wifi_clk_en() .modify(|r, w| unsafe { w.bits(r.bits() & !WIFI_BT_SDIO_CLK | SYSTEM_WIFI_CLK_EN) }); } + +pub(super) fn ble_rtc_clk_init() { + // nothing for this target +} + +pub(super) fn reset_rpa() { + // nothing for this target +} diff --git a/esp-hal/src/clock/mod.rs b/esp-hal/src/clock/mod.rs index f6ed0c5bb6e..906faa9be0d 100644 --- a/esp-hal/src/clock/mod.rs +++ b/esp-hal/src/clock/mod.rs @@ -46,7 +46,10 @@ #[cfg(any(esp32, esp32c2))] use crate::rtc_cntl::RtcClock; -use crate::time::Rate; +use crate::{ + peripheral::{Peripheral, PeripheralRef}, + time::Rate, +}; #[cfg_attr(esp32, path = "clocks_ll/esp32.rs")] #[cfg_attr(esp32c2, path = "clocks_ll/esp32c2.rs")] @@ -564,3 +567,80 @@ impl Clocks { } } } + +/// Control the radio peripheral clocks +#[cfg(any(bt, ieee802154, wifi))] +#[instability::unstable] +pub struct RadioClockController<'d> { + _rcc: PeripheralRef<'d, crate::peripherals::RADIO_CLK>, +} + +#[cfg(any(bt, ieee802154, wifi))] +impl<'d> RadioClockController<'d> { + /// Create a new instance of the radio clock controller + #[instability::unstable] + pub fn new(rcc: impl Peripheral

+ 'd) -> Self { + crate::into_ref!(rcc); + Self { _rcc: rcc } + } + + /// Enable the PHY clocks + #[instability::unstable] + #[cfg(phy)] + #[inline] + pub fn enable_phy(&mut self, enable: bool) { + clocks_ll::enable_phy(enable); + } + + /// Enable the Bluetooth clocks + #[instability::unstable] + #[cfg(bt)] + #[inline] + pub fn enable_bt(&mut self, enable: bool) { + clocks_ll::enable_bt(enable); + } + + /// Enable the WiFi clocks + #[instability::unstable] + #[cfg(wifi)] + #[inline] + pub fn enable_wifi(&mut self, enable: bool) { + clocks_ll::enable_wifi(enable); + } + + /// Enable the IEEE 802.15.4 peripheral clocks + #[instability::unstable] + #[cfg(ieee802154)] + #[inline] + pub fn enable_ieee802154(&mut self, enable: bool) { + clocks_ll::enable_ieee802154(enable); + } + + /// Reset the MAC + #[instability::unstable] + #[inline] + pub fn reset_mac(&mut self) { + clocks_ll::reset_mac(); + } + + /// Do any common initial initialization needed + #[instability::unstable] + #[inline] + pub fn init_clocks(&mut self) { + clocks_ll::init_clocks(); + } + + /// Initialize BLE RTC clocks + #[instability::unstable] + #[inline] + pub fn ble_rtc_clk_init(&mut self) { + clocks_ll::ble_rtc_clk_init(); + } + + /// Reset the Resolvable Private Address (RPA). + #[instability::unstable] + #[inline] + pub fn reset_rpa(&mut self) { + clocks_ll::reset_rpa(); + } +} diff --git a/esp-hal/src/rtc_cntl/rtc/esp32c6.rs b/esp-hal/src/rtc_cntl/rtc/esp32c6.rs index 32ff75c61e5..ec148c8b676 100644 --- a/esp-hal/src/rtc_cntl/rtc/esp32c6.rs +++ b/esp-hal/src/rtc_cntl/rtc/esp32c6.rs @@ -22,7 +22,6 @@ use crate::{ peripherals::TIMG0, rtc_cntl::RtcClock, soc::efuse::Efuse, - system::RadioPeripherals, time::Rate, }; @@ -311,22 +310,12 @@ fn modem_clock_hal_enable_wifipwr_clock(enable: bool) { } } -fn modem_clock_select_lp_clock_source( - periph: RadioPeripherals, - src: ModemClockLpclkSource, - divider: u16, -) { - match periph { - RadioPeripherals::Wifi => { - modem_clock_hal_deselect_all_wifi_lpclk_source(); - modem_clock_hal_select_wifi_lpclk_source(src); - modem_lpcon_ll_set_wifi_lpclk_divisor_value(divider); - modem_clock_hal_enable_wifipwr_clock(true); - } - RadioPeripherals::Phy | RadioPeripherals::Bt | RadioPeripherals::Ieee802154 => { - todo!("unused by setup code") - } - } +// PHY, BT, IEEE802154 are not used by the init code so they are unimplemented +fn modem_clock_select_lp_clock_source_wifi(src: ModemClockLpclkSource, divider: u16) { + modem_clock_hal_deselect_all_wifi_lpclk_source(); + modem_clock_hal_select_wifi_lpclk_source(src); + modem_lpcon_ll_set_wifi_lpclk_divisor_value(divider); + modem_clock_hal_enable_wifipwr_clock(true); } const fn hp_retention_regdma_config(dir: u8, entry: u8) -> u8 { @@ -1196,7 +1185,7 @@ pub(crate) fn init() { // TODO - WIFI-5233 let modem_lpclk_src = ModemClockLpclkSource::from(RtcSlowClockSource::current()); - modem_clock_select_lp_clock_source(RadioPeripherals::Wifi, modem_lpclk_src, 0); + modem_clock_select_lp_clock_source_wifi(modem_lpclk_src, 0); } pub(crate) fn configure_clock() { diff --git a/esp-hal/src/system.rs b/esp-hal/src/system.rs index 36573389484..cb91f854d8c 100755 --- a/esp-hal/src/system.rs +++ b/esp-hal/src/system.rs @@ -1092,42 +1092,3 @@ impl PeripheralClockControl { true } } - -/// Enumeration of the available radio peripherals for this chip. -#[cfg(any(bt, ieee802154, wifi))] -pub enum RadioPeripherals { - /// Represents the PHY (Physical Layer) peripheral. - #[cfg(phy)] - Phy, - /// Represents the Bluetooth peripheral. - #[cfg(bt)] - Bt, - /// Represents the WiFi peripheral. - #[cfg(wifi)] - Wifi, - /// Represents the IEEE 802.15.4 peripheral. - #[cfg(ieee802154)] - Ieee802154, -} - -/// Control the radio peripheral clocks -#[cfg(any(bt, ieee802154, wifi))] -pub trait RadioClockController { - /// Enable the peripheral - fn enable(&mut self, peripheral: RadioPeripherals); - - /// Disable the peripheral - fn disable(&mut self, peripheral: RadioPeripherals); - - /// Reset the MAC - fn reset_mac(&mut self); - - /// Do any common initial initialization needed - fn init_clocks(&mut self); - - /// Initialize BLE RTC clocks - fn ble_rtc_clk_init(&mut self); - - /// Reset the Resolvable Private Address (RPA). - fn reset_rpa(&mut self); -} diff --git a/esp-wifi/src/ble/os_adapter_esp32c2.rs b/esp-wifi/src/ble/os_adapter_esp32c2.rs index 188709b90b5..7821f6ec24f 100644 --- a/esp-wifi/src/ble/os_adapter_esp32c2.rs +++ b/esp-wifi/src/ble/os_adapter_esp32c2.rs @@ -1,6 +1,10 @@ use crate::{ binary::include::esp_bt_controller_config_t, - hal::{interrupt, peripherals::Interrupt, system::RadioClockController}, + hal::{ + clock::RadioClockController, + interrupt, + peripherals::{Interrupt, RADIO_CLK}, + }, }; pub(crate) static mut ISR_INTERRUPT_4: ( @@ -116,14 +120,14 @@ pub(super) unsafe extern "C" fn esp_intr_alloc( pub(super) fn ble_rtc_clk_init() { // stealing RADIO_CLK is safe since it is passed (as mutable reference or by // value) into `init` - let mut radio_clocks = unsafe { esp_hal::peripherals::RADIO_CLK::steal() }; - radio_clocks.ble_rtc_clk_init(); + let radio_clocks = unsafe { RADIO_CLK::steal() }; + RadioClockController::new(radio_clocks).ble_rtc_clk_init(); } pub(super) unsafe extern "C" fn esp_reset_rpa_moudle() { trace!("esp_reset_rpa_moudle"); // stealing RADIO_CLK is safe since it is passed (as mutable reference or by // value) into `init` - let mut radio_clocks = unsafe { esp_hal::peripherals::RADIO_CLK::steal() }; - radio_clocks.reset_rpa(); + let radio_clocks = unsafe { RADIO_CLK::steal() }; + RadioClockController::new(radio_clocks).reset_rpa(); } diff --git a/esp-wifi/src/ble/os_adapter_esp32c6.rs b/esp-wifi/src/ble/os_adapter_esp32c6.rs index 34ab33ccb46..6c3efe77653 100644 --- a/esp-wifi/src/ble/os_adapter_esp32c6.rs +++ b/esp-wifi/src/ble/os_adapter_esp32c6.rs @@ -1,9 +1,9 @@ use crate::{ binary::include::esp_bt_controller_config_t, hal::{ + clock::RadioClockController, interrupt, - peripherals::Interrupt, - system::{RadioClockController, RadioPeripherals}, + peripherals::{Interrupt, RADIO_CLK}, }, }; @@ -71,8 +71,8 @@ pub(crate) static BLE_CONFIG: esp_bt_controller_config_t = esp_bt_controller_con pub(crate) fn bt_periph_module_enable() { // stealing RADIO_CLK is safe since it is passed (as mutable reference or by // value) into `init` - let mut radio_clocks = unsafe { esp_hal::peripherals::RADIO_CLK::steal() }; - radio_clocks.enable(RadioPeripherals::Bt); + let radio_clocks = unsafe { RADIO_CLK::steal() }; + RadioClockController::new(radio_clocks).enable_bt(true); } pub(crate) fn disable_sleep_mode() { @@ -119,16 +119,16 @@ pub(super) unsafe extern "C" fn esp_intr_alloc( pub(super) fn ble_rtc_clk_init() { // stealing RADIO_CLK is safe since it is passed (as mutable reference or by // value) into `init` - let mut radio_clocks = unsafe { esp_hal::peripherals::RADIO_CLK::steal() }; - radio_clocks.ble_rtc_clk_init(); + let radio_clocks = unsafe { RADIO_CLK::steal() }; + RadioClockController::new(radio_clocks).ble_rtc_clk_init(); } pub(super) unsafe extern "C" fn esp_reset_rpa_moudle() { trace!("esp_reset_rpa_moudle"); // stealing RADIO_CLK is safe since it is passed (as mutable reference or by // value) into `init` - let mut radio_clocks = unsafe { esp_hal::peripherals::RADIO_CLK::steal() }; - radio_clocks.reset_rpa(); + let radio_clocks = unsafe { RADIO_CLK::steal() }; + RadioClockController::new(radio_clocks).reset_rpa(); } #[allow(improper_ctypes_definitions)] diff --git a/esp-wifi/src/ble/os_adapter_esp32h2.rs b/esp-wifi/src/ble/os_adapter_esp32h2.rs index 4d19ec5db6c..35d9667747d 100644 --- a/esp-wifi/src/ble/os_adapter_esp32h2.rs +++ b/esp-wifi/src/ble/os_adapter_esp32h2.rs @@ -1,9 +1,9 @@ use crate::{ binary::include::esp_bt_controller_config_t, hal::{ + clock::RadioClockController, interrupt, - peripherals::Interrupt, - system::{RadioClockController, RadioPeripherals}, + peripherals::{Interrupt, RADIO_CLK}, }, }; @@ -71,8 +71,8 @@ pub(crate) static BLE_CONFIG: esp_bt_controller_config_t = esp_bt_controller_con pub(crate) fn bt_periph_module_enable() { // stealing RADIO_CLK is safe since it is passed (as mutable reference or by // value) into `init` - let mut radio_clocks = unsafe { esp_hal::peripherals::RADIO_CLK::steal() }; - radio_clocks.enable(RadioPeripherals::Bt); + let radio_clocks = unsafe { RADIO_CLK::steal() }; + RadioClockController::new(radio_clocks).enable_bt(true); } pub(crate) fn disable_sleep_mode() { @@ -119,16 +119,16 @@ pub(super) unsafe extern "C" fn esp_intr_alloc( pub(super) fn ble_rtc_clk_init() { // stealing RADIO_CLK is safe since it is passed (as reference or by value) into // `init` - let mut radio_clocks = unsafe { esp_hal::peripherals::RADIO_CLK::steal() }; - radio_clocks.ble_rtc_clk_init(); + let radio_clocks = unsafe { RADIO_CLK::steal() }; + RadioClockController::new(radio_clocks).ble_rtc_clk_init(); } pub(super) unsafe extern "C" fn esp_reset_rpa_moudle() { trace!("esp_reset_rpa_moudle"); // stealing RADIO_CLK is safe since it is passed (as mutable reference or by // value) into `init` - let mut radio_clocks = unsafe { esp_hal::peripherals::RADIO_CLK::steal() }; - radio_clocks.reset_rpa(); + let radio_clocks = unsafe { RADIO_CLK::steal() }; + RadioClockController::new(radio_clocks).reset_rpa(); } #[allow(improper_ctypes_definitions)] diff --git a/esp-wifi/src/common_adapter/common_adapter_esp32.rs b/esp-wifi/src/common_adapter/common_adapter_esp32.rs index f9596bad80b..826e672a637 100644 --- a/esp-wifi/src/common_adapter/common_adapter_esp32.rs +++ b/esp-wifi/src/common_adapter/common_adapter_esp32.rs @@ -3,10 +3,7 @@ use portable_atomic::{AtomicU32, Ordering}; use super::phy_init_data::PHY_INIT_DATA_DEFAULT; use crate::{ binary::include::*, - hal::{ - ram, - system::{RadioClockController, RadioPeripherals}, - }, + hal::{peripherals::LPWR, ram}, }; const SOC_PHY_DIG_REGS_MEM_SIZE: usize = 21 * 4; @@ -16,20 +13,15 @@ static mut G_IS_PHY_CALIBRATED: bool = false; static mut G_PHY_DIGITAL_REGS_MEM: *mut u32 = core::ptr::null_mut(); static mut S_IS_PHY_REG_STORED: bool = false; static PHY_ACCESS_REF: AtomicU32 = AtomicU32::new(0); -static PHY_CLOCK_ENABLE_REF: AtomicU32 = AtomicU32::new(0); pub(crate) fn enable_wifi_power_domain() { - unsafe { - let rtc_cntl = &*crate::hal::peripherals::LPWR::ptr(); - - rtc_cntl - .dig_pwc() - .modify(|_, w| w.wifi_force_pd().clear_bit()); + LPWR::regs() + .dig_pwc() + .modify(|_, w| w.wifi_force_pd().clear_bit()); - rtc_cntl - .dig_iso() - .modify(|_, w| w.wifi_force_iso().clear_bit()); - } + LPWR::regs() + .dig_iso() + .modify(|_, w| w.wifi_force_iso().clear_bit()); } pub(crate) fn phy_mem_init() { @@ -49,7 +41,7 @@ pub(crate) unsafe fn phy_enable() { // phy_update_wifi_mac_time(false, s_phy_rf_en_ts); // #endif - phy_enable_clock(); + super::phy_enable_clock(); if !G_IS_PHY_CALIBRATED { let mut cal_data: [u8; core::mem::size_of::()] = @@ -94,7 +86,7 @@ pub(crate) unsafe fn phy_disable() { // Disable WiFi/BT common peripheral clock. Do not disable clock for hardware // RNG - phy_disable_clock(); + super::phy_disable_clock(); trace!("PHY DISABLE"); }); } @@ -117,31 +109,6 @@ fn phy_digital_regs_store() { } } -pub(crate) unsafe fn phy_enable_clock() { - trace!("phy_enable_clock"); - - let count = PHY_CLOCK_ENABLE_REF.fetch_add(1, Ordering::SeqCst); - if count == 0 { - // stealing RADIO_CLK is safe since it is passed (as mutable reference or by - // value) into `init` - let mut radio_clocks = unsafe { esp_hal::peripherals::RADIO_CLK::steal() }; - radio_clocks.enable(RadioPeripherals::Phy); - } -} - -#[allow(unused)] -pub(crate) unsafe fn phy_disable_clock() { - trace!("phy_disable_clock"); - - let count = PHY_CLOCK_ENABLE_REF.fetch_sub(1, Ordering::SeqCst); - if count == 1 { - // stealing RADIO_CLK is safe since it is passed (as mutable reference or by - // value) into `init` - let mut radio_clocks = unsafe { esp_hal::peripherals::RADIO_CLK::steal() }; - radio_clocks.disable(RadioPeripherals::Phy); - } -} - /// ************************************************************************** /// Name: esp_dport_access_reg_read /// diff --git a/esp-wifi/src/common_adapter/common_adapter_esp32c2.rs b/esp-wifi/src/common_adapter/common_adapter_esp32c2.rs index 99a8f74da20..911db6b3ddf 100644 --- a/esp-wifi/src/common_adapter/common_adapter_esp32c2.rs +++ b/esp-wifi/src/common_adapter/common_adapter_esp32c2.rs @@ -1,11 +1,7 @@ use portable_atomic::{AtomicU32, Ordering}; use super::phy_init_data::PHY_INIT_DATA_DEFAULT; -use crate::{ - binary::include::*, - compat::common::str_from_c, - hal::system::{RadioClockController, RadioPeripherals}, -}; +use crate::{binary::include::*, compat::common::str_from_c}; const SOC_PHY_DIG_REGS_MEM_SIZE: usize = 21 * 4; @@ -30,7 +26,7 @@ pub(crate) unsafe fn phy_enable() { let count = PHY_ACCESS_REF.fetch_add(1, Ordering::SeqCst); if count == 0 { critical_section::with(|_| { - phy_enable_clock(); + super::phy_enable_clock(); if !G_IS_PHY_CALIBRATED { let mut cal_data: [u8; core::mem::size_of::()] = @@ -88,7 +84,7 @@ pub(crate) unsafe fn phy_disable() { // Disable WiFi/BT common peripheral clock. Do not disable clock for hardware // RNG - phy_disable_clock(); + super::phy_disable_clock(); trace!("PHY DISABLE"); }); } @@ -110,24 +106,3 @@ fn phy_digital_regs_store() { } } } - -pub(crate) unsafe fn phy_enable_clock() { - trace!("phy_enable_clock"); - // stealing RADIO_CLK is safe since it is passed (as mutable reference or by - // value) into `init` - let mut radio_clocks = unsafe { esp_hal::peripherals::RADIO_CLK::steal() }; - radio_clocks.enable(RadioPeripherals::Phy); - - trace!("phy_enable_clock done!"); -} - -#[allow(unused)] -pub(crate) unsafe fn phy_disable_clock() { - trace!("phy_disable_clock"); - // stealing RADIO_CLK is safe since it is passed (as mutable reference or by - // value) into `init` - let mut radio_clocks = unsafe { esp_hal::peripherals::RADIO_CLK::steal() }; - radio_clocks.disable(RadioPeripherals::Phy); - - trace!("phy_disable_clock done!"); -} diff --git a/esp-wifi/src/common_adapter/common_adapter_esp32c3.rs b/esp-wifi/src/common_adapter/common_adapter_esp32c3.rs index eaa7903a1fe..f5e8dfc425a 100644 --- a/esp-wifi/src/common_adapter/common_adapter_esp32c3.rs +++ b/esp-wifi/src/common_adapter/common_adapter_esp32c3.rs @@ -4,7 +4,7 @@ use super::phy_init_data::PHY_INIT_DATA_DEFAULT; use crate::{ binary::include::*, compat::common::str_from_c, - hal::system::{RadioClockController, RadioPeripherals}, + hal::peripherals::{APB_CTRL, LPWR}, }; const SOC_PHY_DIG_REGS_MEM_SIZE: usize = 21 * 4; @@ -34,25 +34,21 @@ pub(crate) fn enable_wifi_power_domain() { | SYSTEM_RW_BTMAC_REG_RST | SYSTEM_BTBB_REG_RST; - unsafe { - let rtc_cntl = &*crate::hal::peripherals::LPWR::ptr(); - let syscon = &*crate::hal::peripherals::APB_CTRL::ptr(); - - rtc_cntl - .dig_pwc() - .modify(|_, w| w.wifi_force_pd().clear_bit()); - - syscon - .wifi_rst_en() - .modify(|r, w| w.bits(r.bits() | MODEM_RESET_FIELD_WHEN_PU)); - syscon - .wifi_rst_en() - .modify(|r, w| w.bits(r.bits() & !MODEM_RESET_FIELD_WHEN_PU)); - - rtc_cntl - .dig_iso() - .modify(|_, w| w.wifi_force_iso().clear_bit()); - } + LPWR::regs() + .dig_pwc() + .modify(|_, w| w.wifi_force_pd().clear_bit()); + + APB_CTRL::regs() + .wifi_rst_en() + .modify(|r, w| unsafe { w.bits(r.bits() | MODEM_RESET_FIELD_WHEN_PU) }); + + APB_CTRL::regs() + .wifi_rst_en() + .modify(|r, w| unsafe { w.bits(r.bits() & !MODEM_RESET_FIELD_WHEN_PU) }); + + LPWR::regs() + .dig_iso() + .modify(|_, w| w.wifi_force_iso().clear_bit()); } pub(crate) fn phy_mem_init() { @@ -65,7 +61,7 @@ pub(crate) unsafe fn phy_enable() { let count = PHY_ACCESS_REF.fetch_add(1, Ordering::SeqCst); if count == 0 { critical_section::with(|_| { - phy_enable_clock(); + super::phy_enable_clock(); if !G_IS_PHY_CALIBRATED { let mut cal_data: [u8; core::mem::size_of::()] = @@ -130,7 +126,7 @@ pub(crate) unsafe fn phy_disable() { // Disable WiFi/BT common peripheral clock. Do not disable clock for hardware // RNG - phy_disable_clock(); + super::phy_disable_clock(); trace!("PHY DISABLE"); }); } @@ -152,23 +148,3 @@ fn phy_digital_regs_store() { } } } - -pub(crate) unsafe fn phy_enable_clock() { - trace!("phy_enable_clock"); - // stealing RADIO_CLK is safe since it is passed (as mutable reference or by - // value) into `init` - let mut radio_clocks = unsafe { esp_hal::peripherals::RADIO_CLK::steal() }; - radio_clocks.enable(RadioPeripherals::Phy); - trace!("phy_enable_clock done!"); -} - -#[allow(unused)] -pub(crate) unsafe fn phy_disable_clock() { - trace!("phy_disable_clock"); - // stealing RADIO_CLK is safe since it is passed (as mutable reference or by - // value) into `init` - let mut radio_clocks = unsafe { esp_hal::peripherals::RADIO_CLK::steal() }; - radio_clocks.disable(RadioPeripherals::Phy); - - trace!("phy_disable_clock done!"); -} diff --git a/esp-wifi/src/common_adapter/common_adapter_esp32c6.rs b/esp-wifi/src/common_adapter/common_adapter_esp32c6.rs index bd0e30cfe66..071dd9903d7 100644 --- a/esp-wifi/src/common_adapter/common_adapter_esp32c6.rs +++ b/esp-wifi/src/common_adapter/common_adapter_esp32c6.rs @@ -1,11 +1,7 @@ use portable_atomic::{AtomicU32, Ordering}; use super::phy_init_data::PHY_INIT_DATA_DEFAULT; -use crate::{ - binary::include::*, - compat::common::str_from_c, - hal::system::{RadioClockController, RadioPeripherals}, -}; +use crate::{binary::include::*, compat::common::str_from_c}; const SOC_PHY_DIG_REGS_MEM_SIZE: usize = 21 * 4; @@ -30,7 +26,7 @@ pub(crate) unsafe fn phy_enable() { let count = PHY_ACCESS_REF.fetch_add(1, Ordering::SeqCst); if count == 0 { critical_section::with(|_| { - phy_enable_clock(); + super::phy_enable_clock(); if !G_IS_PHY_CALIBRATED { let mut cal_data: [u8; core::mem::size_of::()] = @@ -94,7 +90,7 @@ pub(crate) unsafe fn phy_disable() { // Disable WiFi/BT common peripheral clock. Do not disable clock for hardware // RNG - phy_disable_clock(); + super::phy_disable_clock(); trace!("PHY DISABLE"); }); } @@ -116,22 +112,3 @@ fn phy_digital_regs_store() { } } } - -pub(crate) unsafe fn phy_enable_clock() { - trace!("phy_enable_clock"); - // stealing RADIO_CLK is safe since it is passed (as mutable reference or by - // value) into `init` - let mut radio_clocks = unsafe { esp_hal::peripherals::RADIO_CLK::steal() }; - radio_clocks.enable(RadioPeripherals::Phy); - trace!("phy_enable_clock done!"); -} - -#[allow(unused)] -pub(crate) unsafe fn phy_disable_clock() { - trace!("phy_disable_clock"); - // stealing RADIO_CLK is safe since it is passed (as mutable reference or by - // value) into `init` - let mut radio_clocks = unsafe { esp_hal::peripherals::RADIO_CLK::steal() }; - radio_clocks.disable(RadioPeripherals::Phy); - trace!("phy_disable_clock done!"); -} diff --git a/esp-wifi/src/common_adapter/common_adapter_esp32h2.rs b/esp-wifi/src/common_adapter/common_adapter_esp32h2.rs index 0186c2759fa..fd6e953bea4 100644 --- a/esp-wifi/src/common_adapter/common_adapter_esp32h2.rs +++ b/esp-wifi/src/common_adapter/common_adapter_esp32h2.rs @@ -2,11 +2,7 @@ use portable_atomic::{AtomicU32, Ordering}; use super::phy_init_data::PHY_INIT_DATA_DEFAULT; -use crate::{ - binary::include::*, - compat::common::str_from_c, - hal::system::{RadioClockController, RadioPeripherals}, -}; +use crate::{binary::include::*, compat::common::str_from_c}; const SOC_PHY_DIG_REGS_MEM_SIZE: usize = 21 * 4; @@ -31,7 +27,7 @@ pub(crate) unsafe fn phy_enable() { let count = PHY_ACCESS_REF.fetch_add(1, Ordering::SeqCst); if count == 0 { critical_section::with(|_| { - phy_enable_clock(); + super::phy_enable_clock(); if !G_IS_PHY_CALIBRATED { let mut cal_data: [u8; core::mem::size_of::()] = @@ -97,7 +93,7 @@ pub(crate) unsafe fn phy_disable() { // Disable WiFi/BT common peripheral clock. Do not disable clock for hardware // RNG - phy_disable_clock(); + super::phy_disable_clock(); trace!("PHY DISABLE"); }); } @@ -119,22 +115,3 @@ fn phy_digital_regs_store() { } } } - -pub(crate) unsafe fn phy_enable_clock() { - trace!("phy_enable_clock"); - // stealing RADIO_CLK is safe since it is passed (as mutable reference or by - // value) into `init` - let mut radio_clocks = unsafe { esp_hal::peripherals::RADIO_CLK::steal() }; - radio_clocks.enable(RadioPeripherals::Phy); - trace!("phy_enable_clock done!"); -} - -#[allow(unused)] -pub(crate) unsafe fn phy_disable_clock() { - trace!("phy_disable_clock"); - // stealing RADIO_CLK is safe since it is passed (as mutable reference or by - // value) into `init` - let mut radio_clocks = unsafe { esp_hal::peripherals::RADIO_CLK::steal() }; - radio_clocks.disable(RadioPeripherals::Phy); - trace!("phy_disable_clock done!"); -} diff --git a/esp-wifi/src/common_adapter/common_adapter_esp32s2.rs b/esp-wifi/src/common_adapter/common_adapter_esp32s2.rs index 0d716dee570..16c6b476bea 100644 --- a/esp-wifi/src/common_adapter/common_adapter_esp32s2.rs +++ b/esp-wifi/src/common_adapter/common_adapter_esp32s2.rs @@ -4,8 +4,8 @@ use super::phy_init_data::PHY_INIT_DATA_DEFAULT; use crate::{ binary::include::*, hal::{ + peripherals::{LPWR, SYSCON}, ram, - system::{RadioClockController, RadioPeripherals}, }, }; @@ -16,7 +16,6 @@ static mut G_IS_PHY_CALIBRATED: bool = false; static mut G_PHY_DIGITAL_REGS_MEM: *mut u32 = core::ptr::null_mut(); static mut S_IS_PHY_REG_STORED: bool = false; static PHY_ACCESS_REF: AtomicU32 = AtomicU32::new(0); -static PHY_CLOCK_ENABLE_REF: AtomicU32 = AtomicU32::new(0); pub(crate) fn enable_wifi_power_domain() { const DPORT_WIFIBB_RST: u32 = 1 << 0; @@ -33,26 +32,21 @@ pub(crate) fn enable_wifi_power_domain() { | DPORT_BTMAC_RST | DPORT_RW_BTMAC_RST; - unsafe { - let rtc_cntl = &*crate::hal::peripherals::LPWR::ptr(); - - let syscon = &*crate::hal::peripherals::SYSCON::ptr(); + LPWR::regs() + .dig_pwc() + .modify(|_, w| w.wifi_force_pd().clear_bit()); - rtc_cntl - .dig_pwc() - .modify(|_, w| w.wifi_force_pd().clear_bit()); + SYSCON::regs() + .wifi_rst_en() + .modify(|r, w| unsafe { w.bits(r.bits() | MODEM_RESET_FIELD_WHEN_PU) }); - syscon - .wifi_rst_en() - .modify(|r, w| w.bits(r.bits() | MODEM_RESET_FIELD_WHEN_PU)); - syscon - .wifi_rst_en() - .modify(|r, w| w.bits(r.bits() & !MODEM_RESET_FIELD_WHEN_PU)); + SYSCON::regs() + .wifi_rst_en() + .modify(|r, w| unsafe { w.bits(r.bits() & !MODEM_RESET_FIELD_WHEN_PU) }); - rtc_cntl - .dig_iso() - .modify(|_, w| w.wifi_force_iso().clear_bit()); - } + LPWR::regs() + .dig_iso() + .modify(|_, w| w.wifi_force_iso().clear_bit()); } pub(crate) fn phy_mem_init() { @@ -65,7 +59,7 @@ pub(crate) unsafe fn phy_enable() { let count = PHY_ACCESS_REF.fetch_add(1, Ordering::SeqCst); if count == 0 { critical_section::with(|_| { - phy_enable_clock(); + super::phy_enable_clock(); if !G_IS_PHY_CALIBRATED { let mut cal_data: [u8; core::mem::size_of::()] = @@ -111,7 +105,7 @@ pub(crate) unsafe fn phy_disable() { // Disable WiFi/BT common peripheral clock. Do not disable clock for hardware // RNG - phy_disable_clock(); + super::phy_disable_clock(); }); } } @@ -133,29 +127,6 @@ fn phy_digital_regs_store() { } } -pub(crate) unsafe fn phy_enable_clock() { - let count = PHY_CLOCK_ENABLE_REF.fetch_add(1, Ordering::SeqCst); - if count == 0 { - // stealing RADIO_CLK is safe since it is passed (as mutable reference or by - // value) into `init` - let mut radio_clocks = unsafe { esp_hal::peripherals::RADIO_CLK::steal() }; - radio_clocks.enable(RadioPeripherals::Phy); - trace!("phy_enable_clock done!"); - } -} - -#[allow(unused)] -pub(crate) unsafe fn phy_disable_clock() { - let count = PHY_CLOCK_ENABLE_REF.fetch_sub(1, Ordering::SeqCst); - if count == 1 { - // stealing RADIO_CLK is safe since it is passed (as mutable reference or by - // value) into `init` - let mut radio_clocks = unsafe { esp_hal::peripherals::RADIO_CLK::steal() }; - radio_clocks.disable(RadioPeripherals::Phy); - trace!("phy_disable_clock done!"); - } -} - /// ************************************************************************** /// Name: phy_enter_critical /// diff --git a/esp-wifi/src/common_adapter/common_adapter_esp32s3.rs b/esp-wifi/src/common_adapter/common_adapter_esp32s3.rs index f4213be87dd..24f2f2fe826 100644 --- a/esp-wifi/src/common_adapter/common_adapter_esp32s3.rs +++ b/esp-wifi/src/common_adapter/common_adapter_esp32s3.rs @@ -1,10 +1,7 @@ use portable_atomic::{AtomicU32, Ordering}; use super::phy_init_data::PHY_INIT_DATA_DEFAULT; -use crate::{ - binary::include::*, - hal::system::{RadioClockController, RadioPeripherals}, -}; +use crate::binary::include::*; const SOC_PHY_DIG_REGS_MEM_SIZE: usize = 21 * 4; @@ -64,7 +61,7 @@ pub(crate) unsafe fn phy_enable() { let count = PHY_ACCESS_REF.fetch_add(1, Ordering::SeqCst); if count == 0 { critical_section::with(|_| { - phy_enable_clock(); + super::phy_enable_clock(); if !G_IS_PHY_CALIBRATED { let mut cal_data: [u8; core::mem::size_of::()] = @@ -121,7 +118,7 @@ pub(crate) unsafe fn phy_disable() { // Disable WiFi/BT common peripheral clock. Do not disable clock for hardware // RNG - phy_disable_clock(); + super::phy_disable_clock(); trace!("PHY DISABLE"); }); @@ -145,25 +142,6 @@ fn phy_digital_regs_store() { } } -pub(crate) unsafe fn phy_enable_clock() { - trace!("phy_enable_clock"); - // stealing RADIO_CLK is safe since it is passed (as mutable reference or by - // value) into `init` - let mut radio_clocks = unsafe { esp_hal::peripherals::RADIO_CLK::steal() }; - radio_clocks.enable(RadioPeripherals::Phy); - trace!("phy_enable_clock done!"); -} - -#[allow(unused)] -pub(crate) unsafe fn phy_disable_clock() { - trace!("phy_disable_clock"); - // stealing RADIO_CLK is safe since it is passed (as mutable reference or by - // value) into `init` - let mut radio_clocks = unsafe { esp_hal::peripherals::RADIO_CLK::steal() }; - radio_clocks.disable(RadioPeripherals::Phy); - trace!("phy_disable_clock done!"); -} - #[no_mangle] unsafe extern "C" fn abort() { trace!("misc_nvs_deinit") diff --git a/esp-wifi/src/common_adapter/mod.rs b/esp-wifi/src/common_adapter/mod.rs index 2223ea3a108..46f27edcf79 100644 --- a/esp-wifi/src/common_adapter/mod.rs +++ b/esp-wifi/src/common_adapter/mod.rs @@ -1,10 +1,9 @@ use esp_wifi_sys::include::timeval; -use hal::ram; use crate::{ binary::include::{esp_event_base_t, esp_timer_get_time}, compat::{common::*, timer_compat::*}, - hal, + hal::{self, clock::RadioClockController, peripherals::RADIO_CLK, ram}, }; #[cfg_attr(esp32c3, path = "common_adapter_esp32c3.rs")] @@ -114,7 +113,7 @@ pub unsafe extern "C" fn random() -> crate::binary::c_types::c_ulong { trace!("random"); // stealing RNG is safe since we own it (passed into `init`) - let mut rng = esp_hal::rng::Rng::new(unsafe { esp_hal::peripherals::RNG::steal() }); + let mut rng = hal::rng::Rng::new(unsafe { hal::peripherals::RNG::steal() }); rng.random() } @@ -135,7 +134,7 @@ pub unsafe extern "C" fn random() -> crate::binary::c_types::c_ulong { pub unsafe extern "C" fn read_mac(mac: *mut u8, type_: u32) -> crate::binary::c_types::c_int { trace!("read_mac {:?} {}", mac, type_); - let base_mac = crate::hal::efuse::Efuse::mac_address(); + let base_mac = hal::efuse::Efuse::mac_address(); for (i, &byte) in base_mac.iter().enumerate() { mac.add(i).write_volatile(byte); @@ -307,3 +306,22 @@ pub unsafe extern "C" fn strrchr(_s: *const (), _c: u32) -> *const u8 { pub unsafe extern "C" fn floor(v: f64) -> f64 { libm::floor(v) } + +// TODO: previously ESP32 and S2 refcounted the PHY clock. Should we? + +pub(crate) unsafe fn phy_enable_clock() { + // stealing RADIO_CLK is safe since it is passed (as mutable reference or by + // value) into `init` + let radio_clocks = unsafe { RADIO_CLK::steal() }; + RadioClockController::new(radio_clocks).enable_phy(true); + trace!("phy_enable_clock done!"); +} + +#[allow(unused)] +pub(crate) unsafe fn phy_disable_clock() { + // stealing RADIO_CLK is safe since it is passed (as mutable reference or by + // value) into `init` + let radio_clocks = unsafe { RADIO_CLK::steal() }; + RadioClockController::new(radio_clocks).enable_phy(false); + trace!("phy_disable_clock done!"); +} diff --git a/esp-wifi/src/lib.rs b/esp-wifi/src/lib.rs index 454edd8d374..81a7a66fbfa 100644 --- a/esp-wifi/src/lib.rs +++ b/esp-wifi/src/lib.rs @@ -104,14 +104,17 @@ use core::marker::PhantomData; use common_adapter::chip_specific::phy_mem_init; use esp_config::*; -use esp_hal as hal; -use esp_hal::peripheral::Peripheral; #[cfg(not(feature = "esp32"))] use esp_hal::timer::systimer::Alarm; +use esp_hal::{ + self as hal, + clock::RadioClockController, + peripheral::Peripheral, + peripherals::RADIO_CLK, +}; use hal::{ clock::Clocks, rng::{Rng, Trng}, - system::RadioClockController, time::Rate, timer::{timg::Timer as TimgTimer, AnyTimer, PeriodicTimer}, Blocking, @@ -367,7 +370,7 @@ impl private::Sealed for Trng<'_> {} pub fn init<'d, T: EspWifiTimerSource, R: EspWifiRngSource>( timer: impl Peripheral

+ 'd, _rng: impl Peripheral

+ 'd, - _radio_clocks: impl Peripheral

+ 'd, + _radio_clocks: impl Peripheral

+ 'd, ) -> Result, InitializationError> { // A minimum clock of 80MHz is required to operate WiFi module. const MIN_CLOCK: Rate = Rate::from_mhz(80); @@ -478,6 +481,6 @@ pub fn wifi_set_log_verbose() { } fn init_clocks() { - let mut radio_clocks = unsafe { esp_hal::peripherals::RADIO_CLK::steal() }; - radio_clocks.init_clocks(); + let radio_clocks = unsafe { RADIO_CLK::steal() }; + RadioClockController::new(radio_clocks).init_clocks(); } diff --git a/esp-wifi/src/wifi/os_adapter.rs b/esp-wifi/src/wifi/os_adapter.rs index 8cd7a03e2ae..f11fdab89a0 100644 --- a/esp-wifi/src/wifi/os_adapter.rs +++ b/esp-wifi/src/wifi/os_adapter.rs @@ -10,7 +10,6 @@ pub(crate) mod os_adapter_chip_specific; use core::{cell::RefCell, ptr::addr_of_mut}; use enumset::EnumSet; -use esp_hal::sync::{Locked, RawMutex}; use super::WifiEvent; use crate::{ @@ -30,7 +29,11 @@ use crate::{ }, malloc::calloc, }, - hal::system::{RadioClockController, RadioPeripherals}, + hal::{ + clock::RadioClockController, + peripherals::RADIO_CLK, + sync::{Locked, RawMutex}, + }, memory_fence::memory_fence, timer::yield_task, }; @@ -1046,8 +1049,8 @@ pub unsafe extern "C" fn wifi_reset_mac() { trace!("wifi_reset_mac"); // stealing RADIO_CLK is safe since it is passed (as mutable reference or by // value) into `init` - let mut radio_clocks = unsafe { esp_hal::peripherals::RADIO_CLK::steal() }; - radio_clocks.reset_mac(); + let radio_clocks = unsafe { RADIO_CLK::steal() }; + RadioClockController::new(radio_clocks).reset_mac(); } /// ************************************************************************** @@ -1067,8 +1070,8 @@ pub unsafe extern "C" fn wifi_clock_enable() { trace!("wifi_clock_enable"); // stealing RADIO_CLK is safe since it is passed (as mutable reference or by // value) into `init` - let mut radio_clocks = unsafe { esp_hal::peripherals::RADIO_CLK::steal() }; - radio_clocks.enable(RadioPeripherals::Wifi); + let radio_clocks = unsafe { RADIO_CLK::steal() }; + RadioClockController::new(radio_clocks).enable_wifi(true); } /// ************************************************************************** @@ -1088,8 +1091,8 @@ pub unsafe extern "C" fn wifi_clock_disable() { trace!("wifi_clock_disable"); // stealing RADIO_CLK is safe since it is passed (as mutable reference or by // value) into `init` - let mut radio_clocks = unsafe { esp_hal::peripherals::RADIO_CLK::steal() }; - radio_clocks.disable(RadioPeripherals::Wifi); + let radio_clocks = unsafe { RADIO_CLK::steal() }; + RadioClockController::new(radio_clocks).enable_wifi(false); } /// ************************************************************************** diff --git a/esp-wifi/src/wifi/os_adapter_esp32s2.rs b/esp-wifi/src/wifi/os_adapter_esp32s2.rs index fa2ac9159fd..5c0d01a3fd2 100644 --- a/esp-wifi/src/wifi/os_adapter_esp32s2.rs +++ b/esp-wifi/src/wifi/os_adapter_esp32s2.rs @@ -22,11 +22,11 @@ pub(crate) unsafe extern "C" fn set_intr( } pub(crate) unsafe extern "C" fn phy_common_clock_disable() { - crate::common_adapter::chip_specific::phy_disable_clock(); + crate::common_adapter::phy_disable_clock(); } pub(crate) unsafe extern "C" fn phy_common_clock_enable() { - crate::common_adapter::chip_specific::phy_enable_clock(); + crate::common_adapter::phy_enable_clock(); } /// **************************************************************************