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lowerarmarch.cpp
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// Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
/*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XX XX
XX Lowering for ARM and ARM64 common code XX
XX XX
XX This encapsulates common logic for lowering trees for the ARM and ARM64 XX
XX architectures. For a more detailed view of what is lowering, please XX
XX take a look at Lower.cpp XX
XX XX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
*/
#include "jitpch.h"
#ifdef _MSC_VER
#pragma hdrstop
#endif
#ifdef TARGET_ARMARCH // This file is ONLY used for ARM and ARM64 architectures
#include "jit.h"
#include "sideeffects.h"
#include "lower.h"
#include "lsra.h"
#ifdef FEATURE_HW_INTRINSICS
#include "hwintrinsic.h"
#endif
//------------------------------------------------------------------------
// IsCallTargetInRange: Can a call target address be encoded in-place?
//
// Return Value:
// True if the addr fits into the range.
//
bool Lowering::IsCallTargetInRange(void* addr)
{
return comp->codeGen->validImmForBL((ssize_t)addr);
}
//------------------------------------------------------------------------
// IsContainableImmed: Is an immediate encodable in-place?
//
// Return Value:
// True if the immediate can be folded into an instruction,
// for example small enough and non-relocatable.
//
bool Lowering::IsContainableImmed(GenTree* parentNode, GenTree* childNode) const
{
if (!varTypeIsFloating(parentNode->TypeGet()))
{
#ifdef TARGET_ARM64
if (parentNode->OperIsCompare() && childNode->IsFloatPositiveZero())
{
// Contain 0.0 constant in fcmp on arm64
// TODO: Enable for arm too (vcmp)
// We currently don't emit these for floating points
assert(!parentNode->OperIs(GT_TEST_EQ, GT_TEST_NE));
return true;
}
#endif
// Make sure we have an actual immediate
if (!childNode->IsCnsIntOrI())
return false;
if (childNode->AsIntCon()->ImmedValNeedsReloc(comp))
return false;
// TODO-CrossBitness: we wouldn't need the cast below if GenTreeIntCon::gtIconVal had target_ssize_t type.
target_ssize_t immVal = (target_ssize_t)childNode->AsIntCon()->gtIconVal;
emitAttr attr = emitActualTypeSize(childNode->TypeGet());
emitAttr size = EA_SIZE(attr);
#ifdef TARGET_ARM
insFlags flags = parentNode->gtSetFlags() ? INS_FLAGS_SET : INS_FLAGS_DONT_CARE;
#endif
switch (parentNode->OperGet())
{
case GT_ADD:
case GT_SUB:
#ifdef TARGET_ARM64
return emitter::emitIns_valid_imm_for_add(immVal, size);
case GT_CMPXCHG:
case GT_LOCKADD:
case GT_XORR:
case GT_XAND:
case GT_XADD:
return comp->compOpportunisticallyDependsOn(InstructionSet_Atomics)
? false
: emitter::emitIns_valid_imm_for_add(immVal, size);
#elif defined(TARGET_ARM)
return emitter::emitIns_valid_imm_for_add(immVal, flags);
#endif
break;
#ifdef TARGET_ARM64
case GT_EQ:
case GT_NE:
case GT_LT:
case GT_LE:
case GT_GE:
case GT_GT:
case GT_CMP:
case GT_BOUNDS_CHECK:
return emitter::emitIns_valid_imm_for_cmp(immVal, size);
case GT_AND:
case GT_OR:
case GT_XOR:
case GT_TEST_EQ:
case GT_TEST_NE:
return emitter::emitIns_valid_imm_for_alu(immVal, size);
case GT_JCMP:
assert(immVal == 0);
return true;
case GT_JTEST:
assert(isPow2(immVal));
return true;
#elif defined(TARGET_ARM)
case GT_EQ:
case GT_NE:
case GT_LT:
case GT_LE:
case GT_GE:
case GT_GT:
case GT_CMP:
case GT_AND:
case GT_OR:
case GT_XOR:
return emitter::emitIns_valid_imm_for_alu(immVal);
#endif // TARGET_ARM
#ifdef TARGET_ARM64
case GT_STORE_LCL_FLD:
case GT_STORE_LCL_VAR:
if (immVal == 0)
return true;
break;
#endif
default:
break;
}
}
return false;
}
#ifdef TARGET_ARM64
//------------------------------------------------------------------------
// IsContainableUnaryOrBinaryOp: Is the child node a unary/binary op that is containable from the parent node?
//
// Return Value:
// True if the child node can be contained.
//
// Notes:
// This can handle the decision to emit 'madd' or 'msub'.
//
bool Lowering::IsContainableUnaryOrBinaryOp(GenTree* parentNode, GenTree* childNode) const
{
#ifdef DEBUG
// The node we're checking should be one of the two child nodes
if (parentNode->OperIsBinary())
{
assert((parentNode->gtGetOp1() == childNode) || (parentNode->gtGetOp2() == childNode));
}
else
{
assert(parentNode->OperIsUnary());
assert((parentNode->gtGetOp1() == childNode));
}
#endif // DEBUG
// We cannot contain if the parent node
// * is contained
// * is not operating on an integer
// * is already marking a child node as contained
// * is required to throw on overflow
if (parentNode->isContained())
return false;
if (!varTypeIsIntegral(parentNode))
return false;
if (parentNode->gtGetOp1()->isContained() || (parentNode->OperIsBinary() && parentNode->gtGetOp2()->isContained()))
return false;
if (parentNode->OperMayOverflow() && parentNode->gtOverflow())
return false;
// We cannot contain if the child node:
// * is not operating on an integer
// * is required to set a flag
// * is required to throw on overflow
if (!varTypeIsIntegral(childNode))
return false;
if ((childNode->gtFlags & GTF_SET_FLAGS) != 0)
return false;
if (childNode->OperMayOverflow() && childNode->gtOverflow())
return false;
GenTree* matchedOp = nullptr;
if (childNode->OperIs(GT_MUL))
{
if (childNode->gtGetOp1()->isContained() || childNode->gtGetOp2()->isContained())
{
// Cannot contain if either of the childs operands is already contained
return false;
}
if ((parentNode->gtFlags & GTF_SET_FLAGS) != 0)
{
// Cannot contain if the parent operation needs to set flags
return false;
}
if (parentNode->OperIs(GT_ADD))
{
// Find "c + (a * b)" or "(a * b) + c"
return IsInvariantInRange(childNode, parentNode);
}
if (parentNode->OperIs(GT_SUB))
{
// Find "c - (a * b)"
assert(childNode == parentNode->gtGetOp2());
return IsInvariantInRange(childNode, parentNode);
}
return false;
}
if (childNode->OperIs(GT_LSH, GT_RSH, GT_RSZ))
{
// Find "a op (b shift cns)"
if (childNode->gtGetOp1()->isContained())
{
// Cannot contain if the childs op1 is already contained
return false;
}
GenTree* shiftAmountNode = childNode->gtGetOp2();
if (!shiftAmountNode->IsCnsIntOrI())
{
// Cannot contain if the childs op2 is not a constant
return false;
}
const ssize_t shiftAmount = shiftAmountNode->AsIntCon()->IconValue();
const ssize_t maxShift = (static_cast<ssize_t>(genTypeSize(parentNode)) * BITS_PER_BYTE) - 1;
if ((shiftAmount < 0x01) || (shiftAmount > maxShift))
{
// Cannot contain if the shift amount is less than 1 or greater than maxShift
return false;
}
if (parentNode->OperIs(GT_ADD, GT_SUB, GT_AND, GT_NEG))
{
// These operations can still report flags
if (IsInvariantInRange(childNode, parentNode))
{
assert(shiftAmountNode->isContained());
return true;
}
}
if ((parentNode->gtFlags & GTF_SET_FLAGS) != 0)
{
// Cannot contain if the parent operation needs to set flags
return false;
}
if (parentNode->OperIs(GT_CMP, GT_OR, GT_XOR) || parentNode->OperIsCompare())
{
if (IsInvariantInRange(childNode, parentNode))
{
assert(shiftAmountNode->isContained());
return true;
}
}
// TODO: Handle CMN, NEG/NEGS, BIC/BICS, EON, MVN, ORN, TST
return false;
}
if (childNode->OperIs(GT_ROL, GT_ROR))
{
// Find "a op (b rotate cns)"
if (childNode->gtGetOp1()->isContained())
{
// Cannot contain if the childs op1 is already contained
return false;
}
GenTree* rotateAmountNode = childNode->gtGetOp2();
if (!rotateAmountNode->IsCnsIntOrI())
{
// Cannot contain if the childs op2 is not a constant
return false;
}
const ssize_t wrapAmount = (static_cast<ssize_t>(genTypeSize(childNode)) * BITS_PER_BYTE);
assert((wrapAmount == 32) || (wrapAmount == 64));
// Rotation is circular, so normalize to [0, wrapAmount - 1]
ssize_t rotateAmount = rotateAmountNode->AsIntCon()->IconValue() % wrapAmount;
assert((rotateAmount >= 0) && (rotateAmount <= (wrapAmount - 1)));
if (childNode->OperIs(GT_ROL))
{
// The actual instructions only encode rotate right but
// since rotating left by 1 is equivalen to rotating
// right by (rotateAmount - 1), we can fix things here.
childNode->SetOper(GT_ROR);
rotateAmount = wrapAmount - rotateAmount;
}
rotateAmountNode->AsIntCon()->SetIconValue(rotateAmount);
assert(childNode->OperIs(GT_ROR));
if (parentNode->OperIs(GT_AND))
{
// These operations can still report flags
if (IsInvariantInRange(childNode, parentNode))
{
assert(rotateAmountNode->isContained());
return true;
}
}
if ((parentNode->gtFlags & GTF_SET_FLAGS) != 0)
{
// Cannot contain if the parent operation needs to set flags
return false;
}
if (parentNode->OperIs(GT_OR, GT_XOR))
{
if (IsInvariantInRange(childNode, parentNode))
{
assert(rotateAmountNode->isContained());
return true;
}
}
// TODO: Handle BIC/BICS, EON, MVN, ORN, TST
return false;
}
if (childNode->OperIs(GT_NEG))
{
// If we have a contained LSH, RSH or RSZ, we can still contain NEG if the parent is a EQ or NE.
if (childNode->gtGetOp1()->isContained() && !childNode->gtGetOp1()->OperIs(GT_LSH, GT_RSH, GT_RSZ))
{
// Cannot contain if the childs op1 is already contained
return false;
}
if ((parentNode->gtFlags & GTF_SET_FLAGS) != 0)
{
// Cannot contain if the parent operation needs to set flags
return false;
}
// EQ and NE are the only valid comparison ops that can contain NEG.
if (parentNode->OperIs(GT_EQ, GT_NE))
{
if (IsInvariantInRange(childNode, parentNode))
{
return true;
}
}
return false;
}
if (childNode->OperIs(GT_CAST))
{
// Find "a op cast(b)"
GenTree* castOp = childNode->AsCast()->CastOp();
bool isSupportedCast = false;
if (varTypeIsSmall(childNode->CastToType()))
{
// The JIT doesn't track upcasts from small types, instead most types
// are tracked as TYP_INT and then we get explicit downcasts to the
// desired small type instead.
assert(!varTypeIsFloating(castOp));
isSupportedCast = true;
}
else if (childNode->TypeIs(TYP_LONG) && genActualTypeIsInt(castOp))
{
// We can handle "INT -> LONG", "INT -> ULONG", "UINT -> LONG", and "UINT -> ULONG"
isSupportedCast = true;
}
if (!isSupportedCast)
{
return false;
}
if (parentNode->OperIs(GT_ADD, GT_SUB))
{
// These operations can still report flags
if (IsInvariantInRange(childNode, parentNode))
{
return true;
}
}
if ((parentNode->gtFlags & GTF_SET_FLAGS) != 0)
{
// Cannot contain if the parent operation needs to set flags
return false;
}
if (parentNode->OperIs(GT_CMP))
{
if (IsInvariantInRange(childNode, parentNode))
{
return true;
}
}
// TODO: Handle CMN
return false;
}
return false;
}
#endif // TARGET_ARM64
//------------------------------------------------------------------------
// LowerStoreLoc: Lower a store of a lclVar
//
// Arguments:
// storeLoc - the local store (GT_STORE_LCL_FLD or GT_STORE_LCL_VAR)
//
// Notes:
// This involves:
// - Widening small stores (on ARM).
//
void Lowering::LowerStoreLoc(GenTreeLclVarCommon* storeLoc)
{
#ifdef TARGET_ARM
// On ARM, small stores can cost a bit more in terms of code size so we try to widen them. This is legal
// as most small locals have 4-byte-wide stack homes, the common exception being (dependent) struct fields.
//
if (storeLoc->OperIs(GT_STORE_LCL_VAR) && varTypeIsSmall(storeLoc) && storeLoc->Data()->IsCnsIntOrI())
{
LclVarDsc* varDsc = comp->lvaGetDesc(storeLoc);
if (!varDsc->lvIsStructField && (varDsc->GetStackSlotHomeType() == TYP_INT))
{
storeLoc->gtType = TYP_INT;
}
}
#endif // TARGET_ARM
if (storeLoc->OperIs(GT_STORE_LCL_FLD))
{
// We should only encounter this for lclVars that are lvDoNotEnregister.
verifyLclFldDoNotEnregister(storeLoc->GetLclNum());
}
ContainCheckStoreLoc(storeLoc);
}
//------------------------------------------------------------------------
// LowerStoreIndir: Determine addressing mode for an indirection, and whether operands are contained.
//
// Arguments:
// node - The indirect store node (GT_STORE_IND) of interest
//
// Return Value:
// Next node to lower.
//
GenTree* Lowering::LowerStoreIndir(GenTreeStoreInd* node)
{
GenTree* next = node->gtNext;
ContainCheckStoreIndir(node);
#ifdef TARGET_ARM64
if (comp->opts.OptimizationEnabled())
{
OptimizeForLdpStp(node);
}
#endif
return next;
}
//------------------------------------------------------------------------
// LowerMul: Lower a GT_MUL/GT_MULHI/GT_MUL_LONG node.
//
// For ARM64 recognized GT_MULs that can be turned into GT_MUL_LONGs, as
// those are cheaper. Performs contaiment checks.
//
// Arguments:
// mul - The node to lower
//
// Return Value:
// The next node to lower.
//
GenTree* Lowering::LowerMul(GenTreeOp* mul)
{
assert(mul->OperIsMul());
#ifdef TARGET_ARM64
if (comp->opts.OptimizationEnabled() && mul->OperIs(GT_MUL) && mul->IsValidLongMul())
{
GenTreeCast* op1 = mul->gtGetOp1()->AsCast();
GenTree* op2 = mul->gtGetOp2();
mul->ClearOverflow();
mul->ClearUnsigned();
if (op1->IsUnsigned())
{
mul->SetUnsigned();
}
op1->CastOp()->ClearContained(); // Uncontain any memory operands.
mul->gtOp1 = op1->CastOp();
BlockRange().Remove(op1);
if (op2->OperIs(GT_CAST))
{
op2->AsCast()->CastOp()->ClearContained(); // Uncontain any memory operands.
mul->gtOp2 = op2->AsCast()->CastOp();
BlockRange().Remove(op2);
}
else
{
assert(op2->IsIntegralConst());
assert(FitsIn<int32_t>(op2->AsIntConCommon()->IntegralValue()));
op2->ChangeType(TYP_INT);
}
mul->ChangeOper(GT_MUL_LONG);
}
#endif // TARGET_ARM64
ContainCheckMul(mul);
return mul->gtNext;
}
//------------------------------------------------------------------------
// LowerBinaryArithmetic: lowers the given binary arithmetic node.
//
// Arguments:
// node - the arithmetic node to lower
//
// Returns:
// The next node to lower.
//
GenTree* Lowering::LowerBinaryArithmetic(GenTreeOp* binOp)
{
if (comp->opts.OptimizationEnabled())
{
if (binOp->OperIs(GT_AND))
{
GenTree* opNode = nullptr;
GenTree* notNode = nullptr;
if (binOp->gtGetOp1()->OperIs(GT_NOT))
{
notNode = binOp->gtGetOp1();
opNode = binOp->gtGetOp2();
}
else if (binOp->gtGetOp2()->OperIs(GT_NOT))
{
notNode = binOp->gtGetOp2();
opNode = binOp->gtGetOp1();
}
if (notNode != nullptr)
{
binOp->gtOp1 = opNode;
binOp->gtOp2 = notNode->AsUnOp()->gtGetOp1();
binOp->ChangeOper(GT_AND_NOT);
BlockRange().Remove(notNode);
}
}
#ifdef TARGET_ARM64
if (binOp->OperIs(GT_AND, GT_OR))
{
GenTree* next;
if (TryLowerAndOrToCCMP(binOp, &next))
{
return next;
}
}
if (binOp->OperIs(GT_SUB))
{
// Attempt to optimize for umsubl/smsubl.
GenTree* next;
if (TryLowerAddSubToMulLongOp(binOp, &next))
{
return next;
}
}
#endif
}
ContainCheckBinary(binOp);
return binOp->gtNext;
}
//------------------------------------------------------------------------
// LowerBlockStore: Lower a block store node
//
// Arguments:
// blkNode - The block store node to lower
//
void Lowering::LowerBlockStore(GenTreeBlk* blkNode)
{
GenTree* dstAddr = blkNode->Addr();
GenTree* src = blkNode->Data();
unsigned size = blkNode->Size();
if (blkNode->OperIsInitBlkOp())
{
#ifdef DEBUG
// Use BlkOpKindLoop for more cases under stress mode
if (comp->compStressCompile(Compiler::STRESS_STORE_BLOCK_UNROLLING, 50) && blkNode->OperIs(GT_STORE_BLK) &&
((blkNode->GetLayout()->GetSize() % TARGET_POINTER_SIZE) == 0) && src->IsIntegralConst(0))
{
blkNode->gtBlkOpKind = GenTreeBlk::BlkOpKindLoop;
#ifdef TARGET_ARM64
// On ARM64 we can just use REG_ZR instead of having to load
// the constant into a real register like on ARM32.
src->SetContained();
#endif
return;
}
#endif
if (src->OperIs(GT_INIT_VAL))
{
src->SetContained();
src = src->AsUnOp()->gtGetOp1();
}
if ((size <= comp->getUnrollThreshold(Compiler::UnrollKind::Memset)) && src->OperIs(GT_CNS_INT))
{
blkNode->gtBlkOpKind = GenTreeBlk::BlkOpKindUnroll;
// The fill value of an initblk is interpreted to hold a
// value of (unsigned int8) however a constant of any size
// may practically reside on the evaluation stack. So extract
// the lower byte out of the initVal constant and replicate
// it to a larger constant whose size is sufficient to support
// the largest width store of the desired inline expansion.
ssize_t fill = src->AsIntCon()->IconValue() & 0xFF;
if (fill == 0)
{
#ifdef TARGET_ARM64
// On ARM64 we can just use REG_ZR instead of having to load
// the constant into a real register like on ARM32.
src->SetContained();
#endif
}
#ifdef TARGET_ARM64
else if (size >= REGSIZE_BYTES)
{
fill *= 0x0101010101010101LL;
src->gtType = TYP_LONG;
}
#endif
else
{
fill *= 0x01010101;
}
src->AsIntCon()->SetIconValue(fill);
ContainBlockStoreAddress(blkNode, size, dstAddr, nullptr);
}
else if (blkNode->IsZeroingGcPointersOnHeap())
{
blkNode->gtBlkOpKind = GenTreeBlk::BlkOpKindLoop;
#ifdef TARGET_ARM64
// On ARM64 we can just use REG_ZR instead of having to load
// the constant into a real register like on ARM32.
src->SetContained();
#endif
}
else
{
LowerBlockStoreAsHelperCall(blkNode);
return;
}
}
else
{
assert(src->OperIs(GT_IND, GT_LCL_VAR, GT_LCL_FLD));
src->SetContained();
if (src->OperIs(GT_LCL_VAR))
{
// TODO-1stClassStructs: for now we can't work with STORE_BLOCK source in register.
const unsigned srcLclNum = src->AsLclVar()->GetLclNum();
comp->lvaSetVarDoNotEnregister(srcLclNum DEBUGARG(DoNotEnregisterReason::BlockOp));
}
ClassLayout* layout = blkNode->GetLayout();
bool doCpObj = layout->HasGCPtr();
unsigned copyBlockUnrollLimit = comp->getUnrollThreshold(Compiler::UnrollKind::Memcpy);
if (doCpObj && (size <= copyBlockUnrollLimit))
{
// No write barriers are needed on the stack.
// If the layout contains a byref, then we know it must live on the stack.
if (dstAddr->OperIs(GT_LCL_ADDR) || layout->IsStackOnly(comp))
{
// If the size is small enough to unroll then we need to mark the block as non-interruptible
// to actually allow unrolling. The generated code does not report GC references loaded in the
// temporary register(s) used for copying.
doCpObj = false;
blkNode->gtBlkOpGcUnsafe = true;
}
}
if (doCpObj)
{
// Try to use bulk copy helper
if (TryLowerBlockStoreAsGcBulkCopyCall(blkNode))
{
return;
}
assert((dstAddr->TypeGet() == TYP_BYREF) || (dstAddr->TypeGet() == TYP_I_IMPL));
blkNode->gtBlkOpKind = GenTreeBlk::BlkOpKindCpObjUnroll;
}
else if (blkNode->OperIs(GT_STORE_BLK) && (size <= copyBlockUnrollLimit))
{
blkNode->gtBlkOpKind = GenTreeBlk::BlkOpKindUnroll;
if (src->OperIs(GT_IND))
{
ContainBlockStoreAddress(blkNode, size, src->AsIndir()->Addr(), src->AsIndir());
}
ContainBlockStoreAddress(blkNode, size, dstAddr, nullptr);
}
else
{
assert(blkNode->OperIs(GT_STORE_BLK));
LowerBlockStoreAsHelperCall(blkNode);
}
}
}
//------------------------------------------------------------------------
// ContainBlockStoreAddress: Attempt to contain an address used by an unrolled block store.
//
// Arguments:
// blkNode - the block store node
// size - the block size
// addr - the address node to try to contain
// addrParent - the parent of addr, in case this is checking containment of the source address.
//
void Lowering::ContainBlockStoreAddress(GenTreeBlk* blkNode, unsigned size, GenTree* addr, GenTree* addrParent)
{
assert(blkNode->OperIs(GT_STORE_BLK) && (blkNode->gtBlkOpKind == GenTreeBlk::BlkOpKindUnroll));
assert(size < INT32_MAX);
if (addr->OperIs(GT_LCL_ADDR) && IsContainableLclAddr(addr->AsLclFld(), size))
{
addr->SetContained();
return;
}
if (!addr->OperIs(GT_ADD) || addr->gtOverflow() || !addr->AsOp()->gtGetOp2()->OperIs(GT_CNS_INT))
{
return;
}
GenTreeIntCon* offsetNode = addr->AsOp()->gtGetOp2()->AsIntCon();
ssize_t offset = offsetNode->IconValue();
#ifdef TARGET_ARM
// All integer load/store instructions on Arm support offsets in range -255..255.
// Of course, this is a rather conservative check.
if ((offset < -255) || (offset > 255) || (offset + static_cast<int>(size) > 256))
{
return;
}
#else // !TARGET_ARM
if ((ClrSafeInt<int>(offset) + ClrSafeInt<int>(size)).IsOverflow())
{
return;
}
#endif // !TARGET_ARM
if (!IsInvariantInRange(addr, blkNode, addrParent))
{
return;
}
BlockRange().Remove(offsetNode);
addr->ChangeOper(GT_LEA);
addr->AsAddrMode()->SetIndex(nullptr);
addr->AsAddrMode()->SetScale(0);
addr->AsAddrMode()->SetOffset(static_cast<int>(offset));
addr->SetContained();
}
//------------------------------------------------------------------------
// LowerPutArgStkOrSplit: Lower a GT_PUTARG_STK/GT_PUTARG_SPLIT.
//
// Arguments:
// putArgStk - The node to lower
//
void Lowering::LowerPutArgStkOrSplit(GenTreePutArgStk* putArgNode)
{
GenTree* src = putArgNode->Data();
if (src->TypeIs(TYP_STRUCT))
{
// STRUCT args (FIELD_LIST / BLK / LCL_VAR / LCL_FLD) will always be contained.
MakeSrcContained(putArgNode, src);
if (src->OperIs(GT_LCL_VAR))
{
// TODO-1stClassStructs: support struct enregistration here by retyping "src" to its register type for
// the non-split case.
comp->lvaSetVarDoNotEnregister(src->AsLclVar()->GetLclNum() DEBUGARG(DoNotEnregisterReason::IsStructArg));
}
}
}
//------------------------------------------------------------------------
// LowerCast: Lower GT_CAST(srcType, DstType) nodes.
//
// Arguments:
// tree - GT_CAST node to be lowered
//
// Return Value:
// nextNode to be lowered if tree is modified else returns nullptr
//
// Notes:
// Casts from float/double to a smaller int type are transformed as follows:
// GT_CAST(float/double, byte) = GT_CAST(GT_CAST(float/double, int32), byte)
// GT_CAST(float/double, sbyte) = GT_CAST(GT_CAST(float/double, int32), sbyte)
// GT_CAST(float/double, int16) = GT_CAST(GT_CAST(double/double, int32), int16)
// GT_CAST(float/double, uint16) = GT_CAST(GT_CAST(double/double, int32), uint16)
//
// Note that for the overflow conversions we still depend on helper calls and
// don't expect to see them here.
// i) GT_CAST(float/double, int type with overflow detection)
//
GenTree* Lowering::LowerCast(GenTree* tree)
{
assert(tree->OperGet() == GT_CAST);
JITDUMP("LowerCast for: ");
DISPNODE(tree);
JITDUMP("\n");
GenTree* op1 = tree->AsOp()->gtOp1;
var_types dstType = tree->CastToType();
var_types srcType = genActualType(op1->TypeGet());
if (varTypeIsFloating(srcType))
{
noway_assert(!tree->gtOverflow());
assert(!varTypeIsSmall(dstType)); // fgMorphCast creates intermediate casts when converting from float to small
// int.
}
assert(!varTypeIsSmall(srcType));
// Now determine if we have operands that should be contained.
ContainCheckCast(tree->AsCast());
return nullptr;
}
//------------------------------------------------------------------------
// LowerRotate: Lower GT_ROL and GT_ROR nodes.
//
// Arguments:
// tree - the node to lower
//
// Return Value:
// None.
//
void Lowering::LowerRotate(GenTree* tree)
{
if (tree->OperGet() == GT_ROL)
{
// There is no ROL instruction on ARM. Convert ROL into ROR.
GenTree* rotatedValue = tree->AsOp()->gtOp1;
unsigned rotatedValueBitSize = genTypeSize(rotatedValue->gtType) * 8;
GenTree* rotateLeftIndexNode = tree->AsOp()->gtOp2;
if (rotateLeftIndexNode->IsCnsIntOrI())
{
ssize_t rotateLeftIndex = rotateLeftIndexNode->AsIntCon()->gtIconVal;
ssize_t rotateRightIndex = rotatedValueBitSize - rotateLeftIndex;
rotateLeftIndexNode->AsIntCon()->gtIconVal = rotateRightIndex;
}
else
{
GenTree* tmp = comp->gtNewOperNode(GT_NEG, genActualType(rotateLeftIndexNode->gtType), rotateLeftIndexNode);
BlockRange().InsertAfter(rotateLeftIndexNode, tmp);
tree->AsOp()->gtOp2 = tmp;
}
tree->ChangeOper(GT_ROR);
}
ContainCheckShiftRotate(tree->AsOp());
}
#ifdef TARGET_ARM64
//------------------------------------------------------------------------
// LowerModPow2: Lower GT_MOD if the second operand is a constant power of 2.
//
// Arguments:
// tree - the node to lower
//
// Notes:
// TODO: We could do this optimization in morph but we do not have
// a conditional select op in HIR. At some point, we may
// introduce such an op.
void Lowering::LowerModPow2(GenTree* node)
{
assert(node->OperIs(GT_MOD));
GenTreeOp* mod = node->AsOp();
GenTree* dividend = mod->gtGetOp1();
GenTree* divisor = mod->gtGetOp2();
JITDUMP("Lower: optimize X MOD POW2");
assert(divisor->IsIntegralConstPow2());
const var_types type = mod->TypeGet();
assert((type == TYP_INT) || (type == TYP_LONG));
ssize_t divisorCnsValue = static_cast<ssize_t>(divisor->AsIntConCommon()->IntegralValue());
ssize_t divisorCnsValueMinusOne = divisorCnsValue - 1;
BlockRange().Remove(divisor);
// We need to use the dividend node multiple times so its value needs to be
// computed once and stored in a temp variable.
LIR::Use opDividend(BlockRange(), &mod->AsOp()->gtOp1, mod);
dividend = ReplaceWithLclVar(opDividend);
GenTree* dividend2 = comp->gtClone(dividend);
BlockRange().InsertAfter(dividend, dividend2);
GenTreeIntCon* cns = comp->gtNewIconNode(divisorCnsValueMinusOne, type);
BlockRange().InsertAfter(dividend2, cns);
GenTree* const trueExpr = comp->gtNewOperNode(GT_AND, type, dividend, cns);
BlockRange().InsertAfter(cns, trueExpr);
LowerNode(trueExpr);
if (divisorCnsValue == 2)
{
// {expr} % 2
// Logically turns into:
// let a = {expr}
// if a < 0 then -(a & 1) else (a & 1)
// which then turns into:
// and reg1, reg0, #1
// cmp reg0, #0
// cneg reg0, reg1, lt
GenTreeIntCon* cnsZero = comp->gtNewIconNode(0, type);
BlockRange().InsertAfter(trueExpr, cnsZero);
GenTree* const cmp = comp->gtNewOperNode(GT_CMP, TYP_VOID, dividend2, cnsZero);
cmp->gtFlags |= GTF_SET_FLAGS;