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kunalspathak
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Enable SVE2 instruction set detection for ARM64 (#115117)
* Enable SVE2 instruction set detection for ARM64 * updated the guid * remove the comment --------- Co-authored-by: Kunal Pathak <[email protected]>
1 parent 59a5ce1 commit d23f251

15 files changed

+110
-24
lines changed

‎src/coreclr/inc/clrconfigvalues.h

+1
Original file line numberDiff line numberDiff line change
@@ -725,6 +725,7 @@ RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Sha256, W("EnableArm64Sh
725725
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Rcpc, W("EnableArm64Rcpc"), 1, "Allows Arm64 Rcpc+ hardware intrinsics to be disabled")
726726
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Rcpc2, W("EnableArm64Rcpc2"), 1, "Allows Arm64 Rcpc2+ hardware intrinsics to be disabled")
727727
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Sve, W("EnableArm64Sve"), 1, "Allows Arm64 SVE hardware intrinsics to be disabled")
728+
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Sve2, W("EnableArm64Sve2"), 1, "Allows Arm64 SVE2 hardware intrinsics to be disabled")
728729
#elif defined(TARGET_RISCV64)
729730
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableRiscV64Zba, W("EnableRiscV64Zba"), 1, "Allows RiscV64 Zba hardware intrinsics to be disabled")
730731
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableRiscV64Zbb, W("EnableRiscV64Zbb"), 1, "Allows RiscV64 Zbb hardware intrinsics to be disabled")

‎src/coreclr/inc/corinfoinstructionset.h

+24-9
Original file line numberDiff line numberDiff line change
@@ -32,15 +32,17 @@ enum CORINFO_InstructionSet
3232
InstructionSet_VectorT128=14,
3333
InstructionSet_Rcpc2=15,
3434
InstructionSet_Sve=16,
35-
InstructionSet_ArmBase_Arm64=17,
36-
InstructionSet_AdvSimd_Arm64=18,
37-
InstructionSet_Aes_Arm64=19,
38-
InstructionSet_Crc32_Arm64=20,
39-
InstructionSet_Dp_Arm64=21,
40-
InstructionSet_Rdm_Arm64=22,
41-
InstructionSet_Sha1_Arm64=23,
42-
InstructionSet_Sha256_Arm64=24,
43-
InstructionSet_Sve_Arm64=25,
35+
InstructionSet_Sve2=17,
36+
InstructionSet_ArmBase_Arm64=18,
37+
InstructionSet_AdvSimd_Arm64=19,
38+
InstructionSet_Aes_Arm64=20,
39+
InstructionSet_Crc32_Arm64=21,
40+
InstructionSet_Dp_Arm64=22,
41+
InstructionSet_Rdm_Arm64=23,
42+
InstructionSet_Sha1_Arm64=24,
43+
InstructionSet_Sha256_Arm64=25,
44+
InstructionSet_Sve_Arm64=26,
45+
InstructionSet_Sve2_Arm64=27,
4446
#endif // TARGET_ARM64
4547
#ifdef TARGET_RISCV64
4648
InstructionSet_RiscV64Base=1,
@@ -311,6 +313,8 @@ struct CORINFO_InstructionSetFlags
311313
AddInstructionSet(InstructionSet_Sha256_Arm64);
312314
if (HasInstructionSet(InstructionSet_Sve))
313315
AddInstructionSet(InstructionSet_Sve_Arm64);
316+
if (HasInstructionSet(InstructionSet_Sve2))
317+
AddInstructionSet(InstructionSet_Sve2_Arm64);
314318
#endif // TARGET_ARM64
315319
#ifdef TARGET_RISCV64
316320
#endif // TARGET_RISCV64
@@ -427,6 +431,10 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins
427431
resultflags.RemoveInstructionSet(InstructionSet_Sve);
428432
if (resultflags.HasInstructionSet(InstructionSet_Sve_Arm64) && !resultflags.HasInstructionSet(InstructionSet_Sve))
429433
resultflags.RemoveInstructionSet(InstructionSet_Sve_Arm64);
434+
if (resultflags.HasInstructionSet(InstructionSet_Sve2) && !resultflags.HasInstructionSet(InstructionSet_Sve2_Arm64))
435+
resultflags.RemoveInstructionSet(InstructionSet_Sve2);
436+
if (resultflags.HasInstructionSet(InstructionSet_Sve2_Arm64) && !resultflags.HasInstructionSet(InstructionSet_Sve2))
437+
resultflags.RemoveInstructionSet(InstructionSet_Sve2_Arm64);
430438
if (resultflags.HasInstructionSet(InstructionSet_AdvSimd) && !resultflags.HasInstructionSet(InstructionSet_ArmBase))
431439
resultflags.RemoveInstructionSet(InstructionSet_AdvSimd);
432440
if (resultflags.HasInstructionSet(InstructionSet_Aes) && !resultflags.HasInstructionSet(InstructionSet_ArmBase))
@@ -449,6 +457,8 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins
449457
resultflags.RemoveInstructionSet(InstructionSet_VectorT128);
450458
if (resultflags.HasInstructionSet(InstructionSet_Sve) && !resultflags.HasInstructionSet(InstructionSet_AdvSimd))
451459
resultflags.RemoveInstructionSet(InstructionSet_Sve);
460+
if (resultflags.HasInstructionSet(InstructionSet_Sve2) && !resultflags.HasInstructionSet(InstructionSet_Sve))
461+
resultflags.RemoveInstructionSet(InstructionSet_Sve2);
452462
#endif // TARGET_ARM64
453463
#ifdef TARGET_RISCV64
454464
if (resultflags.HasInstructionSet(InstructionSet_Zbb) && !resultflags.HasInstructionSet(InstructionSet_RiscV64Base))
@@ -889,6 +899,10 @@ inline const char *InstructionSetToString(CORINFO_InstructionSet instructionSet)
889899
return "Sve";
890900
case InstructionSet_Sve_Arm64 :
891901
return "Sve_Arm64";
902+
case InstructionSet_Sve2 :
903+
return "Sve2";
904+
case InstructionSet_Sve2_Arm64 :
905+
return "Sve2_Arm64";
892906
#endif // TARGET_ARM64
893907
#ifdef TARGET_RISCV64
894908
case InstructionSet_RiscV64Base :
@@ -1174,6 +1188,7 @@ inline CORINFO_InstructionSet InstructionSetFromR2RInstructionSet(ReadyToRunInst
11741188
case READYTORUN_INSTRUCTION_VectorT128: return InstructionSet_VectorT128;
11751189
case READYTORUN_INSTRUCTION_Rcpc2: return InstructionSet_Rcpc2;
11761190
case READYTORUN_INSTRUCTION_Sve: return InstructionSet_Sve;
1191+
case READYTORUN_INSTRUCTION_Sve2: return InstructionSet_Sve2;
11771192
#endif // TARGET_ARM64
11781193
#ifdef TARGET_RISCV64
11791194
case READYTORUN_INSTRUCTION_RiscV64Base: return InstructionSet_RiscV64Base;

‎src/coreclr/inc/jiteeversionguid.h

+6-6
Original file line numberDiff line numberDiff line change
@@ -37,11 +37,11 @@
3737

3838
#include <minipal/guid.h>
3939

40-
constexpr GUID JITEEVersionIdentifier = { /* 13de8232-0528-42ca-b2b8-4fc592a9adb9 */
41-
0x13de8232,
42-
0x0528,
43-
0x42ca,
44-
{0xb2, 0xb8, 0x4f, 0xc5, 0x92, 0xa9, 0xad, 0xb9}
45-
};
40+
constexpr GUID JITEEVersionIdentifier = { /* 63dcb8b8-1f9d-43d8-bb09-bf5d8bf85ad4 */
41+
0x63dcb8b8,
42+
0x1f9d,
43+
0x43d8,
44+
{0xbb, 0x09, 0xbf, 0x5d, 0x8b, 0xf8, 0x5a, 0xd4}
45+
};
4646

4747
#endif // JIT_EE_VERSIONING_GUID_H

‎src/coreclr/inc/readytoruninstructionset.h

+1
Original file line numberDiff line numberDiff line change
@@ -66,6 +66,7 @@ enum ReadyToRunInstructionSet
6666
READYTORUN_INSTRUCTION_RiscV64Base=56,
6767
READYTORUN_INSTRUCTION_Zba=57,
6868
READYTORUN_INSTRUCTION_Zbb=58,
69+
READYTORUN_INSTRUCTION_Sve2=59,
6970

7071
};
7172

‎src/coreclr/jit/compiler.cpp

+5
Original file line numberDiff line numberDiff line change
@@ -6087,6 +6087,11 @@ int Compiler::compCompile(CORINFO_MODULE_HANDLE classPtr,
60876087
{
60886088
instructionSetFlags.AddInstructionSet(InstructionSet_Sve);
60896089
}
6090+
6091+
if (JitConfig.EnableArm64Sve2() != 0)
6092+
{
6093+
instructionSetFlags.AddInstructionSet(InstructionSet_Sve2);
6094+
}
60906095
#elif defined(TARGET_XARCH)
60916096
if (info.compMatchedVM)
60926097
{

‎src/coreclr/jit/hwintrinsic.cpp

+2
Original file line numberDiff line numberDiff line change
@@ -857,6 +857,7 @@ static const HWIntrinsicIsaRange hwintrinsicIsaRangeArray[] = {
857857
{ NI_Illegal, NI_Illegal }, // VectorT128
858858
{ NI_Illegal, NI_Illegal }, // Rcpc2
859859
{ FIRST_NI_Sve, LAST_NI_Sve },
860+
{ NI_Illegal, NI_Illegal }, // Sve2
860861
{ FIRST_NI_ArmBase_Arm64, LAST_NI_ArmBase_Arm64 },
861862
{ FIRST_NI_AdvSimd_Arm64, LAST_NI_AdvSimd_Arm64 },
862863
{ NI_Illegal, NI_Illegal }, // Aes_Arm64
@@ -866,6 +867,7 @@ static const HWIntrinsicIsaRange hwintrinsicIsaRangeArray[] = {
866867
{ NI_Illegal, NI_Illegal }, // Sha1_Arm64
867868
{ NI_Illegal, NI_Illegal }, // Sha256_Arm64
868869
{ NI_Illegal, NI_Illegal }, // Sve_Arm64
870+
{ NI_Illegal, NI_Illegal }, // Sve2_Arm64
869871
#else
870872
#error Unsupported platform
871873
#endif

‎src/coreclr/jit/hwintrinsicarm64.cpp

+8
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,8 @@ static CORINFO_InstructionSet Arm64VersionOfIsa(CORINFO_InstructionSet isa)
3636
return InstructionSet_Rdm_Arm64;
3737
case InstructionSet_Sve:
3838
return InstructionSet_Sve_Arm64;
39+
case InstructionSet_Sve2:
40+
return InstructionSet_Sve2_Arm64;
3941
default:
4042
return InstructionSet_NONE;
4143
}
@@ -99,6 +101,10 @@ static CORINFO_InstructionSet lookupInstructionSet(const char* className)
99101
{
100102
return InstructionSet_Sha256;
101103
}
104+
if (strcmp(className, "Sve2") == 0)
105+
{
106+
return InstructionSet_Sve2;
107+
}
102108
if (strcmp(className, "Sve") == 0)
103109
{
104110
return InstructionSet_Sve;
@@ -212,6 +218,8 @@ bool HWIntrinsicInfo::isFullyImplementedIsa(CORINFO_InstructionSet isa)
212218
case InstructionSet_Sha256_Arm64:
213219
case InstructionSet_Sve:
214220
case InstructionSet_Sve_Arm64:
221+
case InstructionSet_Sve2:
222+
case InstructionSet_Sve2_Arm64:
215223
case InstructionSet_Vector64:
216224
case InstructionSet_Vector128:
217225
return true;

‎src/coreclr/jit/jitconfigvalues.h

+1
Original file line numberDiff line numberDiff line change
@@ -439,6 +439,7 @@ RELEASE_CONFIG_INTEGER(EnableArm64Rdm, "EnableArm64Rdm",
439439
RELEASE_CONFIG_INTEGER(EnableArm64Sha1, "EnableArm64Sha1", 1) // Allows Arm64 Sha1+ hardware intrinsics to be disabled
440440
RELEASE_CONFIG_INTEGER(EnableArm64Sha256, "EnableArm64Sha256", 1) // Allows Arm64 Sha256+ hardware intrinsics to be disabled
441441
RELEASE_CONFIG_INTEGER(EnableArm64Sve, "EnableArm64Sve", 1) // Allows Arm64 Sve+ hardware intrinsics to be disabled
442+
RELEASE_CONFIG_INTEGER(EnableArm64Sve2, "EnableArm64Sve2", 1) // Allows Arm64 Sve2+ hardware intrinsics to be disabled
442443
#elif defined(TARGET_RISCV64)
443444
RELEASE_CONFIG_INTEGER(EnableRiscV64Zba, "EnableRiscV64Zba", 1) // Allows RiscV64 Zba hardware intrinsics to be disabled
444445
RELEASE_CONFIG_INTEGER(EnableRiscV64Zbb, "EnableRiscV64Zbb", 1) // Allows RiscV64 Zbb hardware intrinsics to be disabled

‎src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs

+1
Original file line numberDiff line numberDiff line change
@@ -69,6 +69,7 @@ public enum ReadyToRunInstructionSet
6969
RiscV64Base=56,
7070
Zba=57,
7171
Zbb=58,
72+
Sve2=59,
7273

7374
}
7475
}

‎src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs

+2
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,8 @@ public static class ReadyToRunInstructionSetHelper
4848
case InstructionSet.ARM64_Rcpc2: return ReadyToRunInstructionSet.Rcpc2;
4949
case InstructionSet.ARM64_Sve: return ReadyToRunInstructionSet.Sve;
5050
case InstructionSet.ARM64_Sve_Arm64: return ReadyToRunInstructionSet.Sve;
51+
case InstructionSet.ARM64_Sve2: return ReadyToRunInstructionSet.Sve2;
52+
case InstructionSet.ARM64_Sve2_Arm64: return ReadyToRunInstructionSet.Sve2;
5153

5254
default: throw new Exception("Unknown instruction set");
5355
}

‎src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs

+33-9
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,7 @@ public enum InstructionSet
3232
ARM64_VectorT128 = InstructionSet_ARM64.VectorT128,
3333
ARM64_Rcpc2 = InstructionSet_ARM64.Rcpc2,
3434
ARM64_Sve = InstructionSet_ARM64.Sve,
35+
ARM64_Sve2 = InstructionSet_ARM64.Sve2,
3536
ARM64_ArmBase_Arm64 = InstructionSet_ARM64.ArmBase_Arm64,
3637
ARM64_AdvSimd_Arm64 = InstructionSet_ARM64.AdvSimd_Arm64,
3738
ARM64_Aes_Arm64 = InstructionSet_ARM64.Aes_Arm64,
@@ -41,6 +42,7 @@ public enum InstructionSet
4142
ARM64_Sha1_Arm64 = InstructionSet_ARM64.Sha1_Arm64,
4243
ARM64_Sha256_Arm64 = InstructionSet_ARM64.Sha256_Arm64,
4344
ARM64_Sve_Arm64 = InstructionSet_ARM64.Sve_Arm64,
45+
ARM64_Sve2_Arm64 = InstructionSet_ARM64.Sve2_Arm64,
4446
RiscV64_RiscV64Base = InstructionSet_RiscV64.RiscV64Base,
4547
RiscV64_Zba = InstructionSet_RiscV64.Zba,
4648
RiscV64_Zbb = InstructionSet_RiscV64.Zbb,
@@ -213,15 +215,17 @@ public enum InstructionSet_ARM64
213215
VectorT128 = 14,
214216
Rcpc2 = 15,
215217
Sve = 16,
216-
ArmBase_Arm64 = 17,
217-
AdvSimd_Arm64 = 18,
218-
Aes_Arm64 = 19,
219-
Crc32_Arm64 = 20,
220-
Dp_Arm64 = 21,
221-
Rdm_Arm64 = 22,
222-
Sha1_Arm64 = 23,
223-
Sha256_Arm64 = 24,
224-
Sve_Arm64 = 25,
218+
Sve2 = 17,
219+
ArmBase_Arm64 = 18,
220+
AdvSimd_Arm64 = 19,
221+
Aes_Arm64 = 20,
222+
Crc32_Arm64 = 21,
223+
Dp_Arm64 = 22,
224+
Rdm_Arm64 = 23,
225+
Sha1_Arm64 = 24,
226+
Sha256_Arm64 = 25,
227+
Sve_Arm64 = 26,
228+
Sve2_Arm64 = 27,
225229
}
226230

227231
public enum InstructionSet_RiscV64
@@ -587,6 +591,10 @@ public static InstructionSetFlags ExpandInstructionSetByImplicationHelper(Target
587591
resultflags.AddInstructionSet(InstructionSet.ARM64_Sve_Arm64);
588592
if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sve_Arm64))
589593
resultflags.AddInstructionSet(InstructionSet.ARM64_Sve);
594+
if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sve2))
595+
resultflags.AddInstructionSet(InstructionSet.ARM64_Sve2_Arm64);
596+
if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sve2_Arm64))
597+
resultflags.AddInstructionSet(InstructionSet.ARM64_Sve2);
590598
if (resultflags.HasInstructionSet(InstructionSet.ARM64_AdvSimd))
591599
resultflags.AddInstructionSet(InstructionSet.ARM64_ArmBase);
592600
if (resultflags.HasInstructionSet(InstructionSet.ARM64_Aes))
@@ -609,6 +617,8 @@ public static InstructionSetFlags ExpandInstructionSetByImplicationHelper(Target
609617
resultflags.AddInstructionSet(InstructionSet.ARM64_AdvSimd);
610618
if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sve))
611619
resultflags.AddInstructionSet(InstructionSet.ARM64_AdvSimd);
620+
if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sve2))
621+
resultflags.AddInstructionSet(InstructionSet.ARM64_Sve);
612622
break;
613623

614624
case TargetArchitecture.RiscV64:
@@ -1027,6 +1037,8 @@ private static InstructionSetFlags ExpandInstructionSetByReverseImplicationHelpe
10271037
resultflags.AddInstructionSet(InstructionSet.ARM64_Sha256);
10281038
if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sve_Arm64))
10291039
resultflags.AddInstructionSet(InstructionSet.ARM64_Sve);
1040+
if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sve2_Arm64))
1041+
resultflags.AddInstructionSet(InstructionSet.ARM64_Sve2);
10301042
if (resultflags.HasInstructionSet(InstructionSet.ARM64_ArmBase))
10311043
resultflags.AddInstructionSet(InstructionSet.ARM64_AdvSimd);
10321044
if (resultflags.HasInstructionSet(InstructionSet.ARM64_ArmBase))
@@ -1049,6 +1061,8 @@ private static InstructionSetFlags ExpandInstructionSetByReverseImplicationHelpe
10491061
resultflags.AddInstructionSet(InstructionSet.ARM64_VectorT128);
10501062
if (resultflags.HasInstructionSet(InstructionSet.ARM64_AdvSimd))
10511063
resultflags.AddInstructionSet(InstructionSet.ARM64_Sve);
1064+
if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sve))
1065+
resultflags.AddInstructionSet(InstructionSet.ARM64_Sve2);
10521066
break;
10531067

10541068
case TargetArchitecture.RiscV64:
@@ -1443,6 +1457,7 @@ public static IEnumerable<InstructionSetInfo> ArchitectureToValidInstructionSets
14431457
yield return new InstructionSetInfo("vectort128", "VectorT128", InstructionSet.ARM64_VectorT128, true);
14441458
yield return new InstructionSetInfo("rcpc2", "", InstructionSet.ARM64_Rcpc2, true);
14451459
yield return new InstructionSetInfo("sve", "Sve", InstructionSet.ARM64_Sve, true);
1460+
yield return new InstructionSetInfo("sve2", "Sve2", InstructionSet.ARM64_Sve2, true);
14461461
break;
14471462

14481463
case TargetArchitecture.RiscV64:
@@ -1575,6 +1590,8 @@ public void Set64BitInstructionSetVariants(TargetArchitecture architecture)
15751590
AddInstructionSet(InstructionSet.ARM64_Sha256_Arm64);
15761591
if (HasInstructionSet(InstructionSet.ARM64_Sve))
15771592
AddInstructionSet(InstructionSet.ARM64_Sve_Arm64);
1593+
if (HasInstructionSet(InstructionSet.ARM64_Sve2))
1594+
AddInstructionSet(InstructionSet.ARM64_Sve2_Arm64);
15781595
break;
15791596

15801597
case TargetArchitecture.RiscV64:
@@ -1659,6 +1676,7 @@ public void Set64BitInstructionSetVariantsUnconditionally(TargetArchitecture arc
16591676
AddInstructionSet(InstructionSet.ARM64_Sha1_Arm64);
16601677
AddInstructionSet(InstructionSet.ARM64_Sha256_Arm64);
16611678
AddInstructionSet(InstructionSet.ARM64_Sve_Arm64);
1679+
AddInstructionSet(InstructionSet.ARM64_Sve2_Arm64);
16621680
break;
16631681

16641682
case TargetArchitecture.RiscV64:
@@ -1832,6 +1850,12 @@ public static InstructionSet LookupPlatformIntrinsicInstructionSet(TargetArchite
18321850
else
18331851
{ return InstructionSet.ARM64_Sve; }
18341852

1853+
case "Sve2":
1854+
if (nestedTypeName == "Arm64")
1855+
{ return InstructionSet.ARM64_Sve2_Arm64; }
1856+
else
1857+
{ return InstructionSet.ARM64_Sve2; }
1858+
18351859
}
18361860
break;
18371861

‎src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt

+3
Original file line numberDiff line numberDiff line change
@@ -216,6 +216,7 @@ instructionset ,ARM64 , ,Rcpc ,26 ,Rcpc
216216
instructionset ,ARM64 ,VectorT128 , ,39 ,VectorT128 ,vectort128
217217
instructionset ,ARM64 , ,Rcpc2 ,42 ,Rcpc2 ,rcpc2
218218
instructionset ,ARM64 ,Sve , ,43 ,Sve ,sve
219+
instructionset ,ARM64 ,Sve2 , ,59 ,Sve2 ,sve2
219220

220221
instructionset64bit,ARM64 ,ArmBase
221222
instructionset64bit,ARM64 ,AdvSimd
@@ -226,6 +227,7 @@ instructionset64bit,ARM64 ,Rdm
226227
instructionset64bit,ARM64 ,Sha1
227228
instructionset64bit,ARM64 ,Sha256
228229
instructionset64bit,ARM64 ,Sve
230+
instructionset64bit,ARM64 ,Sve2
229231

230232
vectorinstructionset,ARM64,Vector64
231233
vectorinstructionset,ARM64,Vector128
@@ -241,6 +243,7 @@ implication ,ARM64 ,Vector64 ,AdvSimd
241243
implication ,ARM64 ,Vector128 ,AdvSimd
242244
implication ,ARM64 ,VectorT128 ,AdvSimd
243245
implication ,ARM64 ,Sve ,AdvSimd
246+
implication ,ARM64 ,Sve2 ,Sve
244247

245248
; Definition of Riscv64 instruction sets
246249
definearch ,RiscV64 ,64Bit ,RiscV64, RiscV64

‎src/coreclr/vm/codeman.cpp

+5
Original file line numberDiff line numberDiff line change
@@ -1526,6 +1526,11 @@ void EEJitManager::SetCpuInfo()
15261526
// if ((maxVectorTLength >= sveLengthFromOS) || (maxVectorTBitWidth == 0))
15271527
{
15281528
CPUCompileFlags.Set(InstructionSet_Sve);
1529+
1530+
if (((cpuFeatures & ARM64IntrinsicConstants_Sve2) != 0) && CLRConfig::GetConfigValue(CLRConfig::EXTERNAL_EnableArm64Sve2))
1531+
{
1532+
CPUCompileFlags.Set(InstructionSet_Sve2);
1533+
}
15291534
}
15301535
}
15311536

‎src/native/minipal/cpufeatures.c

+17
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,10 @@
1919
#define PF_ARM_SVE_INSTRUCTIONS_AVAILABLE (46)
2020
#endif
2121

22+
#ifndef PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE
23+
#define PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE (47)
24+
#endif
25+
2226
#else // HOST_WINDOWS
2327

2428
#include "minipalconfig.h"
@@ -44,6 +48,9 @@
4448
#ifndef HWCAP_SVE
4549
#define HWCAP_SVE (1 << 22)
4650
#endif
51+
#ifndef HWCAP2_SVE2
52+
#define HWCAP2_SVE2 (1 << 1)
53+
#endif
4754

4855
#endif
4956

@@ -444,6 +451,11 @@ int minipal_getcpufeatures(void)
444451
if (hwCap & HWCAP_SVE)
445452
result |= ARM64IntrinsicConstants_Sve;
446453

454+
unsigned long hwCap2 = getauxval(AT_HWCAP2);
455+
456+
if (hwCap2 & HWCAP2_SVE2)
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result |= ARM64IntrinsicConstants_Sve2;
458+
447459
#else // !HAVE_AUXV_HWCAP_H
448460

449461
#if HAVE_SYSCTLBYNAME
@@ -534,6 +546,11 @@ int minipal_getcpufeatures(void)
534546
result |= ARM64IntrinsicConstants_Sve;
535547
}
536548

549+
if (IsProcessorFeaturePresent(PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE))
550+
{
551+
result |= ARM64IntrinsicConstants_Sve2;
552+
}
553+
537554
#endif // HOST_WINDOWS
538555

539556
#endif // HOST_ARM64

‎src/native/minipal/cpufeatures.h

+1
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,7 @@ enum ARM64IntrinsicConstants
5252
ARM64IntrinsicConstants_Rcpc = 0x0100,
5353
ARM64IntrinsicConstants_Rcpc2 = 0x0200,
5454
ARM64IntrinsicConstants_Sve = 0x0400,
55+
ARM64IntrinsicConstants_Sve2 = 0x0800,
5556
};
5657

5758
#include <assert.h>

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