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snickolls-armsnickolls-arm
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Add ARM64 encodings for groups IF_SVE_HO,HP,HS (#99058)
* Add ARM64 encodings for groups IF_SVE_HO,HP,HS * Fix missing code emission after merge * Refactor to use fewer encoding groups * Address review comments
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4 files changed

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Diff for: ‎src/coreclr/jit/codegenarm64test.cpp

+84
Original file line numberDiff line numberDiff line change
@@ -5173,6 +5173,90 @@ void CodeGen::genArm64EmitterUnitTestsSve()
51735173
theEmitter->emitIns_R_R_R(INS_sve_bfsub, EA_SCALABLE, REG_V12, REG_P6, REG_V13,
51745174
INS_OPTS_SCALABLE_H); // BFSUB <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H
51755175

5176+
// IF_SVE_HO_3A
5177+
theEmitter->emitIns_R_R_R(INS_sve_bfcvt, EA_SCALABLE, REG_V3, REG_P2, REG_V9,
5178+
INS_OPTS_S_TO_H); // BFCVT <Zd>.H, <Pg>/M, <Zn>.S
5179+
5180+
// IF_SVE_HO_3B
5181+
theEmitter->emitIns_R_R_R(INS_sve_fcvt, EA_SCALABLE, REG_V7, REG_P7, REG_V1,
5182+
INS_OPTS_S_TO_D); // FCVT <Zd>.D, <Pg>/M, <Zn>.S
5183+
theEmitter->emitIns_R_R_R(INS_sve_fcvt, EA_SCALABLE, REG_V29, REG_P3, REG_V12,
5184+
INS_OPTS_D_TO_S); // FCVT <Zd>.S, <Pg>/M, <Zn>.D
5185+
theEmitter->emitIns_R_R_R(INS_sve_fcvt, EA_SCALABLE, REG_V0, REG_P4, REG_V13,
5186+
INS_OPTS_D_TO_H); // FCVT <Zd>.H, <Pg>/M, <Zn>.D
5187+
theEmitter->emitIns_R_R_R(INS_sve_fcvt, EA_SCALABLE, REG_V1, REG_P5, REG_V14,
5188+
INS_OPTS_H_TO_D); // FCVT <Zd>.D, <Pg>/M, <Zn>.H
5189+
theEmitter->emitIns_R_R_R(INS_sve_fcvt, EA_SCALABLE, REG_V2, REG_P6, REG_V15,
5190+
INS_OPTS_S_TO_H); // FCVT <Zd>.H, <Pg>/M, <Zn>.S
5191+
theEmitter->emitIns_R_R_R(INS_sve_fcvt, EA_SCALABLE, REG_V3, REG_P7, REG_V16,
5192+
INS_OPTS_H_TO_S); // FCVT <Zd>.S, <Pg>/M, <Zn>.H
5193+
5194+
// IF_SVE_HO_3C
5195+
theEmitter->emitIns_R_R_R(INS_sve_fcvtx, EA_SCALABLE, REG_V2, REG_P0, REG_V6,
5196+
INS_OPTS_D_TO_S); // FCVTX <Zd>.S, <Pg>/M, <Zn>.D
5197+
5198+
// IF_SVE_HP_3B
5199+
theEmitter->emitIns_R_R_R(INS_sve_fcvtzs, EA_SCALABLE, REG_V9, REG_P1, REG_V3,
5200+
INS_OPTS_SCALABLE_S); // FCVTZS <Zd>.S, <Pg>/M, <Zn>.S
5201+
theEmitter->emitIns_R_R_R(INS_sve_fcvtzs, EA_SCALABLE, REG_V5, REG_P0, REG_V24,
5202+
INS_OPTS_S_TO_D); // FCVTZS <Zd>.D, <Pg>/M, <Zn>.S
5203+
theEmitter->emitIns_R_R_R(INS_sve_fcvtzs, EA_SCALABLE, REG_V12, REG_P3, REG_V6,
5204+
INS_OPTS_D_TO_S); // FCVTZS <Zd>.S, <Pg>/M, <Zn>.D
5205+
theEmitter->emitIns_R_R_R(INS_sve_fcvtzs, EA_SCALABLE, REG_V2, REG_P1, REG_V17,
5206+
INS_OPTS_SCALABLE_D); // FCVTZS <Zd>.D, <Pg>/M, <Zn>.D
5207+
theEmitter->emitIns_R_R_R(INS_sve_fcvtzs, EA_SCALABLE, REG_V3, REG_P2, REG_V18,
5208+
INS_OPTS_SCALABLE_H); // FCVTZS <Zd>.H, <Pg>/M, <Zn>.H
5209+
theEmitter->emitIns_R_R_R(INS_sve_fcvtzs, EA_SCALABLE, REG_V4, REG_P3, REG_V19,
5210+
INS_OPTS_H_TO_S); // FCVTZS <Zd>.S, <Pg>/M, <Zn>.H
5211+
theEmitter->emitIns_R_R_R(INS_sve_fcvtzs, EA_SCALABLE, REG_V5, REG_P4, REG_V20,
5212+
INS_OPTS_H_TO_D); // FCVTZS <Zd>.D, <Pg>/M, <Zn>.H
5213+
5214+
theEmitter->emitIns_R_R_R(INS_sve_fcvtzu, EA_SCALABLE, REG_V3, REG_P2, REG_V10,
5215+
INS_OPTS_SCALABLE_S); // FCVTZU <Zd>.S, <Pg>/M, <Zn>.S
5216+
theEmitter->emitIns_R_R_R(INS_sve_fcvtzu, EA_SCALABLE, REG_V10, REG_P7, REG_V1,
5217+
INS_OPTS_S_TO_D); // FCVTZU <Zd>.D, <Pg>/M, <Zn>.S
5218+
theEmitter->emitIns_R_R_R(INS_sve_fcvtzu, EA_SCALABLE, REG_V4, REG_P3, REG_V13,
5219+
INS_OPTS_D_TO_S); // FCVTZU <Zd>.S, <Pg>/M, <Zn>.D
5220+
theEmitter->emitIns_R_R_R(INS_sve_fcvtzu, EA_SCALABLE, REG_V22, REG_P6, REG_V4,
5221+
INS_OPTS_SCALABLE_D); // FCVTZU <Zd>.D, <Pg>/M, <Zn>.D
5222+
theEmitter->emitIns_R_R_R(INS_sve_fcvtzu, EA_SCALABLE, REG_V23, REG_P7, REG_V5,
5223+
INS_OPTS_SCALABLE_H); // FCVTZU <Zd>.H, <Pg>/M, <Zn>.H
5224+
theEmitter->emitIns_R_R_R(INS_sve_fcvtzu, EA_SCALABLE, REG_V24, REG_P0, REG_V6,
5225+
INS_OPTS_H_TO_S); // FCVTZU <Zd>.S, <Pg>/M, <Zn>.H
5226+
theEmitter->emitIns_R_R_R(INS_sve_fcvtzu, EA_SCALABLE, REG_V25, REG_P1, REG_V7,
5227+
INS_OPTS_H_TO_D); // FCVTZU <Zd>.D, <Pg>/M, <Zn>.H
5228+
5229+
// IF_SVE_HS_3A
5230+
theEmitter->emitIns_R_R_R(INS_sve_scvtf, EA_SCALABLE, REG_V19, REG_P2, REG_V8,
5231+
INS_OPTS_SCALABLE_S); // SCVTF <Zd>.S, <Pg>/M, <Zn>.S
5232+
theEmitter->emitIns_R_R_R(INS_sve_scvtf, EA_SCALABLE, REG_V1, REG_P5, REG_V19,
5233+
INS_OPTS_S_TO_D); // SCVTF <Zd>.D, <Pg>/M, <Zn>.S
5234+
theEmitter->emitIns_R_R_R(INS_sve_scvtf, EA_SCALABLE, REG_V4, REG_P0, REG_V14,
5235+
INS_OPTS_D_TO_S); // SCVTF <Zd>.S, <Pg>/M, <Zn>.D
5236+
theEmitter->emitIns_R_R_R(INS_sve_scvtf, EA_SCALABLE, REG_V0, REG_P0, REG_V0,
5237+
INS_OPTS_SCALABLE_D); // SCVTF <Zd>.D, <Pg>/M, <Zn>.D
5238+
theEmitter->emitIns_R_R_R(INS_sve_scvtf, EA_SCALABLE, REG_V12, REG_P5, REG_V14,
5239+
INS_OPTS_SCALABLE_H); // SCVTF <Zd>.H, <Pg>/M, <Zn>.H
5240+
theEmitter->emitIns_R_R_R(INS_sve_scvtf, EA_SCALABLE, REG_V14, REG_P7, REG_V16,
5241+
INS_OPTS_S_TO_H); // SCVTF <Zd>.H, <Pg>/M, <Zn>.S
5242+
theEmitter->emitIns_R_R_R(INS_sve_scvtf, EA_SCALABLE, REG_V16, REG_P1, REG_V18,
5243+
INS_OPTS_D_TO_H); // SCVTF <Zd>.H, <Pg>/M, <Zn>.D
5244+
5245+
theEmitter->emitIns_R_R_R(INS_sve_ucvtf, EA_SCALABLE, REG_V17, REG_P6, REG_V11,
5246+
INS_OPTS_SCALABLE_S); // UCVTF <Zd>.S, <Pg>/M, <Zn>.S
5247+
theEmitter->emitIns_R_R_R(INS_sve_ucvtf, EA_SCALABLE, REG_V3, REG_P3, REG_V20,
5248+
INS_OPTS_S_TO_D); // UCVTF <Zd>.D, <Pg>/M, <Zn>.S
5249+
theEmitter->emitIns_R_R_R(INS_sve_ucvtf, EA_SCALABLE, REG_V8, REG_P1, REG_V7,
5250+
INS_OPTS_D_TO_S); // UCVTF <Zd>.S, <Pg>/M, <Zn>.D
5251+
theEmitter->emitIns_R_R_R(INS_sve_ucvtf, EA_SCALABLE, REG_V8, REG_P4, REG_V9,
5252+
INS_OPTS_SCALABLE_D); // UCVTF <Zd>.D, <Pg>/M, <Zn>.D
5253+
theEmitter->emitIns_R_R_R(INS_sve_ucvtf, EA_SCALABLE, REG_V13, REG_P6, REG_V15,
5254+
INS_OPTS_SCALABLE_H); // UCVTF <Zd>.H, <Pg>/M, <Zn>.H
5255+
theEmitter->emitIns_R_R_R(INS_sve_ucvtf, EA_SCALABLE, REG_V15, REG_P0, REG_V17,
5256+
INS_OPTS_S_TO_H); // UCVTF <Zd>.H, <Pg>/M, <Zn>.S
5257+
theEmitter->emitIns_R_R_R(INS_sve_ucvtf, EA_SCALABLE, REG_V17, REG_P2, REG_V19,
5258+
INS_OPTS_D_TO_H); // UCVTF <Zd>.H, <Pg>/M, <Zn>.D
5259+
51765260
// IF_SVE_HT_4A
51775261
theEmitter->emitIns_R_R_R_R(INS_sve_facge, EA_SCALABLE, REG_P0, REG_P0, REG_V10, REG_V31,
51785262
INS_OPTS_SCALABLE_H); // FACGE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>

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