SystemVerilog: concurrent assertion items go into module namespace #575
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I can see that the commit does what the above message says, but why is this the right thing to do? |
One argument in favour is that it appears to be what other tools are doing (e.g., XCelium uses the same scheme for assertions with label, and |
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I of course wish that the IEEE standard be clear about it, but couldn't find anything. |
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Concurrent assertion items (assert/assume/cover) that are module items with a block label go into the module name space, not into a separate "property" name space. Assertion items without block item now get a label based on the kind of the assertion item (assert/assume/cover).
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tautschnig
approved these changes
Jun 25, 2024
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Concurrent assertion items (assert/assume/cover) that are module items with a block label go into the module name space, not into a separate "property" name space.
Assertion items without block item now get a label based on the kind of the assertion item (assert/assume/cover).