From 6360d2277a6539a962c8c3fc9c5082a3f4d42939 Mon Sep 17 00:00:00 2001
From: Daniel Kroening <dkr@amazon.com>
Date: Sat, 16 Nov 2024 21:24:04 +0000
Subject: [PATCH 1/2] Verilog: test to track constant folding for all
 expressions

---
 .../verilog/expressions/constants2.desc       |  8 +++
 regression/verilog/expressions/constants2.sv  | 52 +++++++++++++++++++
 2 files changed, 60 insertions(+)
 create mode 100644 regression/verilog/expressions/constants2.desc
 create mode 100644 regression/verilog/expressions/constants2.sv

diff --git a/regression/verilog/expressions/constants2.desc b/regression/verilog/expressions/constants2.desc
new file mode 100644
index 00000000..44dd1d18
--- /dev/null
+++ b/regression/verilog/expressions/constants2.desc
@@ -0,0 +1,8 @@
+CORE
+constants2.sv
+--bound 0
+^no properties$
+^EXIT=10$
+^SIGNAL=0$
+--
+^warning: ignoring
diff --git a/regression/verilog/expressions/constants2.sv b/regression/verilog/expressions/constants2.sv
new file mode 100644
index 00000000..0d9e6a30
--- /dev/null
+++ b/regression/verilog/expressions/constants2.sv
@@ -0,0 +1,52 @@
+module main;
+
+  // Test for 1800-2017 11.2.1 Constant expressions
+  // Following the order in 1800-2017 Table 11-1
+  parameter p01 = 1?2:3;
+  parameter p02 = +1;
+  parameter p03 = -1;  
+  parameter p04 = !0;
+  parameter p05 = ~1;
+  parameter p06 = &1;
+  parameter p07 = ~&1;
+  parameter p08 = |1;
+  parameter p09 = ~|1;
+  parameter p10 = ^1;
+  parameter p11 = ~^1;
+  parameter p12 = ^~1;
+  parameter p13 = 1+1;
+  parameter p14 = 1-1;
+  parameter p15 = 1*1;
+  parameter p16 = 1/1;
+  parameter p17 = 1**1;
+  parameter p18 = 1%1;
+  parameter p19 = 1&1;
+  parameter p20 = 1|1;
+  parameter p21 = 1^1;
+//  parameter p22 = 1^~1;
+//  parameter p23 = 1~^1;
+  parameter p24 = 1>>1;
+  parameter p25 = 1<<1;
+  parameter p26 = 1>>>1;
+  parameter p27 = 1<<<1;
+  parameter p28 = 1&&1;
+  parameter p29 = 1||1;
+  parameter p30 = 1->1;
+//  parameter p31 = 1<->1;
+  parameter p32 = 1<1;
+  parameter p33 = 1<=1;
+  parameter p34 = 1>1;
+  parameter p35 = 1>=1;
+//  parameter p36 = 1===1;
+//  parameter p37 = 1!==1;
+  parameter p38 = 1==1;
+  parameter p39 = 1!=1;
+//  parameter p40 = 1==?1;
+//  parameter p41 = 1!=?1;
+//  parameter p42 = 1 inside {1};
+  parameter p43 = {1'b1, 1'b0};
+  parameter p44 = {2{1'b1}};
+//  parameter p45 = {<<{3'b101}};
+//  parameter p46 = {>>{3'b101}};
+
+endmodule

From 01eca40804167a8f8dd588ba54e4a49f277a5099 Mon Sep 17 00:00:00 2001
From: Daniel Kroening <dkr@amazon.com>
Date: Sat, 16 Nov 2024 21:27:55 +0000
Subject: [PATCH 2/2] Verilog: grammar for binary ^~ xnor

---
 src/verilog/parser.y | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/verilog/parser.y b/src/verilog/parser.y
index 8def3f65..d09a3d94 100644
--- a/src/verilog/parser.y
+++ b/src/verilog/parser.y
@@ -3848,6 +3848,8 @@ expression:
 		{ init($$, ID_bitxor); mto($$, $1); mto($$, $3); }
 	| expression TOK_TILDECARET expression
 		{ init($$, ID_bitxnor); mto($$, $1); mto($$, $3); }
+	| expression TOK_CARETTILDE expression
+		{ init($$, ID_bitxnor); mto($$, $1); mto($$, $3); }
 	| expression TOK_LESSLESS expression
 		{ init($$, ID_shl); mto($$, $1); mto($$, $3); }
 	| expression TOK_LESSLESSLESS expression