Verilog: test for concatenation that contains an enum

diffblue · Nov 19, 2024 · f340d83 · f340d83
1 parent 820b050
commit f340d83
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diff --git a/regression/verilog/expressions/concatenation6.desc b/regression/verilog/expressions/concatenation6.desc
@@ -0,0 +1,8 @@
+CORE
+concatenation6.sv
+--bound 0
+^\[.*\] always main\.x == \{ 0, 1 \}: PROVED up to bound 0$
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
diff --git a/regression/verilog/expressions/concatenation6.sv b/regression/verilog/expressions/concatenation6.sv
@@ -0,0 +1,10 @@
+module main;
+
+  typedef enum { RED, YELLOW1, GREEN, YELLOW2 } my_enum;
+
+  // enums are allowed in concatenations
+  wire [63:0] x = { RED, YELLOW1 };
+
+  assert final (x == {32'd0, 32'd1});
+
+endmodule