From e9e73f977bc0debeb71ff4231560656bd59aa461 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Matthias=20G=C3=BCdemann?= Date: Tue, 30 May 2017 11:34:38 +0200 Subject: [PATCH] Adapt print/messaget API, get_error_found --- src/vcegar/abstractor.cpp | 10 ++++++---- src/vcegar/modelchecker_smv.cpp | 2 +- src/verilog/verilog_language.cpp | 2 +- src/verilog/verilog_typecheck_expr.cpp | 7 +++++-- src/vhdl/parser.y | 3 ++- 5 files changed, 15 insertions(+), 9 deletions(-) diff --git a/src/vcegar/abstractor.cpp b/src/vcegar/abstractor.cpp index 2102978c2..8a5597c8e 100644 --- a/src/vcegar/abstractor.cpp +++ b/src/vcegar/abstractor.cpp @@ -572,8 +572,9 @@ void abstractort::calc_abstract_trans_rel( throw "unexpected result from predabs_sat1.solve()"; } - print(9, "Generated "+ - i2string(trans_cube_set.no_insertions())+" cube(s)"); + debug() <<"Generated " + << i2string(trans_cube_set.no_insertions()) << " cube(s)" + << eom; if(show_cubes) std::cout << trans_cube_set; @@ -693,8 +694,9 @@ void abstractort::calc_abstract_initial_states( } // std::cout<<" The abstract transition relation \n"; - print(9, "Generated "+ - i2string(initial.no_insertions())+" cube(s)\n"); + debug() << "Generated " << + << i2string(initial.no_insertions()) <, " cube(s)\n" + << eom; if(show_cubes) std::cout << initial; diff --git a/src/vcegar/modelchecker_smv.cpp b/src/vcegar/modelchecker_smv.cpp index d5ccf95d1..922346208 100644 --- a/src/vcegar/modelchecker_smv.cpp +++ b/src/vcegar/modelchecker_smv.cpp @@ -164,7 +164,7 @@ bool modelchecker_smvt::read_result_cadence_smv( counterexample); - print(9, "Cadence SMV counterexample sucessfully read"); + debug() << "Cadence SMV counterexample sucessfully read" << eom; return false; } diff --git a/src/verilog/verilog_language.cpp b/src/verilog/verilog_language.cpp index 920a3fa01..32ad6198a 100644 --- a/src/verilog/verilog_language.cpp +++ b/src/verilog/verilog_language.cpp @@ -162,7 +162,7 @@ bool verilog_languaget::typecheck( if(verilog_typecheck(parse_tree, symbol_table, module, get_message_handler())) return true; - print(9, "Synthesis "+module); + debug() << "Synthesis " << module << eom; if(verilog_synthesis(symbol_table, module, get_message_handler(), options)) return true; diff --git a/src/verilog/verilog_typecheck_expr.cpp b/src/verilog/verilog_typecheck_expr.cpp index 03a98c7aa..0228639a1 100644 --- a/src/verilog/verilog_typecheck_expr.cpp +++ b/src/verilog/verilog_typecheck_expr.cpp @@ -2026,6 +2026,9 @@ bool verilog_typecheck( message_handlert &message_handler, const namespacet &ns) { + const unsigned errors_before= + message_handler.get_message_count(messaget::M_ERROR); + verilog_typecheck_exprt verilog_typecheck_expr( ns, module_identifier, message_handler); @@ -2048,6 +2051,6 @@ bool verilog_typecheck( { verilog_typecheck_expr.error() << e << messaget::eom; } - - return verilog_typecheck_expr.get_error_found(); + + return message_handler.get_message_count(messaget::M_ERROR)!=errors_before; } diff --git a/src/vhdl/parser.y b/src/vhdl/parser.y index b76873a40..1396907b3 100644 --- a/src/vhdl/parser.y +++ b/src/vhdl/parser.y @@ -53,7 +53,8 @@ int yyvhdlerror(const char *error_str) source_location.set_line(yyvhdllval.line); source_location.set_file(yyvhdllval.file); - PARSER.print(1, tmp, -1, source_location); + PARSER.error().source_location=source_location; + PARSER.error() << tmp << messaget::eom; return strlen(error_str)+1; }