From f340d8379a8b9de3a0dfcf3b121dbd3ea652bc1a Mon Sep 17 00:00:00 2001
From: Daniel Kroening <dkr@amazon.com>
Date: Mon, 18 Nov 2024 12:21:58 +0000
Subject: [PATCH] Verilog: test for concatenation that contains an enum

---
 regression/verilog/expressions/concatenation6.desc |  8 ++++++++
 regression/verilog/expressions/concatenation6.sv   | 10 ++++++++++
 2 files changed, 18 insertions(+)
 create mode 100644 regression/verilog/expressions/concatenation6.desc
 create mode 100644 regression/verilog/expressions/concatenation6.sv

diff --git a/regression/verilog/expressions/concatenation6.desc b/regression/verilog/expressions/concatenation6.desc
new file mode 100644
index 00000000..28ba6bfe
--- /dev/null
+++ b/regression/verilog/expressions/concatenation6.desc
@@ -0,0 +1,8 @@
+CORE
+concatenation6.sv
+--bound 0
+^\[.*\] always main\.x == \{ 0, 1 \}: PROVED up to bound 0$
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
diff --git a/regression/verilog/expressions/concatenation6.sv b/regression/verilog/expressions/concatenation6.sv
new file mode 100644
index 00000000..d3fc5a90
--- /dev/null
+++ b/regression/verilog/expressions/concatenation6.sv
@@ -0,0 +1,10 @@
+module main;
+
+  typedef enum { RED, YELLOW1, GREEN, YELLOW2 } my_enum;
+
+  // enums are allowed in concatenations
+  wire [63:0] x = { RED, YELLOW1 };
+
+  assert final (x == {32'd0, 32'd1});
+
+endmodule