diff --git a/regression/verilog/synthesis/continuous_assignment_to_variable_systemverilog2.desc b/regression/verilog/synthesis/continuous_assignment_to_variable_systemverilog2.desc
new file mode 100644
index 000000000..f9f4ca764
--- /dev/null
+++ b/regression/verilog/synthesis/continuous_assignment_to_variable_systemverilog2.desc
@@ -0,0 +1,9 @@
+KNOWNBUG
+continuous_assignment_to_variable_systemverilog2.sv
+--bound 1
+^\[main\.cover1\] cover 1: PROVED$
+^EXIT=0$
+^SIGNAL=0$
+--
+--
+This creates inconsistent constraints, which yields UNSAT.
diff --git a/regression/verilog/synthesis/continuous_assignment_to_variable_systemverilog2.sv b/regression/verilog/synthesis/continuous_assignment_to_variable_systemverilog2.sv
new file mode 100644
index 000000000..888907c65
--- /dev/null
+++ b/regression/verilog/synthesis/continuous_assignment_to_variable_systemverilog2.sv
@@ -0,0 +1,15 @@
+module main(input clk);
+
+  bit state = 0;
+
+  always_ff @(posedge clk)
+    state = 1;
+
+  logic data;
+
+  // continuous assignment to variable
+  assign data = state;
+
+  cover1: cover property (@(posedge clk) (1));
+
+endmodule