From 5217d7bc2d63106781524e547205288291529715 Mon Sep 17 00:00:00 2001 From: Daniel Kroening Date: Sat, 2 Dec 2023 05:40:46 -0800 Subject: [PATCH 1/2] introduce SYSTEM_VERILOG_OPERATOR macro The new macro removes redundancy in the Verilog tokenizer. --- src/verilog/scanner.l | 120 +++++++++--------------------------------- 1 file changed, 25 insertions(+), 95 deletions(-) diff --git a/src/verilog/scanner.l b/src/verilog/scanner.l index b79fb1b17..1133bc2e3 100644 --- a/src/verilog/scanner.l +++ b/src/verilog/scanner.l @@ -68,6 +68,12 @@ static void preprocessor() else \ IDENTIFIER; \ } +#define SYSTEM_VERILOG_OPERATOR(token, text) \ + { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG) \ + return token; \ + else \ + yyverilogerror(text " is a System Verilog operator"); \ + } #define VIS_VERILOG_KEYWORD(x) \ { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG || \ PARSER.mode==verilog_parsert::VIS_VERILOG) \ @@ -213,101 +219,25 @@ void verilog_scanner_init() /* System Verilog operators */ -"|->" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG) - return TOK_VERTBARMINUSGREATER; - else - yyverilogerror("|-> is a System Verilog operator"); - } -"|=>" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG) - return TOK_VERTBAREQUALGREATER; - else - yyverilogerror("|=> is a System Verilog operator"); - } -"++" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG) - return TOK_PLUSPLUS; - else - yyverilogerror("++ is a System Verilog operator"); - } -"--" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG) - return TOK_MINUSMINUS; - else - yyverilogerror("-- is a System Verilog operator"); - } -"+=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG) - return TOK_PLUSEQUAL; - else - yyverilogerror("+= is a System Verilog operator"); - } -"+:" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG) - return TOK_PLUSCOLON; - else - yyverilogerror("+: is a System Verilog operator"); - } -"-:" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG) - return TOK_MINUSCOLON; - else - yyverilogerror("-: is a System Verilog operator"); - } -"-=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG) - return TOK_MINUSEQUAL; - else - yyverilogerror("-= is a System Verilog operator"); - } -"*=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG) - return TOK_ASTERICEQUAL; - else - yyverilogerror("*= is a System Verilog operator"); - } -"/=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG) - return TOK_SLASHEQUAL; - else - yyverilogerror("+= is a System Verilog operator"); - } -"%=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG) - return TOK_PERCENTEQUAL; - else - yyverilogerror("%= is a System Verilog operator"); - } -"&=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG) - return TOK_AMPEREQUAL; - else - yyverilogerror("&= is a System Verilog operator"); - } -"^=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG) - return TOK_CARETEQUAL; - else - yyverilogerror("^= is a System Verilog operator"); - } -"|=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG) - return TOK_VERTBAREQUAL; - else - yyverilogerror("|= is a System Verilog operator"); - } -"<<=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG) - return TOK_LESSLESSEQUAL; - else - yyverilogerror("<<= is a System Verilog operator"); - } -">>=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG) - return TOK_GREATERGREATEREQUAL; - else - yyverilogerror(">>= is a System Verilog operator"); - } -"<<<=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG) - return TOK_LESSLESSLESSEQUAL; - else - yyverilogerror("<<<= is a System Verilog operator"); - } -">>>=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG) - return TOK_GREATERGREATERGREATEREQUAL; - else - yyverilogerror(">>>= is a System Verilog operator"); - } -"##" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG) - return TOK_HASHHASH; - else - yyverilogerror("## is a System Verilog operator"); - } +"|->" { SYSTEM_VERILOG_OPERATOR(TOK_VERTBARMINUSGREATER, "|->"); } +"|=>" { SYSTEM_VERILOG_OPERATOR(TOK_VERTBAREQUALGREATER, "|=>"); } +"++" { SYSTEM_VERILOG_OPERATOR(TOK_PLUSPLUS, "++"); } +"--" { SYSTEM_VERILOG_OPERATOR(TOK_MINUSMINUS, "--"); } +"+=" { SYSTEM_VERILOG_OPERATOR(TOK_PLUSEQUAL, "+="); } +"+:" { SYSTEM_VERILOG_OPERATOR(TOK_PLUSCOLON, "+:"); } +"-:" { SYSTEM_VERILOG_OPERATOR(TOK_MINUSCOLON, "-:"); } +"-=" { SYSTEM_VERILOG_OPERATOR(TOK_MINUSEQUAL, "-="); } +"*=" { SYSTEM_VERILOG_OPERATOR(TOK_ASTERICEQUAL, "*="); } +"/=" { SYSTEM_VERILOG_OPERATOR(TOK_SLASHEQUAL, "+="); } +"%=" { SYSTEM_VERILOG_OPERATOR(TOK_PERCENTEQUAL, "%="); } +"&=" { SYSTEM_VERILOG_OPERATOR(TOK_AMPEREQUAL, "&="); } +"^=" { SYSTEM_VERILOG_OPERATOR(TOK_CARETEQUAL, "^="); } +"|=" { SYSTEM_VERILOG_OPERATOR(TOK_VERTBAREQUAL, "|="); } +"<<=" { SYSTEM_VERILOG_OPERATOR(TOK_LESSLESSEQUAL, "<<="); } +">>=" { SYSTEM_VERILOG_OPERATOR(TOK_GREATERGREATEREQUAL, ">>="); } +"<<<=" { SYSTEM_VERILOG_OPERATOR(TOK_LESSLESSLESSEQUAL, "<<<="); } +">>>=" { SYSTEM_VERILOG_OPERATOR(TOK_GREATERGREATERGREATEREQUAL, ">>>="); } +"##" { SYSTEM_VERILOG_OPERATOR(TOK_HASHHASH, "##"); } /* Verilog keywords */ From 46bf1957dbcc05ba19ef4c491ccfab6be59924ba Mon Sep 17 00:00:00 2001 From: Daniel Kroening Date: Sat, 2 Dec 2023 05:41:59 -0800 Subject: [PATCH 2/2] -> and <-> are System Verilog The two operators -> and <-> are valid System Verilog, but not Verilog. --- src/verilog/scanner.l | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/verilog/scanner.l b/src/verilog/scanner.l index 1133bc2e3..38460da7a 100644 --- a/src/verilog/scanner.l +++ b/src/verilog/scanner.l @@ -188,7 +188,6 @@ void verilog_scanner_init() "^" { return TOK_CARET; } "~^" { return TOK_TILDECARET; } "^~" { return TOK_CARETTILDE; } -"->" { return TOK_MINUSGREATER; } /* Binary operators */ @@ -210,7 +209,6 @@ void verilog_scanner_init() ">>>" { return TOK_GREATERGREATERGREATER; } "<<" { return TOK_LESSLESS; } "<<<" { return TOK_LESSLESSLESS; } -"<->" { return TOK_LESSMINUSGREATER; } /* Trinary operators */ @@ -238,6 +236,8 @@ void verilog_scanner_init() "<<<=" { SYSTEM_VERILOG_OPERATOR(TOK_LESSLESSLESSEQUAL, "<<<="); } ">>>=" { SYSTEM_VERILOG_OPERATOR(TOK_GREATERGREATERGREATEREQUAL, ">>>="); } "##" { SYSTEM_VERILOG_OPERATOR(TOK_HASHHASH, "##"); } +"<->" { SYSTEM_VERILOG_OPERATOR(TOK_LESSMINUSGREATER, "<->"); } +"->" { SYSTEM_VERILOG_OPERATOR(TOK_MINUSGREATER, "->"); } /* Verilog keywords */