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Merge pull request #220 from diffblue/system-verilog-operators
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System Verilog operators
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@tautschnig
tautschnig authored Dec 2, 2023
2 parents 057a6cb + 46bf195 commit e429921
Showing 1 changed file with 27 additions and 97 deletions.
124 changes: 27 additions & 97 deletions src/verilog/scanner.l
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Original file line number Diff line number Diff line change
Expand Up @@ -68,6 +68,12 @@ static void preprocessor()
else \
IDENTIFIER; \
}
#define SYSTEM_VERILOG_OPERATOR(token, text) \
{ if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG) \
return token; \
else \
yyverilogerror(text " is a System Verilog operator"); \
}
#define VIS_VERILOG_KEYWORD(x) \
{ if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG || \
PARSER.mode==verilog_parsert::VIS_VERILOG) \
Expand Down Expand Up @@ -182,7 +188,6 @@ void verilog_scanner_init()
"^" { return TOK_CARET; }
"~^" { return TOK_TILDECARET; }
"^~" { return TOK_CARETTILDE; }
"->" { return TOK_MINUSGREATER; }

/* Binary operators */

Expand All @@ -204,7 +209,6 @@ void verilog_scanner_init()
">>>" { return TOK_GREATERGREATERGREATER; }
"<<" { return TOK_LESSLESS; }
"<<<" { return TOK_LESSLESSLESS; }
"<->" { return TOK_LESSMINUSGREATER; }

/* Trinary operators */

Expand All @@ -213,101 +217,27 @@ void verilog_scanner_init()

/* System Verilog operators */

"|->" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
return TOK_VERTBARMINUSGREATER;
else
yyverilogerror("|-> is a System Verilog operator");
}
"|=>" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
return TOK_VERTBAREQUALGREATER;
else
yyverilogerror("|=> is a System Verilog operator");
}
"++" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
return TOK_PLUSPLUS;
else
yyverilogerror("++ is a System Verilog operator");
}
"--" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
return TOK_MINUSMINUS;
else
yyverilogerror("-- is a System Verilog operator");
}
"+=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
return TOK_PLUSEQUAL;
else
yyverilogerror("+= is a System Verilog operator");
}
"+:" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
return TOK_PLUSCOLON;
else
yyverilogerror("+: is a System Verilog operator");
}
"-:" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
return TOK_MINUSCOLON;
else
yyverilogerror("-: is a System Verilog operator");
}
"-=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
return TOK_MINUSEQUAL;
else
yyverilogerror("-= is a System Verilog operator");
}
"*=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
return TOK_ASTERICEQUAL;
else
yyverilogerror("*= is a System Verilog operator");
}
"/=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
return TOK_SLASHEQUAL;
else
yyverilogerror("+= is a System Verilog operator");
}
"%=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
return TOK_PERCENTEQUAL;
else
yyverilogerror("%= is a System Verilog operator");
}
"&=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
return TOK_AMPEREQUAL;
else
yyverilogerror("&= is a System Verilog operator");
}
"^=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
return TOK_CARETEQUAL;
else
yyverilogerror("^= is a System Verilog operator");
}
"|=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
return TOK_VERTBAREQUAL;
else
yyverilogerror("|= is a System Verilog operator");
}
"<<=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
return TOK_LESSLESSEQUAL;
else
yyverilogerror("<<= is a System Verilog operator");
}
">>=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
return TOK_GREATERGREATEREQUAL;
else
yyverilogerror(">>= is a System Verilog operator");
}
"<<<=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
return TOK_LESSLESSLESSEQUAL;
else
yyverilogerror("<<<= is a System Verilog operator");
}
">>>=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
return TOK_GREATERGREATERGREATEREQUAL;
else
yyverilogerror(">>>= is a System Verilog operator");
}
"##" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
return TOK_HASHHASH;
else
yyverilogerror("## is a System Verilog operator");
}
"|->" { SYSTEM_VERILOG_OPERATOR(TOK_VERTBARMINUSGREATER, "|->"); }
"|=>" { SYSTEM_VERILOG_OPERATOR(TOK_VERTBAREQUALGREATER, "|=>"); }
"++" { SYSTEM_VERILOG_OPERATOR(TOK_PLUSPLUS, "++"); }
"--" { SYSTEM_VERILOG_OPERATOR(TOK_MINUSMINUS, "--"); }
"+=" { SYSTEM_VERILOG_OPERATOR(TOK_PLUSEQUAL, "+="); }
"+:" { SYSTEM_VERILOG_OPERATOR(TOK_PLUSCOLON, "+:"); }
"-:" { SYSTEM_VERILOG_OPERATOR(TOK_MINUSCOLON, "-:"); }
"-=" { SYSTEM_VERILOG_OPERATOR(TOK_MINUSEQUAL, "-="); }
"*=" { SYSTEM_VERILOG_OPERATOR(TOK_ASTERICEQUAL, "*="); }
"/=" { SYSTEM_VERILOG_OPERATOR(TOK_SLASHEQUAL, "+="); }
"%=" { SYSTEM_VERILOG_OPERATOR(TOK_PERCENTEQUAL, "%="); }
"&=" { SYSTEM_VERILOG_OPERATOR(TOK_AMPEREQUAL, "&="); }
"^=" { SYSTEM_VERILOG_OPERATOR(TOK_CARETEQUAL, "^="); }
"|=" { SYSTEM_VERILOG_OPERATOR(TOK_VERTBAREQUAL, "|="); }
"<<=" { SYSTEM_VERILOG_OPERATOR(TOK_LESSLESSEQUAL, "<<="); }
">>=" { SYSTEM_VERILOG_OPERATOR(TOK_GREATERGREATEREQUAL, ">>="); }
"<<<=" { SYSTEM_VERILOG_OPERATOR(TOK_LESSLESSLESSEQUAL, "<<<="); }
">>>=" { SYSTEM_VERILOG_OPERATOR(TOK_GREATERGREATERGREATEREQUAL, ">>>="); }
"##" { SYSTEM_VERILOG_OPERATOR(TOK_HASHHASH, "##"); }
"<->" { SYSTEM_VERILOG_OPERATOR(TOK_LESSMINUSGREATER, "<->"); }
"->" { SYSTEM_VERILOG_OPERATOR(TOK_MINUSGREATER, "->"); }

/* Verilog keywords */

Expand Down

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