Skip to content

Commit e429921

Browse files
tautschnigtautschnig
authored
Merge pull request #220 from diffblue/system-verilog-operators
System Verilog operators
2 parents 057a6cb + 46bf195 commit e429921

File tree

1 file changed

+27
-97
lines changed

1 file changed

+27
-97
lines changed

‎src/verilog/scanner.l

Lines changed: 27 additions & 97 deletions
Original file line numberDiff line numberDiff line change
@@ -68,6 +68,12 @@ static void preprocessor()
6868
else \
6969
IDENTIFIER; \
7070
}
71+
#define SYSTEM_VERILOG_OPERATOR(token, text) \
72+
{ if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG) \
73+
return token; \
74+
else \
75+
yyverilogerror(text " is a System Verilog operator"); \
76+
}
7177
#define VIS_VERILOG_KEYWORD(x) \
7278
{ if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG || \
7379
PARSER.mode==verilog_parsert::VIS_VERILOG) \
@@ -182,7 +188,6 @@ void verilog_scanner_init()
182188
"^" { return TOK_CARET; }
183189
"~^" { return TOK_TILDECARET; }
184190
"^~" { return TOK_CARETTILDE; }
185-
"->" { return TOK_MINUSGREATER; }
186191

187192
/* Binary operators */
188193

@@ -204,7 +209,6 @@ void verilog_scanner_init()
204209
">>>" { return TOK_GREATERGREATERGREATER; }
205210
"<<" { return TOK_LESSLESS; }
206211
"<<<" { return TOK_LESSLESSLESS; }
207-
"<->" { return TOK_LESSMINUSGREATER; }
208212

209213
/* Trinary operators */
210214

@@ -213,101 +217,27 @@ void verilog_scanner_init()
213217

214218
/* System Verilog operators */
215219

216-
"|->" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
217-
return TOK_VERTBARMINUSGREATER;
218-
else
219-
yyverilogerror("|-> is a System Verilog operator");
220-
}
221-
"|=>" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
222-
return TOK_VERTBAREQUALGREATER;
223-
else
224-
yyverilogerror("|=> is a System Verilog operator");
225-
}
226-
"++" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
227-
return TOK_PLUSPLUS;
228-
else
229-
yyverilogerror("++ is a System Verilog operator");
230-
}
231-
"--" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
232-
return TOK_MINUSMINUS;
233-
else
234-
yyverilogerror("-- is a System Verilog operator");
235-
}
236-
"+=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
237-
return TOK_PLUSEQUAL;
238-
else
239-
yyverilogerror("+= is a System Verilog operator");
240-
}
241-
"+:" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
242-
return TOK_PLUSCOLON;
243-
else
244-
yyverilogerror("+: is a System Verilog operator");
245-
}
246-
"-:" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
247-
return TOK_MINUSCOLON;
248-
else
249-
yyverilogerror("-: is a System Verilog operator");
250-
}
251-
"-=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
252-
return TOK_MINUSEQUAL;
253-
else
254-
yyverilogerror("-= is a System Verilog operator");
255-
}
256-
"*=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
257-
return TOK_ASTERICEQUAL;
258-
else
259-
yyverilogerror("*= is a System Verilog operator");
260-
}
261-
"/=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
262-
return TOK_SLASHEQUAL;
263-
else
264-
yyverilogerror("+= is a System Verilog operator");
265-
}
266-
"%=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
267-
return TOK_PERCENTEQUAL;
268-
else
269-
yyverilogerror("%= is a System Verilog operator");
270-
}
271-
"&=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
272-
return TOK_AMPEREQUAL;
273-
else
274-
yyverilogerror("&= is a System Verilog operator");
275-
}
276-
"^=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
277-
return TOK_CARETEQUAL;
278-
else
279-
yyverilogerror("^= is a System Verilog operator");
280-
}
281-
"|=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
282-
return TOK_VERTBAREQUAL;
283-
else
284-
yyverilogerror("|= is a System Verilog operator");
285-
}
286-
"<<=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
287-
return TOK_LESSLESSEQUAL;
288-
else
289-
yyverilogerror("<<= is a System Verilog operator");
290-
}
291-
">>=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
292-
return TOK_GREATERGREATEREQUAL;
293-
else
294-
yyverilogerror(">>= is a System Verilog operator");
295-
}
296-
"<<<=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
297-
return TOK_LESSLESSLESSEQUAL;
298-
else
299-
yyverilogerror("<<<= is a System Verilog operator");
300-
}
301-
">>>=" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
302-
return TOK_GREATERGREATERGREATEREQUAL;
303-
else
304-
yyverilogerror(">>>= is a System Verilog operator");
305-
}
306-
"##" { if(PARSER.mode==verilog_parsert::SYSTEM_VERILOG)
307-
return TOK_HASHHASH;
308-
else
309-
yyverilogerror("## is a System Verilog operator");
310-
}
220+
"|->" { SYSTEM_VERILOG_OPERATOR(TOK_VERTBARMINUSGREATER, "|->"); }
221+
"|=>" { SYSTEM_VERILOG_OPERATOR(TOK_VERTBAREQUALGREATER, "|=>"); }
222+
"++" { SYSTEM_VERILOG_OPERATOR(TOK_PLUSPLUS, "++"); }
223+
"--" { SYSTEM_VERILOG_OPERATOR(TOK_MINUSMINUS, "--"); }
224+
"+=" { SYSTEM_VERILOG_OPERATOR(TOK_PLUSEQUAL, "+="); }
225+
"+:" { SYSTEM_VERILOG_OPERATOR(TOK_PLUSCOLON, "+:"); }
226+
"-:" { SYSTEM_VERILOG_OPERATOR(TOK_MINUSCOLON, "-:"); }
227+
"-=" { SYSTEM_VERILOG_OPERATOR(TOK_MINUSEQUAL, "-="); }
228+
"*=" { SYSTEM_VERILOG_OPERATOR(TOK_ASTERICEQUAL, "*="); }
229+
"/=" { SYSTEM_VERILOG_OPERATOR(TOK_SLASHEQUAL, "+="); }
230+
"%=" { SYSTEM_VERILOG_OPERATOR(TOK_PERCENTEQUAL, "%="); }
231+
"&=" { SYSTEM_VERILOG_OPERATOR(TOK_AMPEREQUAL, "&="); }
232+
"^=" { SYSTEM_VERILOG_OPERATOR(TOK_CARETEQUAL, "^="); }
233+
"|=" { SYSTEM_VERILOG_OPERATOR(TOK_VERTBAREQUAL, "|="); }
234+
"<<=" { SYSTEM_VERILOG_OPERATOR(TOK_LESSLESSEQUAL, "<<="); }
235+
">>=" { SYSTEM_VERILOG_OPERATOR(TOK_GREATERGREATEREQUAL, ">>="); }
236+
"<<<=" { SYSTEM_VERILOG_OPERATOR(TOK_LESSLESSLESSEQUAL, "<<<="); }
237+
">>>=" { SYSTEM_VERILOG_OPERATOR(TOK_GREATERGREATERGREATEREQUAL, ">>>="); }
238+
"##" { SYSTEM_VERILOG_OPERATOR(TOK_HASHHASH, "##"); }
239+
"<->" { SYSTEM_VERILOG_OPERATOR(TOK_LESSMINUSGREATER, "<->"); }
240+
"->" { SYSTEM_VERILOG_OPERATOR(TOK_MINUSGREATER, "->"); }
311241

312242
/* Verilog keywords */
313243

0 commit comments

Comments
 (0)