@@ -68,6 +68,12 @@ static void preprocessor()
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else \
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IDENTIFIER; \
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}
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+ #define SYSTEM_VERILOG_OPERATOR (token, text ) \
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+ { if (PARSER.mode ==verilog_parsert::SYSTEM_VERILOG) \
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+ return token; \
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+ else \
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+ yyverilogerror (text " is a System Verilog operator" ); \
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+ }
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#define VIS_VERILOG_KEYWORD (x ) \
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{ if (PARSER.mode ==verilog_parsert::SYSTEM_VERILOG || \
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PARSER.mode ==verilog_parsert::VIS_VERILOG) \
@@ -182,7 +188,6 @@ void verilog_scanner_init()
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" ^" { return TOK_CARET; }
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" ~^" { return TOK_TILDECARET; }
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" ^~" { return TOK_CARETTILDE; }
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- " ->" { return TOK_MINUSGREATER; }
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/* Binary operators */
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@@ -204,7 +209,6 @@ void verilog_scanner_init()
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" >>>" { return TOK_GREATERGREATERGREATER; }
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" <<" { return TOK_LESSLESS; }
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" <<<" { return TOK_LESSLESSLESS; }
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- " <->" { return TOK_LESSMINUSGREATER; }
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/* Trinary operators */
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@@ -213,101 +217,27 @@ void verilog_scanner_init()
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/* System Verilog operators */
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- " |->" { if (PARSER.mode ==verilog_parsert::SYSTEM_VERILOG)
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- return TOK_VERTBARMINUSGREATER;
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- else
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- yyverilogerror (" |-> is a System Verilog operator" );
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- }
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- " |=>" { if (PARSER.mode ==verilog_parsert::SYSTEM_VERILOG)
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- return TOK_VERTBAREQUALGREATER;
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- else
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- yyverilogerror (" |=> is a System Verilog operator" );
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- }
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- " ++" { if (PARSER.mode ==verilog_parsert::SYSTEM_VERILOG)
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- return TOK_PLUSPLUS;
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- else
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- yyverilogerror (" ++ is a System Verilog operator" );
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- }
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- " --" { if (PARSER.mode ==verilog_parsert::SYSTEM_VERILOG)
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- return TOK_MINUSMINUS;
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- else
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- yyverilogerror (" -- is a System Verilog operator" );
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- }
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- " +=" { if (PARSER.mode ==verilog_parsert::SYSTEM_VERILOG)
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- return TOK_PLUSEQUAL;
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- else
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- yyverilogerror (" += is a System Verilog operator" );
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- }
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- " +:" { if (PARSER.mode ==verilog_parsert::SYSTEM_VERILOG)
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- return TOK_PLUSCOLON;
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- else
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- yyverilogerror (" +: is a System Verilog operator" );
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- }
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- " -:" { if (PARSER.mode ==verilog_parsert::SYSTEM_VERILOG)
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- return TOK_MINUSCOLON;
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- else
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- yyverilogerror (" -: is a System Verilog operator" );
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- }
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- " -=" { if (PARSER.mode ==verilog_parsert::SYSTEM_VERILOG)
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- return TOK_MINUSEQUAL;
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- else
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- yyverilogerror (" -= is a System Verilog operator" );
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- }
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- " *=" { if (PARSER.mode ==verilog_parsert::SYSTEM_VERILOG)
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- return TOK_ASTERICEQUAL;
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- else
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- yyverilogerror (" *= is a System Verilog operator" );
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- }
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- " /=" { if (PARSER.mode ==verilog_parsert::SYSTEM_VERILOG)
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- return TOK_SLASHEQUAL;
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- else
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- yyverilogerror (" += is a System Verilog operator" );
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- }
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- " %=" { if (PARSER.mode ==verilog_parsert::SYSTEM_VERILOG)
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- return TOK_PERCENTEQUAL;
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- else
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- yyverilogerror (" %= is a System Verilog operator" );
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- }
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- " &=" { if (PARSER.mode ==verilog_parsert::SYSTEM_VERILOG)
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- return TOK_AMPEREQUAL;
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- else
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- yyverilogerror (" &= is a System Verilog operator" );
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- }
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- " ^=" { if (PARSER.mode ==verilog_parsert::SYSTEM_VERILOG)
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- return TOK_CARETEQUAL;
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- else
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- yyverilogerror (" ^= is a System Verilog operator" );
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- }
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- " |=" { if (PARSER.mode ==verilog_parsert::SYSTEM_VERILOG)
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- return TOK_VERTBAREQUAL;
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- else
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- yyverilogerror (" |= is a System Verilog operator" );
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- }
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- " <<=" { if (PARSER.mode ==verilog_parsert::SYSTEM_VERILOG)
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- return TOK_LESSLESSEQUAL;
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- else
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- yyverilogerror (" <<= is a System Verilog operator" );
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- }
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- " >>=" { if (PARSER.mode ==verilog_parsert::SYSTEM_VERILOG)
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- return TOK_GREATERGREATEREQUAL;
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- else
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- yyverilogerror (" >>= is a System Verilog operator" );
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- }
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- " <<<=" { if (PARSER.mode ==verilog_parsert::SYSTEM_VERILOG)
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- return TOK_LESSLESSLESSEQUAL;
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- else
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- yyverilogerror (" <<<= is a System Verilog operator" );
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- }
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- " >>>=" { if (PARSER.mode ==verilog_parsert::SYSTEM_VERILOG)
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- return TOK_GREATERGREATERGREATEREQUAL;
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- else
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- yyverilogerror (" >>>= is a System Verilog operator" );
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- }
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- " ##" { if (PARSER.mode ==verilog_parsert::SYSTEM_VERILOG)
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- return TOK_HASHHASH;
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- else
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- yyverilogerror (" ## is a System Verilog operator" );
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- }
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+ " |->" { SYSTEM_VERILOG_OPERATOR (TOK_VERTBARMINUSGREATER, " |->" ); }
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+ " |=>" { SYSTEM_VERILOG_OPERATOR (TOK_VERTBAREQUALGREATER, " |=>" ); }
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+ " ++" { SYSTEM_VERILOG_OPERATOR (TOK_PLUSPLUS, " ++" ); }
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+ " --" { SYSTEM_VERILOG_OPERATOR (TOK_MINUSMINUS, " --" ); }
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+ " +=" { SYSTEM_VERILOG_OPERATOR (TOK_PLUSEQUAL, " +=" ); }
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+ " +:" { SYSTEM_VERILOG_OPERATOR (TOK_PLUSCOLON, " +:" ); }
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+ " -:" { SYSTEM_VERILOG_OPERATOR (TOK_MINUSCOLON, " -:" ); }
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+ " -=" { SYSTEM_VERILOG_OPERATOR (TOK_MINUSEQUAL, " -=" ); }
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+ " *=" { SYSTEM_VERILOG_OPERATOR (TOK_ASTERICEQUAL, " *=" ); }
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+ " /=" { SYSTEM_VERILOG_OPERATOR (TOK_SLASHEQUAL, " +=" ); }
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+ " %=" { SYSTEM_VERILOG_OPERATOR (TOK_PERCENTEQUAL, " %=" ); }
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+ " &=" { SYSTEM_VERILOG_OPERATOR (TOK_AMPEREQUAL, " &=" ); }
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+ " ^=" { SYSTEM_VERILOG_OPERATOR (TOK_CARETEQUAL, " ^=" ); }
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+ " |=" { SYSTEM_VERILOG_OPERATOR (TOK_VERTBAREQUAL, " |=" ); }
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+ " <<=" { SYSTEM_VERILOG_OPERATOR (TOK_LESSLESSEQUAL, " <<=" ); }
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+ " >>=" { SYSTEM_VERILOG_OPERATOR (TOK_GREATERGREATEREQUAL, " >>=" ); }
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+ " <<<=" { SYSTEM_VERILOG_OPERATOR (TOK_LESSLESSLESSEQUAL, " <<<=" ); }
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+ " >>>=" { SYSTEM_VERILOG_OPERATOR (TOK_GREATERGREATERGREATEREQUAL, " >>>=" ); }
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+ " ##" { SYSTEM_VERILOG_OPERATOR (TOK_HASHHASH, " ##" ); }
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+ " <->" { SYSTEM_VERILOG_OPERATOR (TOK_LESSMINUSGREATER, " <->" ); }
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+ " ->" { SYSTEM_VERILOG_OPERATOR (TOK_MINUSGREATER, " ->" ); }
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/* Verilog keywords */
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