diff --git a/regression/verilog/functioncall/named_block1.desc b/regression/verilog/functioncall/named_block1.desc
new file mode 100644
index 00000000..883cc6df
--- /dev/null
+++ b/regression/verilog/functioncall/named_block1.desc
@@ -0,0 +1,8 @@
+KNOWNBUG
+named_block1.sv
+
+^\[.*\] always main\.foo\(\) == 123: PROVED$
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
diff --git a/regression/verilog/functioncall/named_block1.sv b/regression/verilog/functioncall/named_block1.sv
new file mode 100644
index 00000000..c7eba52c
--- /dev/null
+++ b/regression/verilog/functioncall/named_block1.sv
@@ -0,0 +1,13 @@
+module main;
+
+  function [31:0] foo;
+  begin : block_name
+    reg [31:0] x;
+    x = 123;
+    foo = x;
+  end
+  endfunction;
+
+  assert final (foo() == 123);
+
+endmodule