From 908ddc76aca1506432432f79fc43f25fbfd8587a Mon Sep 17 00:00:00 2001
From: Daniel Kroening <dkr@amazon.com>
Date: Sat, 8 Feb 2025 10:08:14 +0000
Subject: [PATCH] SVA: KNOWNBUG test for default disable iff

The parser rules are incomplete, this causes a crash.

Replicates #974.
---
 regression/verilog/SVA/default_disable1.desc | 8 ++++++++
 regression/verilog/SVA/default_disable1.sv   | 7 +++++++
 2 files changed, 15 insertions(+)
 create mode 100644 regression/verilog/SVA/default_disable1.desc
 create mode 100644 regression/verilog/SVA/default_disable1.sv

diff --git a/regression/verilog/SVA/default_disable1.desc b/regression/verilog/SVA/default_disable1.desc
new file mode 100644
index 00000000..76d1f386
--- /dev/null
+++ b/regression/verilog/SVA/default_disable1.desc
@@ -0,0 +1,8 @@
+KNOWNBUG
+default_disable1.sv
+
+^EXIT=10$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
diff --git a/regression/verilog/SVA/default_disable1.sv b/regression/verilog/SVA/default_disable1.sv
new file mode 100644
index 00000000..74ebd178
--- /dev/null
+++ b/regression/verilog/SVA/default_disable1.sv
@@ -0,0 +1,7 @@
+module main(input clock, reset);
+
+  default clocking cb @(posedge clk);
+  endclocking
+  default disable iff (!reset);
+
+endmodule