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Merge pull request #464 from diffblue/type_parameters1
SystemVerilog: type parameters
2 parents 68409ac + b741269 commit bf6629f

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-12
lines changed

5 files changed

+77
-12
lines changed
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@@ -0,0 +1,9 @@
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CORE
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type_parameters1.sv
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--bound 0
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^\[main\.property\.p1\] always 1 == 1: PROVED up to bound 0$
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^\[main\.property\.p2\] always 32 == 32: PROVED up to bound 0$
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^EXIT=0$
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^SIGNAL=0$
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--
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^warning: ignoring
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module main;
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parameter type T1 = bit;
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localparam type T2 = bit [31:0];
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p1: assert property ($bits(T1) == 1);
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p2: assert property ($bits(T2) == 32);
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endmodule

src/verilog/parser.y

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1040,13 +1040,21 @@ local_parameter_declaration:
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{ init($$, ID_local_parameter_decl);
10411041
stack_expr($$).type() = std::move(stack_type($2));
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swapop($$, $3); }
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| TOK_LOCALPARAM TOK_TYPE list_of_type_assignments
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{ init($$, ID_local_parameter_decl);
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stack_expr($$).type() = typet(ID_type);
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swapop($$, $3); }
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;
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parameter_declaration:
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TOK_PARAMETER data_type_or_implicit list_of_param_assignments
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{ init($$, ID_parameter_decl);
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stack_expr($$).type() = std::move(stack_type($2));
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swapop($$, $3); }
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| TOK_PARAMETER TOK_TYPE list_of_type_assignments
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{ init($$, ID_parameter_decl);
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stack_expr($$).type() = typet(ID_type);
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swapop($$, $3); }
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;
10511059

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specparam_declaration:
@@ -1585,6 +1593,21 @@ param_assignment: param_identifier '=' constant_param_expression
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addswap($$, ID_value, $3); }
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;
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list_of_type_assignments:
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type_assignment
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{ init($$); mto($$, $1); }
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| list_of_type_assignments ',' type_assignment
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{ $$=$1; mto($$, $3); }
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;
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type_assignment: param_identifier '=' data_type
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{ init($$, ID_parameter);
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auto base_name = stack_expr($1).id();
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stack_expr($$).set(ID_identifier, base_name);
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stack_expr($$).set(ID_base_name, base_name);
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addswap($$, ID_type, $3); }
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;
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data_type_or_implicit:
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data_type
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| implicit_data_type

src/verilog/verilog_elaborate.cpp

Lines changed: 32 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -75,22 +75,42 @@ void verilog_typecheckt::collect_symbols(
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auto full_identifier = hierarchical_identifier(base_name);
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78-
// If there's no type, parameters take the type of the
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// value. We signal this using the special type "derive_from_value".
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// Is this a type or a value parameter?
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if(type.id() == ID_type)
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{
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// much like a typedef
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auto symbol_type = to_be_elaborated_typet{declarator.type()};
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81-
auto symbol_type =
82-
to_be_elaborated_typet(type.is_nil() ? derive_from_value_typet() : type);
84+
type_symbolt symbol{full_identifier, symbol_type, mode};
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84-
symbolt symbol{full_identifier, symbol_type, mode};
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symbol.module = module_identifier;
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symbol.base_name = base_name;
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symbol.pretty_name = strip_verilog_prefix(symbol.name);
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symbol.is_macro = true;
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symbol.value = nil_exprt{};
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symbol.location = declarator.source_location();
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93+
add_symbol(std::move(symbol));
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}
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else // It's a value parameter.
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{
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// If there's no type, parameters take the type of the
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// value. We signal this using the special type "derive_from_value".
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86-
symbol.module = module_identifier;
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symbol.base_name = base_name;
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symbol.pretty_name = strip_verilog_prefix(symbol.name);
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symbol.is_macro = true;
90-
symbol.value = declarator.value();
91-
symbol.location = declarator.source_location();
100+
auto symbol_type =
101+
to_be_elaborated_typet(type.is_nil() ? derive_from_value_typet() : type);
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93-
add_symbol(std::move(symbol));
103+
symbolt symbol{full_identifier, symbol_type, mode};
104+
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symbol.module = module_identifier;
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symbol.base_name = base_name;
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symbol.pretty_name = strip_verilog_prefix(symbol.name);
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symbol.is_macro = true;
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symbol.value = declarator.value();
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symbol.location = declarator.source_location();
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112+
add_symbol(std::move(symbol));
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}
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}
95115

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void verilog_typecheckt::collect_symbols(const typet &type)

src/verilog/verilog_typecheck_type.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -292,6 +292,10 @@ typet verilog_typecheck_exprt::convert_type(const typet &src)
292292
return struct_union_typet{src.id(), std::move(components)}
293293
.with_source_location(src.source_location());
294294
}
295+
else if(src.id() == ID_type)
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{
297+
return src;
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}
295299
else
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{
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throw errort().with_location(source_location)

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