From af32756730c5c7804687396c75042a677841b400 Mon Sep 17 00:00:00 2001
From: Daniel Kroening <dkr@amazon.com>
Date: Thu, 16 Jan 2025 10:13:51 -0800
Subject: [PATCH] SystemVerilog: allow SVA in property ... endproperty

This changes the type checker to allow SVA in property ... endproperty.
---
 regression/verilog/property/named_property2.desc | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/regression/verilog/property/named_property2.desc b/regression/verilog/property/named_property2.desc
index a24ff735..23e5c031 100644
--- a/regression/verilog/property/named_property2.desc
+++ b/regression/verilog/property/named_property2.desc
@@ -1,4 +1,4 @@
-KNOWNBUG
+CORE
 named_property2.sv
 --bound 20
 ^\[main\.assert\.1\] always main\.x_is_eventually_ten: PROVED up to bound 20$
@@ -7,5 +7,3 @@ named_property2.sv
 --
 ^warning: ignoring
 --
-The type checker only allows expressions, not properties in property ...
-endproperty.