diff --git a/regression/verilog/covergroup/covergroup1.desc b/regression/verilog/covergroup/covergroup1.desc
new file mode 100644
index 000000000..3eff5392a
--- /dev/null
+++ b/regression/verilog/covergroup/covergroup1.desc
@@ -0,0 +1,7 @@
+CORE
+covergroup1.sv
+
+^no properties$
+^EXIT=10$
+^SIGNAL=0$
+--
diff --git a/regression/verilog/covergroup/covergroup1.sv b/regression/verilog/covergroup/covergroup1.sv
new file mode 100644
index 000000000..7821d097f
--- /dev/null
+++ b/regression/verilog/covergroup/covergroup1.sv
@@ -0,0 +1,9 @@
+module main;
+
+  wire clk, some_signal;
+
+  covergroup cg @(posedge clk);
+    coverpoint some_signal;
+  endgroup
+
+endmodule
diff --git a/src/hw_cbmc_irep_ids.h b/src/hw_cbmc_irep_ids.h
index f7a3ff5a6..4dcc66ac4 100644
--- a/src/hw_cbmc_irep_ids.h
+++ b/src/hw_cbmc_irep_ids.h
@@ -75,6 +75,7 @@ IREP_ID_ONE(verilog_smv_using)
 IREP_ID_ONE(verilog_assert_property)
 IREP_ID_ONE(verilog_assume_property)
 IREP_ID_ONE(verilog_cover_property)
+IREP_ID_ONE(verilog_covergroup)
 IREP_ID_ONE(verilog_smv_assert)
 IREP_ID_ONE(verilog_smv_assume)
 IREP_ID_ONE(verilog_always)
diff --git a/src/verilog/parser.y b/src/verilog/parser.y
index cced4ddb1..7a80dd2b9 100644
--- a/src/verilog/parser.y
+++ b/src/verilog/parser.y
@@ -888,7 +888,7 @@ class_item:
 //	| attribute_instance_brace class_method
 //	| attribute_instance_brace class_constraint
 	  attribute_instance_brace class_declaration
-//	| attribute_instance_brace covergroup_declaration
+	| attribute_instance_brace covergroup_declaration
 	| local_parameter_declaration ';'
 	| parameter_declaration ';'
 	| ';'
@@ -1024,6 +1024,7 @@ package_or_generate_item_declaration:
 	     that let constructs may be declared in a
 	     module/interface/program/checker etc. */
 	| let_declaration
+	| covergroup_declaration
 	| ';'
 		{ init($$, ID_verilog_empty_item); }
         ;
@@ -1255,6 +1256,9 @@ enum_name_declaration_list:
           	{ $$=$1; mts($$, $3); }
 	;
 
+class_scope: class_type TOK_COLONCOLON
+	;
+
 integer_type:
 	  integer_vector_type
 	| integer_atom_type
@@ -1834,6 +1838,13 @@ task_declaration:
 task_prototype: TOK_TASK task_identifier
 	;
 
+tf_port_list_paren_opt:
+	  /* Optional */
+		{ init($$); }
+	| '(' tf_port_list_opt ')'
+		{ $$ = $2; }
+	;
+
 tf_port_list_opt:
 	/* Optional */
 		{ init($$); }
@@ -2037,6 +2048,55 @@ expression_or_dist:
 	  expression
 	;
 
+// System Verilog standard 1800-2017
+// A.2.11 Covergroup declarations
+
+covergroup_declaration:
+	  TOK_COVERGROUP new_identifier tf_port_list_paren_opt coverage_event_opt ';'
+	  coverage_spec_or_option_brace TOK_ENDGROUP
+		{ init($$, ID_verilog_covergroup); }
+	;
+
+coverage_spec_or_option_brace:
+	  /* Optional */
+	| coverage_spec_or_option_brace coverage_spec_or_option
+	;
+
+coverage_spec_or_option:
+	  attribute_instance_brace coverage_spec
+	;
+
+coverage_spec:
+	  cover_point
+	;
+
+coverage_event_opt:
+	  /* Optional */
+	| coverage_event
+	;
+
+coverage_event:
+	  clocking_event
+	;
+
+block_event_expression:
+	  block_event_expression TOK_OR block_event_expression
+	| TOK_BEGIN hierarchical_btf_identifier
+	| TOK_END hierarchical_btf_identifier
+	;
+
+hierarchical_btf_identifier:
+	  hierarchical_tf_identifier
+	| hierarchical_block_identifier
+	| method_identifier
+	| hierarchical_identifier '.' method_identifier
+	| class_scope method_identifier
+	;
+
+cover_point:
+	  TOK_COVERPOINT expression ';'
+	;
+
 // System Verilog standard 1800-2017
 // A.2.12 Let declarations
 
@@ -2880,6 +2940,11 @@ procedural_timing_control:
 // System Verilog standard 1800-2017
 // A.6.11 Clocking block
 
+clocking_event:
+	  '@' identifier
+	| '@' '(' event_expression ')'
+	;
+
 cycle_delay:
           "##" number
                 { init($$, ID_verilog_cycle_delay); mto($$, $2); }
@@ -3364,6 +3429,8 @@ ps_covergroup_identifier:
 	
 memory_identifier: identifier;
 
+method_identifier: identifier;
+
 type_identifier: TOK_TYPE_IDENTIFIER
 		{
 		  init($$, ID_typedef_type);
@@ -3397,6 +3464,8 @@ function_identifier: hierarchical_identifier
 
 hierarchical_event_identifier: event_identifier;
 
+hierarchical_block_identifier: hierarchical_identifier;
+
 hierarchical_identifier:
           identifier
         | hierarchical_identifier '.' identifier
diff --git a/src/verilog/verilog_elaborate.cpp b/src/verilog/verilog_elaborate.cpp
index 070f9f342..f68b4e4b0 100644
--- a/src/verilog/verilog_elaborate.cpp
+++ b/src/verilog/verilog_elaborate.cpp
@@ -769,6 +769,9 @@ void verilog_typecheckt::collect_symbols(
   else if(module_item.id() == ID_verilog_smv_assume)
   {
   }
+  else if(module_item.id() == ID_verilog_covergroup)
+  {
+  }
   else
     DATA_INVARIANT(false, "unexpected module item: " + module_item.id_string());
 }
diff --git a/src/verilog/verilog_interfaces.cpp b/src/verilog/verilog_interfaces.cpp
index b4e2f3fe5..72610d4af 100644
--- a/src/verilog/verilog_interfaces.cpp
+++ b/src/verilog/verilog_interfaces.cpp
@@ -293,6 +293,9 @@ void verilog_typecheckt::interface_module_item(
   else if(module_item.id() == ID_verilog_smv_assume)
   {
   }
+  else if(module_item.id() == ID_verilog_covergroup)
+  {
+  }
   else
   {
     DATA_INVARIANT(false, "unexpected module item: " + module_item.id_string());
diff --git a/src/verilog/verilog_synthesis.cpp b/src/verilog/verilog_synthesis.cpp
index 0b2b9fe2c..d5488d3a9 100644
--- a/src/verilog/verilog_synthesis.cpp
+++ b/src/verilog/verilog_synthesis.cpp
@@ -2740,6 +2740,9 @@ void verilog_synthesist::synth_module_item(
   else if(module_item.id() == ID_verilog_empty_item)
   {
   }
+  else if(module_item.id() == ID_verilog_covergroup)
+  {
+  }
   else
   {
     throw errort().with_location(module_item.source_location())
diff --git a/src/verilog/verilog_typecheck.cpp b/src/verilog/verilog_typecheck.cpp
index 6d6702f68..14e257e73 100644
--- a/src/verilog/verilog_typecheck.cpp
+++ b/src/verilog/verilog_typecheck.cpp
@@ -1584,6 +1584,9 @@ void verilog_typecheckt::convert_module_item(
   else if(module_item.id() == ID_verilog_smv_assume)
   {
   }
+  else if(module_item.id() == ID_verilog_covergroup)
+  {
+  }
   else
   {
     throw errort().with_location(module_item.source_location())