Verilog: fix assignment context semantics

Author: kroening

regression/verilog/assignments/assignment-context1.desc

@@ -1,9 +1,8 @@
-KNOWNBUG
+CORE
 assignment-context1.sv
 
 ^EXIT=0$
 ^SIGNAL=0$
 --
 ^warning: ignoring
 --
-The variants that enlarge give a wrong answer.

src/verilog/verilog_typecheck.cpp

@@ -42,15 +42,12 @@ void verilog_typecheckt::assignment_conversion(
   const typet &lhs_type)
 {
   // Implements 1800-2017 10.7
-  // If the RHS is smaller than the LHS:
-  // * if the RHS is unsigned, it is zero-padded
-  // * if the RHS is signed, it is sign-extended
-  // If the RHS is larger than the LHS, it is truncated.
-
-  // This matches our typecast, but differs from the steps taken
-  // when evaluating binary expressions (11.8.2), where sign
-  // extension only happens when the propagated type is signed.
-  implicit_typecast(rhs, lhs_type);
+  // "The size of the left-hand side of an assignment forms
+  // the context for the right-hand expression."
+
+  // This is _size_ only, the type of the RHS is retained.
+
+  downwards_type_propagation(rhs, lhs_type);
 }
 
 /*******************************************************************\