diff --git a/regression/verilog/SVA/default_disable1.desc b/regression/verilog/SVA/default_disable1.desc
new file mode 100644
index 00000000..76d1f386
--- /dev/null
+++ b/regression/verilog/SVA/default_disable1.desc
@@ -0,0 +1,8 @@
+KNOWNBUG
+default_disable1.sv
+
+^EXIT=10$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
diff --git a/regression/verilog/SVA/default_disable1.sv b/regression/verilog/SVA/default_disable1.sv
new file mode 100644
index 00000000..74ebd178
--- /dev/null
+++ b/regression/verilog/SVA/default_disable1.sv
@@ -0,0 +1,7 @@
+module main(input clock, reset);
+
+  default clocking cb @(posedge clk);
+  endclocking
+  default disable iff (!reset);
+
+endmodule