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Merge pull request #937 from diffblue/posedge_real
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Verilog: error on real operand for edge control
tautschnig authored Jan 17, 2025
2 parents ce3098d + aa53cdd commit 892735f
Showing 3 changed files with 27 additions and 0 deletions.
9 changes: 9 additions & 0 deletions regression/verilog/synthesis/posedge_real.desc
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@@ -0,0 +1,9 @@
CORE
posedge_real.v
--module main
^file posedge_real.v line \d+: edge event controls do not take real operands$
^EXIT=2$
^SIGNAL=0$
--
^warning: ignoring
--
7 changes: 7 additions & 0 deletions regression/verilog/synthesis/posedge_real.v
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@@ -0,0 +1,7 @@
module main;

real data;

always @(posedge data);

endmodule
11 changes: 11 additions & 0 deletions src/verilog/verilog_typecheck_expr.cpp
Original file line number Diff line number Diff line change
@@ -2568,6 +2568,17 @@ exprt verilog_typecheck_exprt::convert_unary_expr(unary_exprt expr)
else if(expr.id() == ID_posedge || expr.id() == ID_negedge)
{
convert_expr(expr.op());

// 1800-2017 6.12.1
// Edge event controls must not be given real operands.
if(
expr.op().type().id() == ID_verilog_shortreal ||
expr.op().type().id() == ID_verilog_real)
{
throw errort().with_location(expr.source_location())
<< "edge event controls do not take real operands";
}

expr.type() = bool_typet{};
}
else if(expr.id() == ID_verilog_smv_eventually)

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