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Merge pull request #446 from diffblue/unique_case1
Verilog: grammar for `unique case` and `unique if`
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6 files changed

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CORE
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unique_case1.sv
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^no properties$
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^EXIT=10$
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^SIGNAL=0$
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--
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^warning: ignoring
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module main(input x);
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always_comb // unique
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unique casex (x)
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0:;
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1:;
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endcase
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always_comb // not unique
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unique casex (x)
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0:;
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'b1?:;
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endcase
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endmodule

regression/verilog/if/unique_if1.desc

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CORE
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unique_if1.sv
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^no properties$
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^EXIT=10$
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^SIGNAL=0$
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--
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^warning: ignoring

regression/verilog/if/unique_if1.sv

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module main(input x);
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always_comb // unique
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unique if (x == 0)
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;
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else if(x == 1)
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;
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always_comb // not unique
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unique if (x == 0)
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;
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else if(x&'b10 == 1)
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;
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endmodule

src/hw_cbmc_irep_ids.h

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@@ -37,6 +37,9 @@ IREP_ID_ONE(inst)
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IREP_ID_ONE(Verilog)
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IREP_ID_ONE(verilog_explicit_cast)
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IREP_ID_ONE(verilog_implicit_typecast)
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IREP_ID_ONE(verilog_unique)
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IREP_ID_ONE(verilog_unique0)
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IREP_ID_ONE(verilog_priority)
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IREP_ID_ONE(verilog_non_indexed_part_select)
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IREP_ID_ONE(verilog_indexed_part_select_plus)
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IREP_ID_ONE(verilog_indexed_part_select_minus)

src/verilog/parser.y

Lines changed: 24 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -2845,27 +2845,38 @@ disable_statement: TOK_DISABLE hierarchical_task_or_block_identifier ';'
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// A.6.6 Conditional statements
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conditional_statement:
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TOK_IF '(' expression ')' statement_or_null %prec LT_TOK_ELSE
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{ init($$, ID_if); mto($$, $3); mto($$, $5); }
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| TOK_IF '(' expression ')' statement_or_null TOK_ELSE statement_or_null
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{ init($$, ID_if); mto($$, $3); mto($$, $5); mto($$, $7); }
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unique_priority_opt TOK_IF '(' expression ')' statement_or_null %prec LT_TOK_ELSE
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{ init($$, ID_if); mto($$, $4); mto($$, $6); }
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| unique_priority_opt TOK_IF '(' expression ')' statement_or_null TOK_ELSE statement_or_null
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{ init($$, ID_if); mto($$, $4); mto($$, $6); mto($$, $8); }
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;
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unique_priority_opt:
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/* Optional */
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{ init($$); }
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| TOK_UNIQUE
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{ init($$, ID_verilog_unique); }
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| TOK_UNIQUE0
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{ init($$, ID_verilog_unique0); }
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| TOK_PRIORITY
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{ init($$, ID_verilog_priority); }
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;
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// System Verilog standard 1800-2017
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// A.6.7 Case statements
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case_statement:
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TOK_CASE '(' expression ')' case_item_brace TOK_ENDCASE
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{ init($$, ID_case); mto($$, $3);
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Forall_operands(it, stack_expr($5))
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unique_priority_opt TOK_CASE '(' expression ')' case_item_brace TOK_ENDCASE
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{ init($$, ID_case); mto($$, $4);
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Forall_operands(it, stack_expr($6))
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stack_expr($$).add_to_operands(std::move(*it)); }
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| TOK_CASEX '(' expression ')' case_item_brace TOK_ENDCASE
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{ init($$, ID_casex); mto($$, $3);
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Forall_operands(it, stack_expr($5))
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| unique_priority_opt TOK_CASEX '(' expression ')' case_item_brace TOK_ENDCASE
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{ init($$, ID_casex); mto($$, $4);
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Forall_operands(it, stack_expr($6))
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stack_expr($$).add_to_operands(std::move(*it)); }
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| TOK_CASEZ '(' expression ')' case_item_brace TOK_ENDCASE
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{ init($$, ID_casez); mto($$, $3);
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Forall_operands(it, stack_expr($5))
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| unique_priority_opt TOK_CASEZ '(' expression ')' case_item_brace TOK_ENDCASE
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{ init($$, ID_casez); mto($$, $4);
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Forall_operands(it, stack_expr($6))
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stack_expr($$).add_to_operands(std::move(*it)); }
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;
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