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Merge pull request #224 from diffblue/lasso-inputs
ebmc: force inputs to be equal when comparing states
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regression/verilog/system_verilog_assertion/eventually1.desc
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CORE | ||
eventually1.sv | ||
--module main --bound 1 --trace | ||
^EXIT=10$ | ||
^SIGNAL=0$ | ||
^Counterexample:$ | ||
-- | ||
^ main\.reset = 0$ | ||
^warning: ignoring | ||
-- | ||
The last state must be identical to the first state on the trace. | ||
In both states reset must be 1. |
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regression/verilog/system_verilog_assertion/eventually1.sv
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// count up from 0 to 10 | ||
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module main(input clk, input reset); | ||
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reg [3:0] counter; | ||
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initial counter = 0; | ||
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always @(posedge clk) | ||
if(reset) | ||
counter = 0; | ||
else if(counter != 10) | ||
counter = counter + 1; | ||
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// expected to fail, owing to reset | ||
p0: assert property (eventually counter == 10); | ||
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endmodule |
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