diff --git a/regression/verilog/modules/inout_and_variable.desc b/regression/verilog/modules/inout_and_variable.desc
new file mode 100644
index 000000000..6143de355
--- /dev/null
+++ b/regression/verilog/modules/inout_and_variable.desc
@@ -0,0 +1,9 @@
+KNOWNBUG
+inout_and_variable.v
+
+^file .* line 4: symbol `some_var' is declared both as input and as register$
+^EXIT=2$
+^SIGNAL=0$
+--
+--
+The use of a variable with an inout port should be rejected.
diff --git a/regression/verilog/modules/inout_and_variable.v b/regression/verilog/modules/inout_and_variable.v
new file mode 100644
index 000000000..e8f9a3a92
--- /dev/null
+++ b/regression/verilog/modules/inout_and_variable.v
@@ -0,0 +1,12 @@
+module sub(inout some_port);
+
+endmodule
+
+module main;
+  // 1800-2017 6.5
+  // "Variables cannot be connected to either side of an inout port"
+  reg my_var;
+
+  sub sub(my_var);
+
+endmodule