Merge pull request #209 from diffblue/verilog-integer-type

Verilog: use verilog_integer instead of integer

Author: tautschnig

regression/verilog/bit-extract/bit-extract4.desc

@@ -0,0 +1,7 @@
+CORE
+bit-extract4.sv
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring

regression/verilog/bit-extract/bit-extract4.sv

@@ -0,0 +1,7 @@
+module main;
+
+  wire integer x = 'hff;
+
+  p0: assert property (x[7] == 1);
+
+endmodule

src/verilog/parser.y

@@ -1336,7 +1336,7 @@ integer_atom_type:
 	| TOK_SHORTINT { init($$, ID_verilog_shortint); }
 	| TOK_INT { init($$, ID_verilog_int); }
 	| TOK_LONGINT { init($$, ID_verilog_longint); }
-	| TOK_INTEGER { init($$, ID_integer); }
+	| TOK_INTEGER { init($$, ID_verilog_integer); }
 	| TOK_TIME { init($$, ID_verilog_time); }
 	;
 
@@ -1830,7 +1830,7 @@ range_or_type_opt:
 range_or_type:
 	  packed_dimension
 	| TOK_INTEGER
-		{ init($$, ID_integer); }
+		{ init($$, ID_verilog_integer); }
 	| TOK_REAL
 		{ init($$, ID_verilog_real); }
 	| TOK_REALTIME

src/verilog/verilog_typecheck_type.cpp

@@ -35,10 +35,6 @@ typet verilog_typecheck_exprt::convert_type(const typet &src)
     // it's just a bit
     return bool_typet().with_source_location(source_location);
   }
-  else if(src.id() == ID_integer)
-  {
-    return integer_typet().with_source_location(source_location);
-  }
   else if(src.id() == ID_verilog_byte)
   {
     return signedbv_typet{8}.with_source_location(source_location);