From 46bf1957dbcc05ba19ef4c491ccfab6be59924ba Mon Sep 17 00:00:00 2001 From: Daniel Kroening Date: Sat, 2 Dec 2023 05:41:59 -0800 Subject: [PATCH] -> and <-> are System Verilog The two operators -> and <-> are valid System Verilog, but not Verilog. --- src/verilog/scanner.l | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/verilog/scanner.l b/src/verilog/scanner.l index 1133bc2e3..38460da7a 100644 --- a/src/verilog/scanner.l +++ b/src/verilog/scanner.l @@ -188,7 +188,6 @@ void verilog_scanner_init() "^" { return TOK_CARET; } "~^" { return TOK_TILDECARET; } "^~" { return TOK_CARETTILDE; } -"->" { return TOK_MINUSGREATER; } /* Binary operators */ @@ -210,7 +209,6 @@ void verilog_scanner_init() ">>>" { return TOK_GREATERGREATERGREATER; } "<<" { return TOK_LESSLESS; } "<<<" { return TOK_LESSLESSLESS; } -"<->" { return TOK_LESSMINUSGREATER; } /* Trinary operators */ @@ -238,6 +236,8 @@ void verilog_scanner_init() "<<<=" { SYSTEM_VERILOG_OPERATOR(TOK_LESSLESSLESSEQUAL, "<<<="); } ">>>=" { SYSTEM_VERILOG_OPERATOR(TOK_GREATERGREATERGREATEREQUAL, ">>>="); } "##" { SYSTEM_VERILOG_OPERATOR(TOK_HASHHASH, "##"); } +"<->" { SYSTEM_VERILOG_OPERATOR(TOK_LESSMINUSGREATER, "<->"); } +"->" { SYSTEM_VERILOG_OPERATOR(TOK_MINUSGREATER, "->"); } /* Verilog keywords */