Merge pull request #440 from diffblue/fixup-sva_ranged_always

fixup for #432
diffblue · Apr 15, 2024 · 3d28944 · 3d28944
2 parents 4b56ef0 + 200b4ec
commit 3d28944
Showing 1 changed file with 0 additions and 2 deletions.
diff --git a/src/verilog/verilog_typecheck_expr.cpp b/src/verilog/verilog_typecheck_expr.cpp
@@ -1592,7 +1592,6 @@ void verilog_typecheck_exprt::implicit_typecast(
       return;
     }
   }
-#if 0
   else if(src_type.id() == ID_natural)
   {
     if(dest_type.id()==ID_integer)
@@ -1601,7 +1600,6 @@ void verilog_typecheck_exprt::implicit_typecast(
       return;
     }
   }
-#endif
   else if(
     src_type.id() == ID_bool || src_type.id() == ID_unsignedbv ||
     src_type.id() == ID_signedbv || src_type.id() == ID_verilog_unsignedbv ||