diff --git a/src/verilog/verilog_language.cpp b/src/verilog/verilog_language.cpp
index 920a3fa01..32ad6198a 100644
--- a/src/verilog/verilog_language.cpp
+++ b/src/verilog/verilog_language.cpp
@@ -162,7 +162,7 @@ bool verilog_languaget::typecheck(
   if(verilog_typecheck(parse_tree, symbol_table, module, get_message_handler()))
     return true;
     
-  print(9, "Synthesis "+module);
+  debug() << "Synthesis " << module << eom;
 
   if(verilog_synthesis(symbol_table, module, get_message_handler(), options))
     return true;
diff --git a/src/vhdl/parser.y b/src/vhdl/parser.y
index b76873a40..1396907b3 100644
--- a/src/vhdl/parser.y
+++ b/src/vhdl/parser.y
@@ -53,7 +53,8 @@ int yyvhdlerror(const char *error_str)
   source_location.set_line(yyvhdllval.line);
   source_location.set_file(yyvhdllval.file);
 
-  PARSER.print(1, tmp, -1, source_location);
+  PARSER.error().source_location=source_location;
+  PARSER.error() << tmp << messaget::eom;
                   
   return strlen(error_str)+1;
 }