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kroeningkroening
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SystemVerilog: package scope operator
This adds the SystemVerilog package scope operator ::.
1 parent 129c081 commit 3a3a576

14 files changed

+119
-53
lines changed

‎CHANGELOG

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Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@
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* SystemVerilog: $bitstoreal/$bitstoshortreal, $realtobits/$shortrealtobits
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* SystemVerilog: $itor, $rtoi
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* SystemVerilog: chandle, event
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* SystemVerilog: package scope operator
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# EBMC 5.4
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‎regression/verilog/packages/package2.desc

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@@ -0,0 +1,7 @@
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CORE
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package2.sv
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^^\[.*\] always main\.Q == 123: PROVED$
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^EXIT=0$
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^SIGNAL=0$
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--

‎regression/verilog/packages/package2.sv

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@@ -0,0 +1,15 @@
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package moo;
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parameter P = 123;
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endpackage
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module main;
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import moo::*;
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parameter Q = moo::P;
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assert final (Q == 123);
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endmodule

‎src/hw_cbmc_irep_ids.h

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Original file line numberDiff line numberDiff line change
@@ -250,6 +250,7 @@ IREP_ID_ONE(verilog_class)
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IREP_ID_ONE(verilog_module)
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IREP_ID_ONE(verilog_package)
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IREP_ID_ONE(verilog_package_import)
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IREP_ID_ONE(verilog_package_scope)
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IREP_ID_ONE(verilog_program)
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IREP_ID_ONE(verilog_udp)
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IREP_ID_ONE(module_source)

‎src/verilog/parser.y

Lines changed: 13 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1355,9 +1355,13 @@ package_import_item_brace:
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13561356
package_import_item:
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package_identifier "::" identifier
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{ init($$, ID_verilog_import_item); mto($$, $1); mto($$, $3); }
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{ init($$, ID_verilog_import_item);
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stack_expr($$).set(ID_verilog_package, stack_expr($1).id());
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stack_expr($$).set(ID_identifier, stack_expr($3).id()); }
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| package_identifier "::" "*"
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{ init($$, ID_verilog_import_item); mto($$, $1); }
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{ init($$, ID_verilog_import_item);
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stack_expr($$).set(ID_verilog_package, stack_expr($1).id());
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stack_expr($$).set(ID_identifier, "*"); }
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;
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genvar_declaration:
@@ -4032,6 +4036,10 @@ part_select_range:
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primary: primary_literal
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| hierarchical_identifier_select
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| package_scope hierarchical_identifier_select
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{ init($$, ID_verilog_package_scope);
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mto($$, $1);
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mto($$, $2); }
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| concatenation
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| multiple_concatenation
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| function_subroutine_call
@@ -4209,6 +4217,9 @@ net_identifier: identifier;
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package_identifier: TOK_NON_TYPE_IDENTIFIER;
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4220+
package_scope: package_identifier "::"
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;
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42124223
param_identifier: TOK_NON_TYPE_IDENTIFIER;
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port_identifier: identifier;

‎src/verilog/verilog_expr.cpp

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Original file line numberDiff line numberDiff line change
@@ -100,6 +100,14 @@ static void dependencies_rec(
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{
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dependencies_rec(to_verilog_generate_for(module_item).body(), dest);
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}
103+
else if(module_item.id() == ID_verilog_package_import)
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{
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for(auto &import_item : module_item.get_sub())
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{
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dest.push_back(
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verilog_package_identifier(import_item.get(ID_verilog_package)));
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}
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}
103111
}
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std::vector<irep_idt> verilog_item_containert::dependencies() const

‎src/verilog/verilog_language.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -132,7 +132,7 @@ void verilog_languaget::dependencies(
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std::set<std::string> &dependency_set)
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{
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verilog_parse_treet::item_mapt::const_iterator it =
135-
parse_tree.item_map.find(id2string(verilog_module_name(module)));
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parse_tree.item_map.find(id2string(verilog_item_key(module)));
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if(it != parse_tree.item_map.end())
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{

‎src/verilog/verilog_parse_tree.cpp

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Original file line numberDiff line numberDiff line change
@@ -62,8 +62,15 @@ void verilog_parse_treet::modules_provided(
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for(auto &item : items)
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{
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if(item.id() == ID_verilog_module)
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{
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module_set.insert(id2string(
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verilog_module_symbol(to_verilog_module_source(item).base_name())));
68+
}
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else if(item.id() == ID_verilog_package)
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{
71+
module_set.insert(id2string(verilog_package_identifier(
72+
to_verilog_module_source(item).base_name())));
73+
}
6774
}
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}
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‎src/verilog/verilog_parse_tree.h

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Original file line numberDiff line numberDiff line change
@@ -75,7 +75,7 @@ class verilog_parse_treet
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// An index into the items list.
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// The key is
78-
// package::name for pagages
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// package::name for packages
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// name for modules, etc.
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// as packages have a separate name space (1800-2017 3.13).
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typedef std::

‎src/verilog/verilog_typecheck.cpp

Lines changed: 12 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -1947,55 +1947,27 @@ Function: verilog_typecheck
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bool verilog_typecheck(
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const verilog_parse_treet &parse_tree,
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symbol_table_baset &symbol_table,
1950-
const std::string &module,
1950+
const irep_idt &module_identifier,
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bool warn_implicit_nets,
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message_handlert &message_handler)
19531953
{
19541954
verilog_parse_treet::item_mapt::const_iterator it =
1955-
parse_tree.item_map.find(id2string(verilog_module_name(module)));
1955+
parse_tree.item_map.find(id2string(verilog_item_key(module_identifier)));
19561956

19571957
if(it == parse_tree.item_map.end())
19581958
{
19591959
messaget message(message_handler);
1960-
message.error() << "module `" << module
1961-
<< "' not found" << messaget::eom;
1960+
message.error() << "module `" << module_identifier << "' not found"
1961+
<< messaget::eom;
19621962
return true;
19631963
}
19641964

1965-
auto &module_source = to_verilog_module_source(*it->second);
1966-
1967-
return verilog_typecheck(
1968-
symbol_table,
1969-
module_source,
1970-
parse_tree.standard,
1971-
warn_implicit_nets,
1972-
message_handler);
1973-
}
1974-
1975-
/*******************************************************************\
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1977-
Function: verilog_typecheck
1978-
1979-
Inputs:
1980-
1981-
Outputs:
1982-
1983-
Purpose:
1984-
1985-
\*******************************************************************/
1986-
1987-
bool verilog_typecheck(
1988-
symbol_table_baset &symbol_table,
1989-
const verilog_module_sourcet &verilog_module_source,
1990-
verilog_standardt standard,
1991-
bool warn_implicit_nets,
1992-
message_handlert &message_handler)
1993-
{
1994-
// create symbol
1965+
auto &verilog_module_source = to_verilog_module_source(*it->second);
19951966

1967+
// create the symbol
19961968
irep_idt base_name = verilog_module_source.base_name();
19971969

1998-
symbolt symbol{verilog_module_symbol(base_name), module_typet{}, ID_Verilog};
1970+
symbolt symbol{module_identifier, module_typet{}, ID_Verilog};
19991971

20001972
symbol.base_name = base_name;
20011973
symbol.pretty_name = base_name;
@@ -2017,7 +1989,11 @@ bool verilog_typecheck(
20171989
}
20181990

20191991
verilog_typecheckt verilog_typecheck(
2020-
standard, warn_implicit_nets, *new_symbol, symbol_table, message_handler);
1992+
parse_tree.standard,
1993+
warn_implicit_nets,
1994+
*new_symbol,
1995+
symbol_table,
1996+
message_handler);
20211997

20221998
return verilog_typecheck.typecheck_main();
20231999
}

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