From 529fd28042c9b6dbf555cb4e8e63a35d6114fc17 Mon Sep 17 00:00:00 2001 From: Daniel Kroening Date: Tue, 4 Feb 2025 12:02:40 +0000 Subject: [PATCH] Increase the error verbosity of the Verilog parser Bison is instructed to generate verbose error messages for the Verilog parser. This results in more helpful syntax error messages at least in some cases. --- regression/smv/syntax-errors/syntax1.desc | 7 +++++++ regression/smv/syntax-errors/syntax1.smv | 4 ++++ regression/smv/syntax-errors/syntax2.desc | 7 +++++++ regression/smv/syntax-errors/syntax2.smv | 4 ++++ regression/smv/syntax-errors/syntax3.desc | 7 +++++++ regression/smv/syntax-errors/syntax3.smv | 4 ++++ regression/verilog/preprocessor/ifdef1.desc | 2 +- regression/verilog/preprocessor/ifdef2.desc | 2 +- regression/verilog/preprocessor/multi-line-define2.desc | 2 +- regression/verilog/preprocessor/multi-line-define3.desc | 2 +- regression/verilog/syntax-errors/syntax1.desc | 7 +++++++ regression/verilog/syntax-errors/syntax1.sv | 1 + regression/verilog/syntax-errors/syntax2.desc | 7 +++++++ regression/verilog/syntax-errors/syntax2.sv | 6 ++++++ regression/verilog/syntax-errors/syntax3.desc | 7 +++++++ regression/verilog/syntax-errors/syntax3.sv | 1 + src/smvlang/parser.y | 1 + src/verilog/parser.y | 3 +++ 18 files changed, 70 insertions(+), 4 deletions(-) create mode 100644 regression/smv/syntax-errors/syntax1.desc create mode 100644 regression/smv/syntax-errors/syntax1.smv create mode 100644 regression/smv/syntax-errors/syntax2.desc create mode 100644 regression/smv/syntax-errors/syntax2.smv create mode 100644 regression/smv/syntax-errors/syntax3.desc create mode 100644 regression/smv/syntax-errors/syntax3.smv create mode 100644 regression/verilog/syntax-errors/syntax1.desc create mode 100644 regression/verilog/syntax-errors/syntax1.sv create mode 100644 regression/verilog/syntax-errors/syntax2.desc create mode 100644 regression/verilog/syntax-errors/syntax2.sv create mode 100644 regression/verilog/syntax-errors/syntax3.desc create mode 100644 regression/verilog/syntax-errors/syntax3.sv diff --git a/regression/smv/syntax-errors/syntax1.desc b/regression/smv/syntax-errors/syntax1.desc new file mode 100644 index 000000000..bdb15bc0d --- /dev/null +++ b/regression/smv/syntax-errors/syntax1.desc @@ -0,0 +1,7 @@ +CORE +syntax1.smv + +^file .* line 3: syntax error, unexpected VAR, expecting string or "'" before 'VAR'$ +^EXIT=1$ +^SIGNAL=0$ +-- diff --git a/regression/smv/syntax-errors/syntax1.smv b/regression/smv/syntax-errors/syntax1.smv new file mode 100644 index 000000000..162030203 --- /dev/null +++ b/regression/smv/syntax-errors/syntax1.smv @@ -0,0 +1,4 @@ +MODULE -- forgot the name + +VAR abc : BOOLEAN; + diff --git a/regression/smv/syntax-errors/syntax2.desc b/regression/smv/syntax-errors/syntax2.desc new file mode 100644 index 000000000..a70f65a7f --- /dev/null +++ b/regression/smv/syntax-errors/syntax2.desc @@ -0,0 +1,7 @@ +CORE +syntax2.smv + +^file .* line 3: syntax error, unexpected VAR before 'VAR'$ +^EXIT=1$ +^SIGNAL=0$ +-- diff --git a/regression/smv/syntax-errors/syntax2.smv b/regression/smv/syntax-errors/syntax2.smv new file mode 100644 index 000000000..fb5b5343f --- /dev/null +++ b/regression/smv/syntax-errors/syntax2.smv @@ -0,0 +1,4 @@ +-- forgot the MODULE + +VAR abc : BOOLEAN; + diff --git a/regression/smv/syntax-errors/syntax3.desc b/regression/smv/syntax-errors/syntax3.desc new file mode 100644 index 000000000..9cde9f524 --- /dev/null +++ b/regression/smv/syntax-errors/syntax3.desc @@ -0,0 +1,7 @@ +CORE +syntax3.smv + +^file .* line 3: syntax error, unexpected string, expecting number before 'not_a_number'$ +^EXIT=1$ +^SIGNAL=0$ +-- diff --git a/regression/smv/syntax-errors/syntax3.smv b/regression/smv/syntax-errors/syntax3.smv new file mode 100644 index 000000000..514a1b1f9 --- /dev/null +++ b/regression/smv/syntax-errors/syntax3.smv @@ -0,0 +1,4 @@ +MODULE main + +VAR foobar : 1.. not_a_number; + diff --git a/regression/verilog/preprocessor/ifdef1.desc b/regression/verilog/preprocessor/ifdef1.desc index e3b240e7d..462e2a77a 100644 --- a/regression/verilog/preprocessor/ifdef1.desc +++ b/regression/verilog/preprocessor/ifdef1.desc @@ -1,7 +1,7 @@ CORE ifdef1.v -^file ifdef1\.v line 4: syntax error before 'syntax'$ +^file ifdef1\.v line 4: syntax error, unexpected .* before 'syntax'$ ^EXIT=1$ ^SIGNAL=0$ -- diff --git a/regression/verilog/preprocessor/ifdef2.desc b/regression/verilog/preprocessor/ifdef2.desc index a9dba86d4..dd3add7f0 100644 --- a/regression/verilog/preprocessor/ifdef2.desc +++ b/regression/verilog/preprocessor/ifdef2.desc @@ -1,7 +1,7 @@ CORE ifdef2.v -^file ifdef2\.v line 4: syntax error before 'syntax'$ +^file ifdef2\.v line 4: syntax error, unexpected .* before 'syntax'$ ^EXIT=1$ ^SIGNAL=0$ -- diff --git a/regression/verilog/preprocessor/multi-line-define2.desc b/regression/verilog/preprocessor/multi-line-define2.desc index b37c27bbf..bbf0de6cf 100644 --- a/regression/verilog/preprocessor/multi-line-define2.desc +++ b/regression/verilog/preprocessor/multi-line-define2.desc @@ -1,7 +1,7 @@ CORE multi-line-define2.v -^file multi-line-define2\.v line 4: syntax error before 'syntax'$ +^file multi-line-define2\.v line 4: syntax error, unexpected .* before 'syntax'$ ^EXIT=1$ ^SIGNAL=0$ -- diff --git a/regression/verilog/preprocessor/multi-line-define3.desc b/regression/verilog/preprocessor/multi-line-define3.desc index 1a62201f9..8745899f9 100644 --- a/regression/verilog/preprocessor/multi-line-define3.desc +++ b/regression/verilog/preprocessor/multi-line-define3.desc @@ -1,7 +1,7 @@ CORE multi-line-define3.v -^file multi-line-define3\.v line 4: syntax error before 'syntax'$ +^file multi-line-define3\.v line 4: syntax error, unexpected .* before 'syntax'$ ^EXIT=1$ ^SIGNAL=0$ -- diff --git a/regression/verilog/syntax-errors/syntax1.desc b/regression/verilog/syntax-errors/syntax1.desc new file mode 100644 index 000000000..e11d6efd9 --- /dev/null +++ b/regression/verilog/syntax-errors/syntax1.desc @@ -0,0 +1,7 @@ +CORE +syntax1.sv + +^file .* line 1: syntax error, unexpected ';', expecting TOK_NON_TYPE_IDENTIFIER before ';'$ +^EXIT=1$ +^SIGNAL=0$ +-- diff --git a/regression/verilog/syntax-errors/syntax1.sv b/regression/verilog/syntax-errors/syntax1.sv new file mode 100644 index 000000000..58f49c61c --- /dev/null +++ b/regression/verilog/syntax-errors/syntax1.sv @@ -0,0 +1 @@ +module ;// forgot the name diff --git a/regression/verilog/syntax-errors/syntax2.desc b/regression/verilog/syntax-errors/syntax2.desc new file mode 100644 index 000000000..62713a3b5 --- /dev/null +++ b/regression/verilog/syntax-errors/syntax2.desc @@ -0,0 +1,7 @@ +CORE +syntax2.sv + +^file syntax2.sv line 3: syntax error, unexpected byte, expecting ';' before 'byte'$ +^EXIT=1$ +^SIGNAL=0$ +-- diff --git a/regression/verilog/syntax-errors/syntax2.sv b/regression/verilog/syntax-errors/syntax2.sv new file mode 100644 index 000000000..3fdc4c52c --- /dev/null +++ b/regression/verilog/syntax-errors/syntax2.sv @@ -0,0 +1,6 @@ +module main // forgot the ; + +byte some_var; + +endmodule + diff --git a/regression/verilog/syntax-errors/syntax3.desc b/regression/verilog/syntax-errors/syntax3.desc new file mode 100644 index 000000000..ebe779e96 --- /dev/null +++ b/regression/verilog/syntax-errors/syntax3.desc @@ -0,0 +1,7 @@ +CORE +syntax3.sv + +^file syntax3.sv line 1: syntax error, unexpected ';' before ';'$ +^EXIT=1$ +^SIGNAL=0$ +-- diff --git a/regression/verilog/syntax-errors/syntax3.sv b/regression/verilog/syntax-errors/syntax3.sv new file mode 100644 index 000000000..78a885932 --- /dev/null +++ b/regression/verilog/syntax-errors/syntax3.sv @@ -0,0 +1 @@ +module main(; // forgot the ) diff --git a/src/smvlang/parser.y b/src/smvlang/parser.y index e7ee0861c..e4fb057a6 100644 --- a/src/smvlang/parser.y +++ b/src/smvlang/parser.y @@ -1,3 +1,4 @@ +/* increase verbosity of error messages, to include expected tokens */ %define parse.error verbose %{ diff --git a/src/verilog/parser.y b/src/verilog/parser.y index 658c31c6e..dd31f867a 100644 --- a/src/verilog/parser.y +++ b/src/verilog/parser.y @@ -1,3 +1,6 @@ +/* increase verbosity of error messages, to include expected tokens */ +%define parse.error verbose + %{ /*******************************************************************\