From 34da31d9095763cdf428696f9616551cae23fd1b Mon Sep 17 00:00:00 2001
From: Daniel Kroening <dkr@amazon.com>
Date: Fri, 17 Jan 2025 07:30:31 -0800
Subject: [PATCH] SVA: add test with non-constant SVA cycle delays

Replicates third example in #931.
---
 regression/verilog/SVA/cycle_delay1.desc | 10 ++++++++++
 regression/verilog/SVA/cycle_delay1.sv   | 11 +++++++++++
 2 files changed, 21 insertions(+)
 create mode 100644 regression/verilog/SVA/cycle_delay1.desc
 create mode 100644 regression/verilog/SVA/cycle_delay1.sv

diff --git a/regression/verilog/SVA/cycle_delay1.desc b/regression/verilog/SVA/cycle_delay1.desc
new file mode 100644
index 00000000..b71fab1c
--- /dev/null
+++ b/regression/verilog/SVA/cycle_delay1.desc
@@ -0,0 +1,10 @@
+CORE
+cycle_delay1.sv
+
+^C string exception : failed to convert sva_cycle_delay offsets$
+^EXIT=2$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+The error message could be better.
diff --git a/regression/verilog/SVA/cycle_delay1.sv b/regression/verilog/SVA/cycle_delay1.sv
new file mode 100644
index 00000000..5c14cb79
--- /dev/null
+++ b/regression/verilog/SVA/cycle_delay1.sv
@@ -0,0 +1,11 @@
+module main(input clk, input [31:0] from);
+
+  reg [31:0] x;
+
+  always_ff @(posedge clk)
+    x++;
+
+  // The cycle delay must be elaboration-time constant
+  initial assert property (##[from:2] x!=10);
+
+endmodule