SVA: add test with non-constant SVA cycle delays

Replicates third example in #931.

regression/verilog/SVA/cycle_delay1.desc

@@ -0,0 +1,10 @@
+CORE
+cycle_delay1.sv
+
+^C string exception : failed to convert sva_cycle_delay offsets$
+^EXIT=2$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+The error message could be better.

regression/verilog/SVA/cycle_delay1.sv

@@ -0,0 +1,11 @@
+module main(input clk, input [31:0] from);
+
+  reg [31:0] x;
+
+  always_ff @(posedge clk)
+    x++;
+
+  // The cycle delay must be elaboration-time constant
+  initial assert property (##[from:2] x!=10);
+
+endmodule