Skip to content

Commit 2e75751

Browse files
committed
Verilog: extract scope data structure from parser
This extracts the scope data structure from the parser class into a separate file, as the scopes need to be preserved until all Verilog parsing is finished.
1 parent 7dfd0f2 commit 2e75751

File tree

4 files changed

+65
-0
lines changed

4 files changed

+65
-0
lines changed

src/verilog/Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,7 @@ SRC = aval_bval_encoding.cpp \
1818
verilog_preprocessor.cpp \
1919
verilog_preprocessor_lex.yy.cpp \
2020
verilog_preprocessor_tokenizer.cpp \
21+
verilog_scope.cpp \
2122
verilog_simplifier.cpp \
2223
verilog_standard.cpp \
2324
verilog_symbol_table.cpp \

src/verilog/verilog_parser.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@ Author: Daniel Kroening, [email protected]
1313
#include <util/parser.h>
1414

1515
#include "verilog_parse_tree.h"
16+
#include "verilog_scope.h"
1617
#include "verilog_standard.h"
1718

1819
#include <map>

src/verilog/verilog_scope.cpp

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
/*******************************************************************\
2+
3+
Module: Verilog Scope
4+
5+
Author: Daniel Kroening, [email protected]
6+
7+
\*******************************************************************/
8+
9+
#include "verilog_scope.h"

src/verilog/verilog_scope.h

Lines changed: 54 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,54 @@
1+
/*******************************************************************\
2+
3+
Module: Verilog Scopes
4+
5+
Author: Daniel Kroening, [email protected]
6+
7+
\*******************************************************************/
8+
9+
#ifndef CPROVER_VERILOG_SCOPE_H
10+
#define CPROVER_VERILOG_SCOPE_H
11+
12+
#include <util/irep.h>
13+
14+
#include <map>
15+
16+
// parser scopes and identifiers
17+
struct scopet
18+
{
19+
scopet() : parent(nullptr), prefix("Verilog::")
20+
{
21+
}
22+
23+
explicit scopet(
24+
irep_idt _base_name,
25+
const std::string &separator,
26+
scopet *_parent)
27+
: parent(_parent),
28+
__base_name(_base_name),
29+
prefix(id2string(_parent->prefix) + id2string(_base_name) + separator)
30+
{
31+
}
32+
33+
scopet *parent = nullptr;
34+
bool is_type = false;
35+
irep_idt __base_name;
36+
std::string prefix;
37+
38+
irep_idt identifier() const
39+
{
40+
PRECONDITION(parent != nullptr);
41+
return parent->prefix + id2string(__base_name);
42+
}
43+
44+
const irep_idt &base_name() const
45+
{
46+
return __base_name;
47+
}
48+
49+
// sub-scopes
50+
using scope_mapt = std::map<irep_idt, scopet>;
51+
scope_mapt scope_map;
52+
};
53+
54+
#endif

0 commit comments

Comments
 (0)