diff --git a/src/verilog/verilog_expr.h b/src/verilog/verilog_expr.h index 6ae3170d2..95e1a4510 100644 --- a/src/verilog/verilog_expr.h +++ b/src/verilog/verilog_expr.h @@ -573,6 +573,39 @@ class verilog_inst_baset : public verilog_module_itemt return set(ID_module, module); } + class named_port_connectiont : public binary_exprt + { + public: + named_port_connectiont(exprt _port, exprt _value) + : binary_exprt( + std::move(_port), + ID_named_port_connection, + std::move(_value), + typet{}) + { + } + + const exprt &port() const + { + return op0(); + } + + exprt &port() + { + return op0(); + } + + const exprt &value() const + { + return op1(); + } + + exprt &value() + { + return op1(); + } + }; + class instancet : public exprt { public: @@ -621,6 +654,22 @@ class verilog_inst_baset : public verilog_module_itemt using exprt::operands; }; +inline const verilog_inst_baset::named_port_connectiont & +to_verilog_named_port_connection(const exprt &expr) +{ + PRECONDITION(expr.id() == ID_named_port_connection); + verilog_inst_baset::named_port_connectiont::check(expr); + return static_cast(expr); +} + +inline verilog_inst_baset::named_port_connectiont & +to_verilog_named_port_connection(exprt &expr) +{ + PRECONDITION(expr.id() == ID_named_port_connection); + verilog_inst_baset::named_port_connectiont::check(expr); + return static_cast(expr); +} + class verilog_instt : public verilog_inst_baset { public: diff --git a/src/verilog/verilog_typecheck.cpp b/src/verilog/verilog_typecheck.cpp index ffb6cb3b2..d9b6f62ae 100644 --- a/src/verilog/verilog_typecheck.cpp +++ b/src/verilog/verilog_typecheck.cpp @@ -121,24 +121,24 @@ void verilog_typecheckt::typecheck_port_connections( for(auto &connection : inst.connections()) { - if( - connection.id() != ID_named_port_connection || - connection.operands().size() != 2) + if(connection.id() != ID_named_port_connection) { throw errort().with_location(inst.source_location()) << "expected a named port connection"; } - exprt &op = to_binary_expr(connection).op1(); - const irep_idt &name = - to_binary_expr(connection).op0().get(ID_identifier); + auto &named_port_connection = + to_verilog_named_port_connection(connection); + + exprt &value = named_port_connection.value(); + const irep_idt &name = named_port_connection.port().get(ID_identifier); bool found=false; std::string identifier= id2string(symbol.module)+"."+id2string(name); - to_binary_expr(connection).op0().set(ID_identifier, identifier); + named_port_connection.port().set(ID_identifier, identifier); if(assigned_ports.find(name)!= assigned_ports.end()) @@ -153,8 +153,8 @@ void verilog_typecheckt::typecheck_port_connections( { auto &p_expr = static_cast(port); found=true; - typecheck_port_connection(op, p_expr); - to_binary_expr(connection).op0().type() = p_expr.type(); + typecheck_port_connection(value, p_expr); + named_port_connection.port().type() = p_expr.type(); break; } }