Verilog/BCD_to_7seg.bld at master · devendrajat64/Verilog · GitHub

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Release 14.7 ngdbuild P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
-intstyle ise -dd _ngo -nt timestamp -i -p xc3s500e-fg320-4 BCD_to_7seg.ngc
BCD_to_7seg.ngd

Reading NGO file "D:/verilog programms/BCD_7SEg/BCD_to_7seg.ngc" ...
Gathering constraint information from source properties...
Done.

Resolving constraint associations...
Checking Constraint Associations...
Done...

Checking expanded design ...

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 4391348 kilobytes

Writing NGD file "BCD_to_7seg.ngd" ...
Total REAL time to NGDBUILD completion:  3 sec
Total CPU time to NGDBUILD completion:   3 sec

Writing NGDBUILD log file "BCD_to_7seg.bld"...