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wengwzwengwz
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fix timing violation in RX datapath and add support for blue-crc updates
1 parent 13d7a8a commit e148a74

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15 files changed

+363
-185
lines changed

15 files changed

+363
-185
lines changed

‎fpga/UdpCmacLoopPerfTest/Makefile

+7-2
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,9 @@ ROOT_DIR = $(abspath ../../)
22
SCRIPTS_DIR = $(ROOT_DIR)/scripts
33
include $(SCRIPTS_DIR)/Makefile.base
44
LOCALSRCDIR = $(ROOT_DIR)/src:$(ROOT_DIR)/src/includes
5-
LIBSRCDIR = $(ROOT_DIR)/lib/blue-wrapper/src:$(ROOT_DIR)/lib/blue-crc/src
6-
CRC_TAB_SCRIPT = $(ROOT_DIR)/lib/blue-crc/scripts/gen_crc_tab.py
5+
LIB_CRC_DIR = $(ROOT_DIR)/lib/blue-crc
6+
LIBSRCDIR = $(ROOT_DIR)/lib/blue-wrapper/src:$(LIB_CRC_DIR)/src
7+
CRC_TAB_SCRIPT = $(LIB_CRC_DIR)/scripts/gen_crc_tab.py
78
BSV_DIR = ../common/bsv
89

910
# Design Configurations
@@ -61,6 +62,10 @@ endif
6162

6263
verilog: $(BSV_MODULES)
6364
cp ../common/verilog/UdpCmacRxTxWrapper.v $(DIR_VLOG_GEN)
65+
ifeq ($(SUPPORT_RDMA), True)
66+
find $(LIB_CRC_DIR)/lib/primitives/ -name "*.v" -exec cp {} $(DIR_VLOG_GEN) \;
67+
endif
68+
6469
$(BSV_MODULES):
6570
mkdir -p $(BUILDDIR)
6671
mkdir -p $(DIR_VLOG_GEN)

‎fpga/UdpCmacPerfTest/Makefile

+7-2
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,9 @@ ROOT_DIR = $(abspath ../../)
22
SCRIPTS_DIR = $(ROOT_DIR)/scripts
33
include $(SCRIPTS_DIR)/Makefile.base
44
LOCALSRCDIR = $(ROOT_DIR)/src:$(ROOT_DIR)/src/includes
5-
LIBSRCDIR = $(ROOT_DIR)/lib/blue-wrapper/src:$(ROOT_DIR)/lib/blue-crc/src
6-
CRC_TAB_SCRIPT = $(ROOT_DIR)/lib/blue-crc/scripts/gen_crc_tab.py
5+
LIB_CRC_DIR = $(ROOT_DIR)/lib/blue-crc
6+
LIBSRCDIR = $(ROOT_DIR)/lib/blue-wrapper/src:$(LIB_CRC_DIR)/src
7+
CRC_TAB_SCRIPT = $(LIB_CRC_DIR)/scripts/gen_crc_tab.py
78
BSV_DIR = ../common/bsv
89

910
# Design Configurations
@@ -62,6 +63,10 @@ endif
6263

6364
verilog: $(BSV_MODULES)
6465
cp ../common/verilog/UdpCmacRxTxWrapper.v $(DIR_VLOG_GEN)
66+
ifeq ($(SUPPORT_RDMA), True)
67+
find $(LIB_CRC_DIR)/lib/primitives/ -name "*.v" -exec cp {} $(DIR_VLOG_GEN) \;
68+
endif
69+
6570
$(BSV_MODULES):
6671
mkdir -p $(BUILDDIR)
6772
mkdir -p $(DIR_VLOG_GEN)

‎fpga/XdmaUdpCmac/Makefile

+17-8
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,9 @@ ROOT_DIR = $(abspath ../../)
22
SCRIPTS_DIR = $(ROOT_DIR)/scripts
33
include $(SCRIPTS_DIR)/Makefile.base
44
LOCALSRCDIR = $(ROOT_DIR)/src:$(ROOT_DIR)/src/includes
5-
LIBSRCDIR = $(ROOT_DIR)/lib/blue-wrapper/src:$(ROOT_DIR)/lib/blue-crc/src
6-
CRC_TAB_SCRIPT = $(ROOT_DIR)/lib/blue-crc/scripts/gen_crc_tab.py
5+
LIB_CRC_DIR = $(ROOT_DIR)/lib/blue-crc
6+
LIBSRCDIR = $(ROOT_DIR)/lib/blue-wrapper/src:$(LIB_CRC_DIR)/src
7+
CRC_TAB_SCRIPT = $(LIB_CRC_DIR)/scripts/gen_crc_tab.py
78
BSV_DIR = ../common/bsv
89

910
# Design Configurations
@@ -13,15 +14,15 @@ BSV_DIR = ../common/bsv
1314
# SUPPORT_RDMA: False - Disable, True - Enable
1415
QSFP_IDX = 1
1516
ENABLE_CMAC_RSFEC = 1
16-
#ENABLE_ARP_PROCESS = 0
17+
ENABLE_BYPASS_MODE = 1
1718
ENABLE_DEBUG_MODE = 1
18-
SUPPORT_RDMA ?= False
19+
SUPPORT_RDMA ?= True
1920

2021
MACROFLAGS = -D IS_SUPPORT_RDMA=$(SUPPORT_RDMA)
2122

2223
# Pass arguments to vivado
2324
export PART = xcvu13p-fhgb2104-2-i
24-
export BUILD_TOP = XdmaUdpCmacWrapper
25+
export BUILD_TOP = XdmaUdpCmacWrapper512
2526

2627
## Directories and Files
2728
export DIR_VLOG = ./verilog
@@ -45,7 +46,7 @@ export DEBUG_PROBES_EN = 1
4546
export TARGET_CLOCKS = xdma_axi_aclk
4647
export MAX_NET_PATH_NUM = 1000
4748

48-
BSV_MODULES = CmacRecvMonitor CmacSendMonitor XdmaUdpIpEthCmacRxTx
49+
BSV_MODULES = CmacRecvMonitor CmacSendMonitor XdmaUdpIpEthCmacRxTx XdmaUdpIpEthBypassCmacRxTx
4950
IP = xdma clk_wiz cmac_mon_ila axis512_mon_ila
5051
ifeq ($(ENABLE_CMAC_RSFEC), 1)
5152
IP += cmac_rsfec_q$(QSFP_IDX)
@@ -55,19 +56,24 @@ endif
5556
XDC = common pciex16 qsfp$(QSFP_IDX)
5657

5758

58-
table:
59+
mem_init:
5960
ifeq ($(SUPPORT_RDMA), True)
61+
mkdir -p $(DIR_MEM_CONFIG)
6062
python3 $(CRC_TAB_SCRIPT) $(SCRIPTS_DIR)/crc_ieee_32_1024.json $(DIR_MEM_CONFIG)
6163
endif
6264

6365
verilog: $(BSV_MODULES)
6466
cp ../common/verilog/UdpCmacRxTxWrapper.v $(DIR_VLOG_GEN)
67+
ifeq ($(SUPPORT_RDMA), True)
68+
find $(LIB_CRC_DIR)/lib/primitives/ -name "*.v" -exec cp {} $(DIR_VLOG_GEN) \;
69+
endif
6570
$(BSV_MODULES):
6671
mkdir -p $(BUILDDIR)
6772
mkdir -p $(DIR_VLOG_GEN)
6873
bsc -elab $(VERILOGFLAGS) $(DIRFLAGS) $(MISCFLAGS) $(RECOMPILEFLAGS) $(RUNTIMEFLAGS) $(TRANSFLAGS) $(MACROFLAGS) -g mk$@ $(BSV_DIR)/$@.bsv
6974
bluetcl $(SCRIPTS_DIR)/listVlogFiles.tcl -bdir $(BUILDDIR) -vdir $(BUILDDIR) mk$@ mk$@ | grep -i '\.v' | xargs -I {} cp {} $(DIR_VLOG_GEN)
7075

76+
7177
ip: $(IP)
7278
$(IP):
7379
@mkdir -p $(DIR_IP_TCL)
@@ -87,8 +93,11 @@ endif
8793
ifeq ($(ENABLE_DEBUG_MODE), 1)
8894
@echo "\`define ENABLE_DEBUG_MODE" >> $(CONFIG_FILE)
8995
endif
96+
ifeq ($(ENABLE_BYPASS_MODE), 1)
97+
@echo "\`define ENABLE_BYPASS_MODE" >> $(CONFIG_FILE)
98+
endif
9099

91-
build: table verilog ip xdc config
100+
build: mem_init verilog ip xdc config
92101
vivado -mode batch -source ../common/tcl/non_proj_build.tcl 2>&1 | tee ./build_run.log
93102

94103
clean:

‎fpga/XdmaUdpCmac/verilog/XdmaUdpCmacWrapper.v

+3-3
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11

2-
module XdmaUdpCmacWrapper#(
2+
module XdmaUdpCmacWrapper256#(
33
parameter PCIE_GT_LANE_WIDTH = 16,
44
parameter CMAC_GT_LANE_WIDTH = 4
55
)(
@@ -419,8 +419,8 @@ module XdmaUdpCmacWrapper512#(
419419
.xdma_clk (xdma_axi_aclk ),
420420
.xdma_reset(xdma_axi_aresetn),
421421

422-
.udp_clk (udp_clk ),
423-
.udp_reset (udp_reset),
422+
.udp_clk (xdma_axi_aclk ),
423+
.udp_reset (xdma_axi_aresetn),
424424

425425
.gt_ref_clk_p(qsfp_ref_clk_p ),
426426
.gt_ref_clk_n(qsfp_ref_clk_n ),

‎fpga/XdmaUdpCmacLoop/Makefile

+7-2
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,9 @@ ROOT_DIR = $(abspath ../../)
22
SCRIPTS_DIR = $(ROOT_DIR)/scripts
33
include $(SCRIPTS_DIR)/Makefile.base
44
LOCALSRCDIR = $(ROOT_DIR)/src:$(ROOT_DIR)/src/includes
5-
LIBSRCDIR = $(ROOT_DIR)/lib/blue-wrapper/src:$(ROOT_DIR)/lib/blue-crc/src
6-
CRC_TAB_SCRIPT = $(ROOT_DIR)/lib/blue-crc/scripts/gen_crc_tab.py
5+
LIB_CRC_DIR = $(ROOT_DIR)/lib/blue-crc
6+
LIBSRCDIR = $(ROOT_DIR)/lib/blue-wrapper/src:$(LIB_CRC_DIR)/src
7+
CRC_TAB_SCRIPT = $(LIB_CRC_DIR)/scripts/gen_crc_tab.py
78
BSV_DIR = ../common/bsv
89

910
# Design Configurations
@@ -61,6 +62,10 @@ endif
6162

6263
verilog: $(BSV_MODULES)
6364
cp ../common/verilog/UdpCmacRxTxWrapper.v $(DIR_VLOG_GEN)
65+
ifeq ($(SUPPORT_RDMA), True)
66+
find $(LIB_CRC_DIR)/lib/primitives/ -name "*.v" -exec cp {} $(DIR_VLOG_GEN) \;
67+
endif
68+
6469
$(BSV_MODULES):
6570
mkdir -p $(BUILDDIR)
6671
mkdir -p $(DIR_VLOG_GEN)

‎fpga/XdmaUdpCmacPerfTest/Makefile

+7-2
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,9 @@ ROOT_DIR = $(abspath ../../)
22
SCRIPTS_DIR = $(ROOT_DIR)/scripts
33
include $(SCRIPTS_DIR)/Makefile.base
44
LOCALSRCDIR = $(ROOT_DIR)/src:$(ROOT_DIR)/src/includes
5-
LIBSRCDIR = $(ROOT_DIR)/lib/blue-wrapper/src:$(ROOT_DIR)/lib/blue-crc/src
6-
CRC_TAB_SCRIPT = $(ROOT_DIR)/lib/blue-crc/scripts/gen_crc_tab.py
5+
LIB_CRC_DIR = $(ROOT_DIR)/lib/blue-crc
6+
LIBSRCDIR = $(ROOT_DIR)/lib/blue-wrapper/src:$(LIB_CRC_DIR)/src
7+
CRC_TAB_SCRIPT = $(LIB_CRC_DIR)/scripts/gen_crc_tab.py
78
BSV_DIR = ../common/bsv
89

910
# Design Configurations
@@ -64,6 +65,10 @@ endif
6465

6566
verilog: $(BSV_MODULES)
6667
cp ../common/verilog/UdpCmacRxTxWrapper.v $(DIR_VLOG_GEN)
68+
ifeq ($(SUPPORT_RDMA), True)
69+
find $(LIB_CRC_DIR)/lib/primitives/ -name "*.v" -exec cp {} $(DIR_VLOG_GEN) \;
70+
endif
71+
6772
$(BSV_MODULES):
6873
mkdir -p $(BUILDDIR)
6974
mkdir -p $(DIR_VLOG_GEN)

‎fpga/common/bsv/TestUdpCmacRxTx.bsv

+14-8
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ import AxiStreamTypes :: *;
1313
typedef 33 CYCLE_COUNT_WIDTH;
1414
typedef 16 CASE_COUNT_WIDTH;
1515
typedef 8 FRAME_COUNT_WIDTH;
16-
typedef 256 TEST_CASE_NUM;
16+
typedef 4 TEST_CASE_NUM;
1717

1818
typedef 2048 PAYLOAD_BYTE_NUM;
1919
typedef TMul#(PAYLOAD_BYTE_NUM, 8) PAYLOAD_WIDTH;
@@ -55,7 +55,7 @@ module mkTestUdpCmacRxTx(TestUdpCmacRxTx);
5555

5656

5757
// Input/Output FIFO
58-
FIFOF#(AxiStream512) refAxiStreamBuf <- mkSizedFIFOF(valueOf(TEST_CASE_NUM));
58+
FIFOF#(AxiStream512) refAxiStreamBuf <- mkSizedFIFOF(512);
5959
FIFOF#(AxiStream512) xdmaAxiStreamOutTxBuf <- mkFIFOF;
6060
FIFOF#(AxiStream512) xdmaAxiStreamInRxBuf <- mkFIFOF;
6161

@@ -93,21 +93,27 @@ module mkTestUdpCmacRxTx(TestUdpCmacRxTx);
9393
let rawData <- randRawData.next;
9494
Bit#(PAYLOAD_EXT_WIDTH) extRawData = zeroExtend(rawData);
9595
Vector#(PAYLOAD_FRAME_NUM, Bit#(AXIS512_TDATA_WIDTH)) rawDataVec = unpack(extRawData);
96+
// AxiStream512 axiStream = AxiStream {
97+
// tData: rawDataVecReg[inputFrameCount],
98+
// tKeep: setAllBits,
99+
// tLast: False,
100+
// tUser: 0
101+
// };
96102
AxiStream512 axiStream = AxiStream {
97-
tData: rawDataVecReg[inputFrameCount],
103+
tData: setAllBits,
98104
tKeep: setAllBits,
99105
tLast: False,
100106
tUser: 0
101107
};
102108

103-
if (inputFrameCount == 0) begin
104-
rawDataVecReg <= rawDataVec;
105-
axiStream.tData = rawDataVec[0];
106-
end
109+
// if (inputFrameCount == 0) begin
110+
// rawDataVecReg <= rawDataVec;
111+
// axiStream.tData = rawDataVec[0];
112+
// end
107113

108114
if (nextFrameCount == fromInteger(payloadFrameNum)) begin
109115
axiStream.tLast = True;
110-
axiStream.tKeep = axiStream.tKeep >> valueOf(EXTRA_BYTE_NUM);
116+
//axiStream.tKeep = axiStream.tKeep >> valueOf(EXTRA_BYTE_NUM);
111117
inputFrameCount <= 0;
112118
inputCaseCount <= inputCaseCount + 1;
113119
end

‎fpga/common/bsv/XdmaUdpIpEthBypassCmacRxTx.bsv

+27-2
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ typedef 32'hC0A80102 SOURCE_IP_ADDR;
3636

3737
typedef 32'h00000000 TEST_NET_MASK;
3838
typedef 32'h00000000 TEST_GATE_WAY;
39-
typedef 88 TEST_UDP_PORT;
39+
typedef UDP_PORT_RDMA TEST_UDP_PORT;
4040
typedef 2048 TEST_PAYLOAD_SIZE;
4141

4242

@@ -97,8 +97,10 @@ module mkUdpIpEthBypassRxTxForXdma(UdpIpEthBypassRxTxForXdma);
9797
endrule
9898

9999
rule recvUdpIpMetaData;
100-
let udpIpMetaData = udpIpEthBypassRxTx.udpIpMetaDataRxOut.first;
101100
udpIpEthBypassRxTx.udpIpMetaDataRxOut.deq;
101+
endrule
102+
103+
rule recvMacMetaData;
102104
udpIpEthBypassRxTx.macMetaDataRxOut.deq;
103105
endrule
104106

@@ -121,6 +123,29 @@ module mkUdpIpEthBypassRxTxForXdma(UdpIpEthBypassRxTxForXdma);
121123
interface cmacAxiStreamTxOut = cmacAxiStream512TxOut;
122124
endmodule
123125

126+
interface RawUdpIpEthBypassRxTxForXdma;
127+
interface RawAxiStreamSlave#(AXIS512_TKEEP_WIDTH, AXIS_TUSER_WIDTH) xdmaAxiStreamTxIn;
128+
interface RawAxiStreamMaster#(AXIS512_TKEEP_WIDTH, AXIS_TUSER_WIDTH) xdmaAxiStreamRxOut;
129+
interface RawAxiStreamSlave#(AXIS512_TKEEP_WIDTH, AXIS_TUSER_WIDTH) cmacAxiStreamRxIn;
130+
interface RawAxiStreamMaster#(AXIS512_TKEEP_WIDTH, AXIS_TUSER_WIDTH) cmacAxiStreamTxOut;
131+
endinterface
132+
133+
(* synthesize *)
134+
module mkRawUdpIpEthBypassRxTxForXdma(RawUdpIpEthBypassRxTxForXdma);
135+
let udpIpEthBypass <- mkUdpIpEthBypassRxTxForXdma;
136+
137+
let rawXdmaAxiStreamTxIn <- mkFifoInToRawAxiStreamSlave(udpIpEthBypass.xdmaAxiStreamTxIn);
138+
let rawXdmaAxiStreamRxOut <- mkFifoOutToRawAxiStreamMaster(udpIpEthBypass.xdmaAxiStreamRxOut);
139+
let rawCmacAxiStreamRxIn <- mkFifoInToRawAxiStreamSlave(udpIpEthBypass.cmacAxiStreamRxIn);
140+
let rawCmacAxiStreamTxOut <- mkFifoOutToRawAxiStreamMaster(udpIpEthBypass.cmacAxiStreamTxOut);
141+
142+
interface xdmaAxiStreamTxIn = rawXdmaAxiStreamTxIn;
143+
interface xdmaAxiStreamRxOut = rawXdmaAxiStreamRxOut;
144+
interface cmacAxiStreamRxIn = rawCmacAxiStreamRxIn;
145+
interface cmacAxiStreamTxOut = rawCmacAxiStreamTxOut;
146+
147+
endmodule
148+
124149

125150
interface XdmaUdpIpEthBypassCmacRxTx;
126151
// Interface with CMAC IP

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