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BIGWJZBIGWJZ
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Fix streamUtils and pass all test
1 parent cec958d commit e0b92ab

7 files changed

+143
-10
lines changed

‎backend/verilog.tar

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‎src/DmaCompleter.bsv

+7
Original file line numberDiff line numberDiff line change
@@ -104,10 +104,12 @@ module mkCompleterRequest(CompleterRequest);
104104
let descriptor = getDescriptorFromFirstBeat(axiStream);
105105
case (descriptor.reqType)
106106
fromInteger(valueOf(MEM_WRITE_REQ)): begin
107+
$display("SIM INFO @ mkCompleterRequest: MemWrite Detect!");
107108
if (descriptor.dwordCnt == fromInteger(valueOf(IDEA_DWORD_CNT_OF_CSR)) && isFirstBytesAllValid(sideBand)) begin
108109
let firstData = getDataFromFirstBeat(axiStream);
109110
DmaCsrValue wrValue = firstData[valueOf(DMA_CSR_ADDR_WIDTH)-1:0];
110111
DmaCsrAddr wrAddr = getCsrAddrFromCqDescriptor(descriptor);
112+
$display("SIM INFO @ mkCompleterRequest: Valid wrReq with Addr %h, data %h", wrAddr, wrValue);
111113
let wrReq = CsrWriteReq {
112114
addr : wrAddr,
113115
value : wrValue
@@ -119,11 +121,13 @@ module mkCompleterRequest(CompleterRequest);
119121
end
120122
end
121123
fromInteger(valueOf(MEM_READ_REQ)): begin
124+
$display("SIM INFO @ mkCompleterRequest: MemRead Detect!");
122125
let rdReqAddr = getCsrAddrFromCqDescriptor(descriptor);
123126
let rdReq = CsrReadReq{
124127
addr: rdReqAddr,
125128
cqDescriptor: descriptor
126129
};
130+
$display("SIM INFO @ mkCompleterRequest: Valid rdReq with Addr %h", rdReqAddr);
127131
rdReqFifo.enq(rdReq);
128132
end
129133
default: illegalPcieReqCntReg <= illegalPcieReqCntReg + 1;
@@ -148,6 +152,7 @@ module mkCompleterComplete(CompleterComplete);
148152
let cqDescriptor = rdReqFifo.first.cqDescriptor;
149153
let addr = rdReqFifo.first.addr;
150154
rdReqFifo.deq;
155+
$display("SIM INFO @ mkCompleterComplete: Valid rdResp with Addr %h, data %h", addr, value);
151156
let ccDescriptor = PcieCompleterCompleteDescriptor {
152157
reserve0 : 0,
153158
attributes : cqDescriptor.attributes,
@@ -231,6 +236,8 @@ module mkDmaCompleter(DmaCompleter);
231236
rule procCsrReadResp;
232237
let req = csrRdReqStoreFifo.first;
233238
let resp = h2cCsrReadDataFifo.first;
239+
csrRdReqStoreFifo.deq;
240+
h2cCsrReadDataFifo.deq;
234241
cmplComplete.csrReadRespFifoIn.enq(resp);
235242
cmplComplete.csrReadReqFifoIn.enq(req);
236243
endrule

‎src/DmaRequester.bsv

+66
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,15 @@
11
import FIFOF::*;
2+
import GetPut::*;
23

34
import SemiFifo::*;
5+
import StreamUtils::*;
46
import PcieTypes::*;
57
import PcieAxiStreamTypes::*;
68
import PcieDescriptorTypes::*;
79
import DmaTypes::*;
810

11+
typedef TSub#(DATA_WIDTH, DES_RQ_DESCRIPTOR_WIDTH) ONE_TLP_THRESH;
12+
913
typedef PcieAxiStream#(PCIE_REQUESTER_REQUEST_TUSER_WIDTH) ReqReqAxiStream;
1014
typedef PcieAxiStream#(PCIE_REQUESTER_COMPLETE_TUSER_WIDTH) ReqCmplAxiStream;
1115

@@ -21,6 +25,9 @@ interface RequesterRequest;
2125
interface FifoIn#(DmaRequest) wrReqFifoIn;
2226
interface FifoIn#(DmaRequest) rdReqFifoIn;
2327
interface FifoOut#(ReqReqAxiStream) axiStreamFifoOut;
28+
interface Put#(Bool) postedEn;
29+
interface Put#(Bool) nonPostedEn;
30+
interface Get#(Bool) isWriteDataRecvDone;
2431
endinterface
2532

2633
interface RequesterComplete;
@@ -30,17 +37,76 @@ interface RequesterComplete;
3037
endinterface
3138

3239
module mkRequesterRequest(RequesterRequest);
40+
StreamConcat streamConcat <- mkStreamConcat;
41+
3342
FIFOF#(DataStream) wrDataInFifo <- mkFIFOF;
3443
FIFOF#(DmaRequest) wrReqInFifo <- mkFIFOF;
3544
FIFOF#(DmaRequest) rdReqInFifo <- mkFIFOF;
3645
FIFOF#(ReqReqAxiStream) axiStreamOutFifo <- mkFIFOF;
3746

47+
Reg#(DmaMemAddr) inflightRemainBytesReg <- mkReg(0);
48+
Reg#(Bool) isInWritingReg <- mkReg(False);
49+
Wire#(Bool) postedEnWire <- mkDWire(False);
50+
Wire#(Bool) nonPostedEnWire <- mkDWire(True);
51+
52+
function DataStream genRQDescriptorStream(DmaRequest req, Bool isWrite);
53+
let descriptor = PcieRequesterRequestDescriptor {
54+
forceECRC : False,
55+
attributes : 0,
56+
trafficClass : 0,
57+
requesterIdEn : False,
58+
completerId : 0,
59+
tag : 0,
60+
requesterId : 0,
61+
isPoisoned : False,
62+
reqType : isWrite ? fromInteger(valueOf(MEM_WRITE_REQ)) : fromInteger(valueOf(MEM_READ_REQ)),
63+
dwordCnt : truncate(req.length >> 2 + (req.length[0] | req.length[1])),
64+
address : truncate(req.startAddr >> 2),
65+
addrType : 2'b10
66+
};
67+
ByteEn byteEn = 1;
68+
let stream = DataStream {
69+
data : zeroExtend(pack(descriptor)),
70+
byteEn : (byteEn << (valueOf(TDiv#(DES_RQ_DESCRIPTOR_WIDTH, BYTE_WIDTH)) + 1)) - 1,
71+
isFirst : True,
72+
isLast : False
73+
};
74+
return stream;
75+
endfunction
76+
3877
// TODO: RQ Logic
78+
rule recvWriteReq if (postedEnWire);
79+
if (!isInWritingReg) begin
80+
let wrReq = wrReqInFifo.first;
81+
let wrData = wrDataInFifo.first;
82+
wrReqInFifo.deq;
83+
wrDataInFifo.deq;
84+
isInWritingReg <= (wrReq.length > fromInteger(valueOf(ONE_TLP_THRESH)));
85+
end
86+
endrule
3987

4088
interface wrDataFifoIn = convertFifoToFifoIn(wrDataInFifo);
4189
interface wrReqFifoIn = convertFifoToFifoIn(wrReqInFifo);
4290
interface rdReqFifoIn = convertFifoToFifoIn(rdReqInFifo);
4391
interface axiStreamFifoOut = convertFifoToFifoOut(axiStreamOutFifo);
92+
93+
interface Put postedEn;
94+
method Action put(Bool postedEnable);
95+
postedEnWire <= postedEnable;
96+
endmethod
97+
endinterface
98+
99+
interface Put nonPostedEn;
100+
method Action put(Bool nonPostedEnable);
101+
nonPostedEnWire <= nonPostedEnable;
102+
endmethod
103+
endinterface
104+
105+
interface Get isWriteDataRecvDone;
106+
method ActionValue#(Bool) get();
107+
return (inflightRemainBytesReg == 0);
108+
endmethod
109+
endinterface
44110
endmodule
45111

46112
module mkRequesterComplete(RequesterComplete);

‎src/PcieDescriptorTypes.bsv

+52-3
Original file line numberDiff line numberDiff line change
@@ -56,10 +56,10 @@ typedef struct {
5656
typedef 96 DES_CC_DESCRIPTOR_WIDTH;
5757
typedef 3 DES_CMPL_STATUS_WIDTH;
5858
typedef 13 DES_CMPL_BYTE_CNT_WIDTH;
59-
typedef 7 DES_LOWER_ADDR_WIDTH;
59+
typedef 7 DES_CC_LOWER_ADDR_WIDTH;
6060
typedef Bit#(DES_CMPL_STATUS_WIDTH) CmplStatus;
6161
typedef Bit#(DES_CMPL_BYTE_CNT_WIDTH) CmplByteCnt;
62-
typedef Bit#(DES_LOWER_ADDR_WIDTH) LowerAddr;
62+
typedef Bit#(DES_CC_LOWER_ADDR_WIDTH) CCLowerAddr;
6363

6464
typedef 0 DES_CC_STAUS_SUCCESS;
6565
typedef 1 DES_CC_STATUS_UPSUPPORT;
@@ -85,9 +85,58 @@ typedef struct {
8585
CmplByteCnt byteCnt;
8686
ReserveBit6 reserve3;
8787
AddrType addrType;
88-
LowerAddr lowerAddr;
88+
CCLowerAddr lowerAddr;
8989
} PcieCompleterCompleteDescriptor deriving(Bits, Eq, Bounded, FShow);
9090

91+
typedef 128 DES_RQ_DESCRIPTOR_WIDTH;
92+
93+
typedef struct {
94+
// DW + 3
95+
Bool forceECRC;
96+
Attributes attributes;
97+
TrafficClass trafficClass;
98+
Bool requesterIdEn;
99+
BusDeviceFunc completerId;
100+
Tag tag;
101+
// DW + 2
102+
BusDeviceFunc requesterId;
103+
Bool isPoisoned;
104+
ReqType reqType;
105+
DwordCount dwordCnt;
106+
// DW + 1 & DW + 0
107+
Address address;
108+
AddrType addrType;
109+
} PcieRequesterRequestDescriptor deriving(Bits, Eq, Bounded, FShow);
110+
111+
typedef 96 DES_RC_DESCRIPTOR_WIDTH;
112+
typedef 4 DES_ERROR_CODE_WIDTH;
113+
typedef 12 DES_RC_LOWER_ADDR_WIDTH;
114+
115+
typedef Bit#(DES_ERROR_CODE_WIDTH) ErrorCode;
116+
typedef Bit#(DES_RC_LOWER_ADDR_WIDTH) RCLowerAddr;
117+
118+
typedef struct {
119+
// DW + 2
120+
ReserveBit1 reserve0;
121+
Attributes attributes;
122+
TrafficClass trafficClass;
123+
ReserveBit1 reserve1;
124+
BusDeviceFunc completerId;
125+
Tag tag;
126+
// DW + 1
127+
BusDeviceFunc requesterId;
128+
ReserveBit1 reserve2;
129+
Bool isPoisoned;
130+
CmplStatus status;
131+
DwordCount dwordCnt;
132+
ReserveBit1 reserve3;
133+
Bool isRequestCompleted;
134+
Bool isLockedReadCmpl;
135+
CmplByteCnt byteCnt;
136+
ErrorCode errorcode;
137+
RCLowerAddr lowerAddr;
138+
} PcieRequesterCompleteDescriptor deriving(Bits, Eq, Bounded, FShow);
139+
91140
// Pcie Tlp types of descriptor
92141
typedef 4'b0000 MEM_READ_REQ;
93142
typedef 4'b0001 MEM_WRITE_REQ;

‎src/PrimUtils.bsv

+12-2
Original file line numberDiff line numberDiff line change
@@ -245,17 +245,27 @@ interface CounteredFIFOF#(type t);
245245
endinterface
246246

247247
module mkCounteredFIFOF#(Integer depth)(CounteredFIFOF#(t)) provisos(Bits#(t, tSz));
248+
Wire#(Bool) hasDeqCall <- mkDWire(False);
249+
Wire#(Bool) hasEnqCall <- mkDWire(False);
248250
Reg#(FifoSize) curSize <- mkReg(0);
249251
FIFOF#(t) fifo <- mkSizedFIFOF(depth);
250252

253+
rule updateSize;
254+
case({pack(hasEnqCall), pack(hasDeqCall)})
255+
2'b10: curSize <= curSize + 1;
256+
2'b01: curSize <= curSize -1;
257+
default: curSize <= curSize;
258+
endcase
259+
endrule
260+
251261
method Action enq (t x);
252262
fifo.enq(x);
253-
curSize <= curSize + 1;
263+
hasEnqCall <= True;
254264
endmethod
255265

256266
method Action deq;
257267
fifo.deq;
258-
curSize <= curSize - 1;
268+
hasDeqCall <= True;
259269
endmethod
260270

261271
method t first = fifo.first;

‎src/StreamUtils.bsv

+3-3
Original file line numberDiff line numberDiff line change
@@ -99,9 +99,9 @@ function DataBytePtr convertByteEn2BytePtr (ByteEn byteEn);
9999
return ptr;
100100
endfunction
101101

102-
function Bool isByteEnZero(ByteEn byteEn) begin
103-
return !unpack(remainStream.byteEn[0]);
104-
end
102+
function Bool isByteEnZero(ByteEn byteEn);
103+
return !unpack(byteEn[0]);
104+
endfunction
105105

106106
function DataStream getEmptyStream ();
107107
return DataStream{

‎test/TestDmacVivado.bsv

+3-2
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ module mkTestDmacCsrWrRdLoop((* reset="sys_rst" *) Reset sysRst, TestDmacWrRdLoo
2222
BRAM_Configure {
2323
memorySize : valueOf(TEST_BRAM_SIZE),
2424
loadFormat : None,
25-
latency : 2,
25+
latency : 1,
2626
outFIFODepth: 3,
2727
allowWriteResponseBypass : False
2828
}
@@ -56,6 +56,7 @@ module mkTestDmacCsrWrRdLoop((* reset="sys_rst" *) Reset sysRst, TestDmacWrRdLoo
5656
endrule
5757

5858
rule testReadResp;
59+
$display("SIM INFO @ mkTestDmacCsrWrRdLoop: h2cRead resp detect!");
5960
let value <- ram.portB.response.get;
6061
dmac.h2cRead.dataFifoIn.enq(value);
6162
endrule
@@ -76,7 +77,7 @@ module mkTestDmacCsrWrRdLoopTb(TestDmacCsrWrRdLoopTb);
7677
BRAM_Configure {
7778
memorySize : valueOf(TEST_BRAM_SIZE),
7879
loadFormat : None,
79-
latency : 2,
80+
latency : 1,
8081
outFIFODepth: 3,
8182
allowWriteResponseBypass : False
8283
}

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