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nemecadnemecad
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Machine: refactor TLB setup
Removes the previous approach; instead, TLBs are now created every time. If virtual memory is disabled, the TLB logic is skipped.
1 parent 98099d8 commit 7b06705

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7 files changed

+449
-457
lines changed

7 files changed

+449
-457
lines changed

‎src/machine/CMakeLists.txt‎

Lines changed: 26 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -22,9 +22,9 @@ set(machine_SOURCES
2222
memory/cache/cache_policy.cpp
2323
memory/frontend_memory.cpp
2424
memory/memory_bus.cpp
25-
memory/tlb/tlb.cpp
26-
memory/tlb/tlb_policy.cpp
27-
memory/virtual/page_table_walker.cpp
25+
memory/tlb/tlb.cpp
26+
memory/tlb/tlb_policy.cpp
27+
memory/virtual/page_table_walker.cpp
2828
programloader.cpp
2929
predictor.cpp
3030
registers.cpp
@@ -71,11 +71,11 @@ set(machine_HEADERS
7171
utils.h
7272
execute/alu_op.h
7373
execute/mul_op.h
74-
memory/virtual/virtual_address.h
75-
memory/tlb/tlb.h
76-
memory/virtual/sv32.h
77-
memory/tlb/tlb_policy.h
78-
memory/virtual/page_table_walker.h
74+
memory/virtual/virtual_address.h
75+
memory/tlb/tlb.h
76+
memory/virtual/sv32.h
77+
memory/tlb/tlb_policy.h
78+
memory/virtual/page_table_walker.h
7979
)
8080

8181
# Object library is preferred, because the library archive is never really
@@ -123,12 +123,12 @@ if(NOT ${WASM})
123123
memory/backend/memory.test.h
124124
memory/frontend_memory.cpp
125125
memory/frontend_memory.h
126-
memory/tlb/tlb.h
127-
memory/tlb/tlb.cpp
128-
memory/tlb/tlb_policy.h
129-
memory/tlb/tlb_policy.cpp
130-
memory/virtual/page_table_walker.h
131-
memory/virtual/page_table_walker.cpp
126+
memory/tlb/tlb.h
127+
memory/tlb/tlb.cpp
128+
memory/tlb/tlb_policy.h
129+
memory/tlb/tlb_policy.cpp
130+
memory/virtual/page_table_walker.h
131+
memory/virtual/page_table_walker.cpp
132132
memory/memory_bus.cpp
133133
memory/memory_bus.h
134134
simulator_exception.cpp
@@ -154,12 +154,12 @@ if(NOT ${WASM})
154154
memory/cache/cache_policy.h
155155
memory/frontend_memory.cpp
156156
memory/frontend_memory.h
157-
memory/tlb/tlb.h
158-
memory/tlb/tlb.cpp
159-
memory/tlb/tlb_policy.h
160-
memory/tlb/tlb_policy.cpp
161-
memory/virtual/page_table_walker.h
162-
memory/virtual/page_table_walker.cpp
157+
memory/tlb/tlb.h
158+
memory/tlb/tlb.cpp
159+
memory/tlb/tlb_policy.h
160+
memory/tlb/tlb_policy.cpp
161+
memory/virtual/page_table_walker.h
162+
memory/virtual/page_table_walker.cpp
163163
memory/memory_bus.cpp
164164
memory/memory_bus.h
165165
simulator_exception.cpp
@@ -227,12 +227,12 @@ if(NOT ${WASM})
227227
memory/cache/cache_policy.h
228228
memory/frontend_memory.cpp
229229
memory/frontend_memory.h
230-
memory/tlb/tlb.h
231-
memory/tlb/tlb.cpp
232-
memory/tlb/tlb_policy.h
233-
memory/tlb/tlb_policy.cpp
234-
memory/virtual/page_table_walker.h
235-
memory/virtual/page_table_walker.cpp
230+
memory/tlb/tlb.h
231+
memory/tlb/tlb.cpp
232+
memory/tlb/tlb_policy.h
233+
memory/tlb/tlb_policy.cpp
234+
memory/virtual/page_table_walker.h
235+
memory/virtual/page_table_walker.cpp
236236
memory/memory_bus.cpp
237237
memory/memory_bus.h
238238
registers.cpp

‎src/machine/machine.cpp‎

Lines changed: 18 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -12,8 +12,6 @@ Machine::Machine(MachineConfig config, bool load_symtab, bool load_executable)
1212
: machine_config(std::move(config))
1313
, stat(ST_READY) {
1414
regs = new Registers();
15-
controlst
16-
= new CSR::ControlState(machine_config.get_simulated_xlen(), machine_config.get_isa_word());
1715
if (load_executable) {
1816
ProgramLoader program(machine_config.elf());
1917
this->machine_config.set_simulated_endian(program.get_endian());
@@ -79,19 +77,16 @@ Machine::Machine(MachineConfig config, bool load_symtab, bool load_executable)
7977
access_time_burst,
8078
access_enable_burst);
8179

82-
controlst = new CSR::ControlState(machine_config.get_simulated_xlen(), machine_config.get_isa_word());
83-
if (machine_config.get_vm_enabled()) {
84-
tlb_program.emplace(cch_program, PROGRAM, machine_config.access_tlb_program());
85-
tlb_data.emplace(cch_data, DATA, machine_config.access_tlb_data());
86-
controlst->write_internal(CSR::Id::SATP, 0);
87-
tlb_program->on_csr_write(CSR::Id::SATP, 0);
88-
tlb_data->on_csr_write(CSR::Id::SATP, 0);
89-
}
80+
controlst
81+
= new CSR::ControlState(machine_config.get_simulated_xlen(), machine_config.get_isa_word());
9082

91-
instr_if_ = tlb_program ? static_cast<FrontendMemory *>(&*tlb_program)
92-
: static_cast<FrontendMemory *>(cch_program);
93-
data_if_ = tlb_data ? static_cast<FrontendMemory *>(&*tlb_data)
94-
: static_cast<FrontendMemory *>(cch_data);
83+
tlb_program = new TLB(
84+
cch_program, PROGRAM, machine_config.access_tlb_program(), machine_config.get_vm_enabled());
85+
tlb_data = new TLB(
86+
cch_data, DATA, machine_config.access_tlb_data(), machine_config.get_vm_enabled());
87+
controlst->write_internal(CSR::Id::SATP, 0);
88+
tlb_program->on_csr_write(CSR::Id::SATP, 0);
89+
tlb_data->on_csr_write(CSR::Id::SATP, 0);
9590

9691
predictor = new BranchPredictor(
9792
machine_config.get_bp_enabled(), machine_config.get_bp_type(),
@@ -100,11 +95,12 @@ Machine::Machine(MachineConfig config, bool load_symtab, bool load_executable)
10095

10196
if (machine_config.pipelined()) {
10297
cr = new CorePipelined(
103-
regs, predictor, instr_if_, data_if_, controlst,
104-
machine_config.get_simulated_xlen(), machine_config.get_isa_word(), machine_config.hazard_unit());
98+
regs, predictor, tlb_program, tlb_data, controlst, machine_config.get_simulated_xlen(),
99+
machine_config.get_isa_word(), machine_config.hazard_unit());
105100
} else {
106-
cr = new CoreSingle(regs, predictor, instr_if_, data_if_, controlst,
107-
machine_config.get_simulated_xlen(), machine_config.get_isa_word());
101+
cr = new CoreSingle(
102+
regs, predictor, tlb_program, tlb_data, controlst, machine_config.get_simulated_xlen(),
103+
machine_config.get_isa_word());
108104
}
109105
connect(
110106
this, &Machine::set_interrupt_signal, controlst, &CSR::ControlState::set_interrupt_signal);
@@ -211,14 +207,16 @@ Machine::~Machine() {
211207
regs = nullptr;
212208
delete mem;
213209
mem = nullptr;
210+
delete tlb_program;
211+
tlb_program = nullptr;
212+
delete tlb_data;
213+
tlb_data = nullptr;
214214
delete cch_program;
215215
cch_program = nullptr;
216216
delete cch_data;
217217
cch_data = nullptr;
218218
delete cch_level2;
219219
cch_level2 = nullptr;
220-
tlb_program.reset();
221-
tlb_data.reset();
222220
delete data_bus;
223221
data_bus = nullptr;
224222
delete mem_program_only;

‎src/machine/machine.h‎

Lines changed: 2 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,6 @@
2121
#include <QObject>
2222
#include <QTimer>
2323
#include <cstdint>
24-
#include <iostream>
2524
#include <optional>
2625
#include <ostream>
2726

@@ -50,8 +49,6 @@ class Machine : public QObject {
5049
TLB *get_tlb_program_rw();
5150
TLB *get_tlb_data_rw();
5251
void tlb_sync();
53-
FrontendMemory *instr_frontend() { return instr_if_; }
54-
FrontendMemory *data_frontend() { return data_if_; }
5552
const MemoryDataBus *memory_data_bus();
5653
MemoryDataBus *memory_data_bus_rw();
5754
SerialPort *serial_port();
@@ -150,10 +147,8 @@ private slots:
150147
Cache *cch_program = nullptr;
151148
Cache *cch_data = nullptr;
152149
Cache *cch_level2 = nullptr;
153-
std::optional<TLB> tlb_program;
154-
std::optional<TLB> tlb_data;
155-
FrontendMemory *instr_if_;
156-
FrontendMemory *data_if_;
150+
TLB *tlb_program = nullptr;
151+
TLB *tlb_data = nullptr;
157152
CSR::ControlState *controlst = nullptr;
158153
BranchPredictor *predictor = nullptr;
159154
Core *cr = nullptr;

‎src/machine/machineconfig.cpp‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4,9 +4,8 @@
44
#include "machine.h"
55

66
#include <QMap>
7-
#include <utility>
8-
#include <iostream>
97
#include <ostream>
8+
#include <utility>
109

1110
using namespace machine;
1211

@@ -345,7 +344,6 @@ MachineConfig::MachineConfig(const QSettings *sts, const QString &prefix) {
345344
bp_bht_addr_bits = sts->value(N("BranchPredictor_BitsBHTAddr"), DFC_BP_BHT_ADDR_BITS).toUInt();
346345
bp_bht_bits = bp_bhr_bits + bp_bht_addr_bits;
347346

348-
349347
// Virtual memory
350348
vm_enabled = sts->value(N("VMEnabled"), DFC_VM_ENABLED).toBool();
351349
tlb_data = TLBConfig(sts, N("DataTLB_"));

‎src/machine/memory/frontend_memory.cpp‎

Lines changed: 2 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,7 @@
11
#include "memory/frontend_memory.h"
22

3-
#include "tlb/tlb.h"
4-
53
#include "common/endian.h"
4+
#include "tlb/tlb.h"
65

76
namespace machine {
87

@@ -149,11 +148,7 @@ bool FrontendMemory::write_generic(
149148
const T value,
150149
AccessEffects type) {
151150
// See example in read_generic for byteswap explanation.
152-
const T swapped_value
153-
= byteswap_if(value, this->simulated_machine_endian != NATIVE_ENDIAN);
154-
if (auto tlb = dynamic_cast<TLB *>(this)) {
155-
return tlb->write(address, &swapped_value, sizeof(T), { .type = type }).changed;
156-
}
151+
const T swapped_value = byteswap_if(value, this->simulated_machine_endian != NATIVE_ENDIAN);
157152
return write(address, &swapped_value, sizeof(T), { .type = type }).changed;
158153
}
159154
FrontendMemory::FrontendMemory(Endian simulated_endian)

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