diff --git a/Configuration/PyReleaseValidation/README.md b/Configuration/PyReleaseValidation/README.md
index 33908547fbec0..756cdffc750cc 100644
--- a/Configuration/PyReleaseValidation/README.md
+++ b/Configuration/PyReleaseValidation/README.md
@@ -85,4 +85,8 @@ The offsets currently in use are:
 * 0.9001: Sonic Triton
 * 0.278: Weighted Vertexing in Blocks
 * 0.279: Weighted Vertexing in Blocks and tracking only wf
-
+* 0.111: Activate OuterTracker inefficiency (PS-p: bias rails inefficiency only)
+* 0.112: Activate OuterTracker inefficiency (PS-p: bias rails inefficiency; PS-s and SS: 1% bad strips)
+* 0.113: Activate OuterTracker inefficiency (PS-p: bias rails inefficiency; PS-s and SS: 5% bad strips)
+* 0.114: Activate OuterTracker inefficiency (PS-p: bias rails inefficiency; PS-s and SS: 10% bad strips)
+* 0.141: Activate emulation of the signal shape of the InnerTracker FE chip (CROC)
diff --git a/Configuration/PyReleaseValidation/python/upgradeWorkflowComponents.py b/Configuration/PyReleaseValidation/python/upgradeWorkflowComponents.py
index 77c9ce19d9625..3da7b379925ea 100644
--- a/Configuration/PyReleaseValidation/python/upgradeWorkflowComponents.py
+++ b/Configuration/PyReleaseValidation/python/upgradeWorkflowComponents.py
@@ -1876,6 +1876,29 @@ def condition(self, fragment, stepList, key, hasHarvest):
 upgradeWFs['OTInefficiency10PC'].offset = 0.114
 upgradeWFs['OTInefficiency10PC'].percent = 'Ten'
 
+#
+# Simulates CROC signal shape in IT modules
+#
+class UpgradeWorkflow_ITSignalShape(UpgradeWorkflow):
+    def setup_(self, step, stepName, stepDict, k, properties):
+        if 'Digi' in step:
+            stepDict[stepName][k] = merge([{'--customise': 'SimTracker/SiPhase2Digitizer/customizeForPhase2TrackerSignalShape.customizeSiPhase2ITSignalShape'}, stepDict[step][k]])
+    def condition(self, fragment, stepList, key, hasHarvest):
+        return '2026' in key
+# define several of them
+upgradeWFs['ITSignalShape'] = UpgradeWorkflow_ITSignalShape(
+    steps =  [
+        'Digi',
+        'DigiTrigger',
+    ],
+    PU =  [
+        'Digi',
+        'DigiTrigger',
+    ],
+    suffix = '_ITSignalShape',
+    offset = 0.141
+)
+
 # Specifying explicitly the --filein is not nice but that was the
 # easiest way to "skip" the output of step2 (=premixing stage1) for
 # filein (as it goes to pileup_input). It works (a bit accidentally
diff --git a/SimTracker/SiPhase2Digitizer/plugins/PixelDigitizerAlgorithm.cc b/SimTracker/SiPhase2Digitizer/plugins/PixelDigitizerAlgorithm.cc
index 08d490748d7d1..cdb3fa1a0f08a 100644
--- a/SimTracker/SiPhase2Digitizer/plugins/PixelDigitizerAlgorithm.cc
+++ b/SimTracker/SiPhase2Digitizer/plugins/PixelDigitizerAlgorithm.cc
@@ -80,8 +80,9 @@ PixelDigitizerAlgorithm::~PixelDigitizerAlgorithm() { LogDebug("PixelDigitizerAl
 // -- Select the Hit for Digitization
 //
 bool PixelDigitizerAlgorithm::select_hit(const PSimHit& hit, double tCorr, double& sigScale) const {
-  double time = hit.tof() - tCorr;
-  return (time >= theTofLowerCut_ && time < theTofUpperCut_);
+  // in case of signal-shape emulation do not apply [TofLower,TofUpper] selection
+  double toa = hit.tof() - tCorr;
+  return apply_timewalk_ || (toa >= theTofLowerCut_ && toa < theTofUpperCut_);
 }
 
 // ======================================================================
diff --git a/SimTracker/SiPhase2Digitizer/python/customizeForPhase2TrackerSignalShape.py b/SimTracker/SiPhase2Digitizer/python/customizeForPhase2TrackerSignalShape.py
new file mode 100644
index 0000000000000..c55ed04b0e977
--- /dev/null
+++ b/SimTracker/SiPhase2Digitizer/python/customizeForPhase2TrackerSignalShape.py
@@ -0,0 +1,27 @@
+import FWCore.ParameterSet.Config as cms
+
+#
+# activate signal shape in IT only
+#
+
+def customizeSiPhase2ITSignalShape(process):
+    ## for standard mixing
+    if hasattr(process,'mix') and hasattr(process.mix,'digitizers') and hasattr(process.mix.digitizers,'pixel'): 
+        if hasattr(process.mix.digitizers.pixel,'PixelDigitizerAlgorithm'):
+            print("# Activating signal shape emulation in IT pixel (planar)")
+            process.mix.digitizers.pixel.PixelDigitizerAlgorithm.ApplyTimewalk = True
+        if hasattr(process.mix.digitizers.pixel,'Pixel3DDigitizerAlgorithm'):
+            print("# Activating signal shape emulation in IT pixel (3D)")
+            process.mix.digitizers.pixel.Pixel3DDigitizerAlgorithm.ApplyTimewalk = True
+
+
+    ## for pre-mixing
+    if hasattr(process, "mixData") and hasattr(process.mixData, "workers") and hasattr(process.mixData.workers, "pixel"):
+        if hasattr(process.mixData.workers.pixel,'PixelDigitizerAlgorithm'):
+            print("# Activating signal shape emulation in IT pixel (planar)")
+            process.mixData.workers.pixel.PixelDigitizerAlgorithm.ApplyTimewalk = True
+        if hasattr(process.mixData.workers.pixel,'Pixel3DDigitizerAlgorithm'):
+            print("# Activating signal shape emulation in IT pixel (3D)")
+            process.mixData.workers.pixel.Pixel3DDigitizerAlgorithm.ApplyTimewalk = True
+
+    return process
diff --git a/SimTracker/SiPhase2Digitizer/python/phase2TrackerDigitizer_cfi.py b/SimTracker/SiPhase2Digitizer/python/phase2TrackerDigitizer_cfi.py
index e19632b04fd8c..78603e8bf6e7f 100644
--- a/SimTracker/SiPhase2Digitizer/python/phase2TrackerDigitizer_cfi.py
+++ b/SimTracker/SiPhase2Digitizer/python/phase2TrackerDigitizer_cfi.py
@@ -13,8 +13,8 @@
     NoiseInElectrons = cms.double(0.0),
     Phase2ReadoutMode = cms.int32(3), # Flag to decide Readout Mode :Digital(0) or Analog (linear TDR (-1), dual slope with slope parameters (+1,+2,+3,+4) with threshold subtraction
     AdcFullScale = cms.int32(15),
-    TofUpperCut = cms.double(12.5),
-    TofLowerCut = cms.double(-12.5),
+    TofUpperCut = cms.double(20.),
+    TofLowerCut = cms.double(-5.),
     AddNoisyPixels = cms.bool(False),
     Alpha2Order = cms.bool(True),			#D.B.: second order effect, does not switch off magnetic field as described
     AddNoise = cms.bool(False),