diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py
index ddc90b0..b650670 100644
--- a/WriteVHDLSyntax.py
+++ b/WriteVHDLSyntax.py
@@ -439,6 +439,17 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl
 
     first_merge_streamer = True
 
+    first_tp=""
+
+    for memmod in memList:
+        mem=memmod.inst
+        if "L1L2" in mem:
+            first_tp = "TP_L1L2A"
+
+    #If we did not find L1L2 assume L5L6 for reduced project
+    if first_tp == "" :
+        first_tp = "TP_L5L6A"
+
     for memmod in memList:
 
         nmem = 0
@@ -747,7 +758,7 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl
         if "MPAR" in mem and "in" not in mem:
             portlist += "        sync_nent => "+mem+"_start,\n"
         elif "AS" in mem and "n1" in mem and split == 1:
-            portlist += "        sync_nent => TP_L1L2A_start,\n"
+            portlist += "        sync_nent => "+first_tp+"_start,\n"
         elif "TPAR" in mem and split == 1:
             portlist += "        sync_nent => TP_done,\n" 
         else: