From d360074c3ff74dbaf0df6fe3b05f03c4993b2b45 Mon Sep 17 00:00:00 2001 From: Anders Ryd Date: Sat, 7 Dec 2024 17:32:08 -0500 Subject: [PATCH 01/14] Add new bodge files for AAAA and BBBB track builders - I think eventually we can remove these --- bodge/TF_AAAA_tb_writer.vhd.bodge | 15 +++++++++++++++ bodge/TF_BBBB_tb_writer.vhd.bodge | 15 +++++++++++++++ 2 files changed, 30 insertions(+) create mode 100644 bodge/TF_AAAA_tb_writer.vhd.bodge create mode 100644 bodge/TF_BBBB_tb_writer.vhd.bodge diff --git a/bodge/TF_AAAA_tb_writer.vhd.bodge b/bodge/TF_AAAA_tb_writer.vhd.bodge new file mode 100644 index 0000000..0e88c66 --- /dev/null +++ b/bodge/TF_AAAA_tb_writer.vhd.bodge @@ -0,0 +1,15 @@ + -- A bodge for TrackBuilder to write TF concatenated track+stub data for L1L2. + -- (Needed to compare with emData/). + writeTF_L1L2_484 : entity work.FileWriterFIFO + generic map ( + FILE_NAME => FILE_OUT_TF&"L1L2"&outputFileNameEnding, + FIFO_WIDTH => 484 + ) + port map ( + CLK => CLK, + DONE => FT_DONE, + WRITE_EN => (TW_L1L2_stream_A_write and TW_L1L2_stream_AV_din(103)), + FULL_NEG => TW_L1L2_stream_A_full_neg, + DATA => TW_L1L2_stream_AV_din&BW_L1L2_L3_stream_AV_din&BW_L1L2_L4_stream_AV_din&BW_L1L2_L5_stream_AV_din&BW_L1L2_L6_stream_AV_din&emptyDiskStub&emptyDiskStub&emptyDiskStub&emptyDiskStub + ); + diff --git a/bodge/TF_BBBB_tb_writer.vhd.bodge b/bodge/TF_BBBB_tb_writer.vhd.bodge new file mode 100644 index 0000000..0e88c66 --- /dev/null +++ b/bodge/TF_BBBB_tb_writer.vhd.bodge @@ -0,0 +1,15 @@ + -- A bodge for TrackBuilder to write TF concatenated track+stub data for L1L2. + -- (Needed to compare with emData/). + writeTF_L1L2_484 : entity work.FileWriterFIFO + generic map ( + FILE_NAME => FILE_OUT_TF&"L1L2"&outputFileNameEnding, + FIFO_WIDTH => 484 + ) + port map ( + CLK => CLK, + DONE => FT_DONE, + WRITE_EN => (TW_L1L2_stream_A_write and TW_L1L2_stream_AV_din(103)), + FULL_NEG => TW_L1L2_stream_A_full_neg, + DATA => TW_L1L2_stream_AV_din&BW_L1L2_L3_stream_AV_din&BW_L1L2_L4_stream_AV_din&BW_L1L2_L5_stream_AV_din&BW_L1L2_L6_stream_AV_din&emptyDiskStub&emptyDiskStub&emptyDiskStub&emptyDiskStub + ); + From 9c2713bdc10e56baf559e36bc27ac9468780bbea Mon Sep 17 00:00:00 2001 From: Anders Ryd Date: Sun, 8 Dec 2024 05:24:54 -0500 Subject: [PATCH 02/14] Remove the 'bodge' files as no longer needed --- TrackletGraph.py | 2 +- WriteVHDLSyntax.py | 8 ++++---- bodge/TF_AAAA_tb_writer.vhd.bodge | 15 --------------- bodge/TF_BBBB_tb_writer.vhd.bodge | 15 --------------- bodge/TF_D1D2_tb_writer.vhd.bodge | 16 ---------------- bodge/TF_D3D4_tb_writer.vhd.bodge | 15 --------------- bodge/TF_L1D1_tb_writer.vhd.bodge | 15 --------------- bodge/TF_L1L2_tb_writer.vhd.bodge | 15 --------------- bodge/TF_L2D1_tb_writer.vhd.bodge | 15 --------------- bodge/TF_L2L3_tb_writer.vhd.bodge | 15 --------------- bodge/TF_L3L4_tb_writer.vhd.bodge | 15 --------------- bodge/TF_L5L6_tb_writer.vhd.bodge | 15 --------------- generator_hdl.py | 32 +++++++++++++++++++------------ 13 files changed, 25 insertions(+), 168 deletions(-) delete mode 100644 bodge/TF_AAAA_tb_writer.vhd.bodge delete mode 100644 bodge/TF_BBBB_tb_writer.vhd.bodge delete mode 100644 bodge/TF_D1D2_tb_writer.vhd.bodge delete mode 100644 bodge/TF_D3D4_tb_writer.vhd.bodge delete mode 100644 bodge/TF_L1D1_tb_writer.vhd.bodge delete mode 100644 bodge/TF_L1L2_tb_writer.vhd.bodge delete mode 100644 bodge/TF_L2D1_tb_writer.vhd.bodge delete mode 100644 bodge/TF_L2L3_tb_writer.vhd.bodge delete mode 100644 bodge/TF_L3L4_tb_writer.vhd.bodge delete mode 100644 bodge/TF_L5L6_tb_writer.vhd.bodge diff --git a/TrackletGraph.py b/TrackletGraph.py index 4c6c212..738e88a 100644 --- a/TrackletGraph.py +++ b/TrackletGraph.py @@ -233,7 +233,7 @@ def populate_bitwidths(mem,hls_dir): # FIXME this information should be parsed f if barrelPS>-1 or barrel2S>-1: mem.bitwidth = 52 if disk>-1: mem.bitwidth = 55 elif mem.mtype == "TrackWord": - mem.bitwidth = 104 + mem.bitwidth = 113 elif mem.mtype == "BarrelStubWord": mem.bitwidth = 46 elif mem.mtype == "DiskStubWord": diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index 1d3df4a..4b22e53 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -825,7 +825,7 @@ def writeControlSignals_interface(initial_proc, final_procs, notfinal_procs, del string_ctrl_signals += " "+final_proc_short+"_bx_out : out std_logic_vector(2 downto 0);\n" string_ctrl_signals += " "+final_proc_short+"_bx_out_vld : out std_logic;\n" string_ctrl_signals += " "+final_proc_short+"_done : out std_logic;\n" - if final_proc_short == "FT": + if final_proc_short == "TB": for final_proc in final_procs: string_ctrl_signals += " "+final_proc+"_last_track : out std_logic;\n" string_ctrl_signals += " "+final_proc+"_last_track_vld : out std_logic;\n" @@ -1071,7 +1071,7 @@ def writeTBControlSignals(memDict, memInfoDict, initial_proc, final_procs, notfi string_ctrl_signals += (" signal "+final_procs[-1].mtype_short()+"_bx_out").ljust(str_len)+": std_logic_vector(2 downto 0) := (others => '1');\n" string_ctrl_signals += (" signal "+final_procs[-1].mtype_short()+"_bx_out_vld").ljust(str_len)+": std_logic := '0';\n" string_ctrl_signals += (" signal "+final_procs[-1].mtype_short()+"_done").ljust(str_len)+": std_logic := '0';\n" - if final_procs[-1].mtype_short().startswith("FT"): + if final_procs[-1].mtype_short().startswith("TB"): for final_proc in final_procs: string_ctrl_signals += (" signal "+final_proc.inst+"_last_track").ljust(str_len)+": std_logic := '0';\n" string_ctrl_signals += (" signal "+final_proc.inst+"_last_track_vld").ljust(str_len)+": std_logic := '0';\n" @@ -1219,7 +1219,7 @@ def writeFWBlockInstance(topfunc, memDict, memInfoDict, initial_proc, final_proc string_fwblock_inst += (" " + final_procs[-1].mtype_short() + "_bx_out").ljust(str_len) + "=> " + final_procs[-1].mtype_short() + "_bx_out,\n" string_fwblock_inst += (" " + final_procs[-1].mtype_short() + "_bx_out_vld").ljust(str_len) + "=> " + final_procs[-1].mtype_short() + "_bx_out_vld,\n" string_fwblock_inst += (" " + final_procs[-1].mtype_short() + "_done").ljust(str_len) + "=> " + final_procs[-1].mtype_short() + "_done,\n" - if final_procs[-1].mtype_short().startswith("FT"): + if final_procs[-1].mtype_short().startswith("TB"): for final_proc in final_procs : string_fwblock_inst += (" " + final_proc.inst + "_last_track").ljust(str_len) + "=> " + final_proc.inst + "_last_track,\n" string_fwblock_inst += (" " + final_proc.inst + "_last_track_vld").ljust(str_len) + "=> " + final_proc.inst + "_last_track_vld,\n" @@ -1643,7 +1643,7 @@ def writeProcBXPort(modName,isInput,isInitial,first_of_type,delay): else: if first_of_type and not ("VMSMER" in modName or "PC" in modName): bx_str += " bx_o_V => "+modName.split("_")[0]+"_bx_out,\n" - if ("FT_" in modName) or ("TP_" in modName): + if ("TB_" in modName) or ("TP_" in modName): bx_str += " bx_o_V_ap_vld => "+modName.split("_")[0]+"_bx_out_vld,\n" else: bx_str += " bx_o_V_ap_vld => open,\n" diff --git a/bodge/TF_AAAA_tb_writer.vhd.bodge b/bodge/TF_AAAA_tb_writer.vhd.bodge deleted file mode 100644 index 0e88c66..0000000 --- a/bodge/TF_AAAA_tb_writer.vhd.bodge +++ /dev/null @@ -1,15 +0,0 @@ - -- A bodge for TrackBuilder to write TF concatenated track+stub data for L1L2. - -- (Needed to compare with emData/). - writeTF_L1L2_484 : entity work.FileWriterFIFO - generic map ( - FILE_NAME => FILE_OUT_TF&"L1L2"&outputFileNameEnding, - FIFO_WIDTH => 484 - ) - port map ( - CLK => CLK, - DONE => FT_DONE, - WRITE_EN => (TW_L1L2_stream_A_write and TW_L1L2_stream_AV_din(103)), - FULL_NEG => TW_L1L2_stream_A_full_neg, - DATA => TW_L1L2_stream_AV_din&BW_L1L2_L3_stream_AV_din&BW_L1L2_L4_stream_AV_din&BW_L1L2_L5_stream_AV_din&BW_L1L2_L6_stream_AV_din&emptyDiskStub&emptyDiskStub&emptyDiskStub&emptyDiskStub - ); - diff --git a/bodge/TF_BBBB_tb_writer.vhd.bodge b/bodge/TF_BBBB_tb_writer.vhd.bodge deleted file mode 100644 index 0e88c66..0000000 --- a/bodge/TF_BBBB_tb_writer.vhd.bodge +++ /dev/null @@ -1,15 +0,0 @@ - -- A bodge for TrackBuilder to write TF concatenated track+stub data for L1L2. - -- (Needed to compare with emData/). - writeTF_L1L2_484 : entity work.FileWriterFIFO - generic map ( - FILE_NAME => FILE_OUT_TF&"L1L2"&outputFileNameEnding, - FIFO_WIDTH => 484 - ) - port map ( - CLK => CLK, - DONE => FT_DONE, - WRITE_EN => (TW_L1L2_stream_A_write and TW_L1L2_stream_AV_din(103)), - FULL_NEG => TW_L1L2_stream_A_full_neg, - DATA => TW_L1L2_stream_AV_din&BW_L1L2_L3_stream_AV_din&BW_L1L2_L4_stream_AV_din&BW_L1L2_L5_stream_AV_din&BW_L1L2_L6_stream_AV_din&emptyDiskStub&emptyDiskStub&emptyDiskStub&emptyDiskStub - ); - diff --git a/bodge/TF_D1D2_tb_writer.vhd.bodge b/bodge/TF_D1D2_tb_writer.vhd.bodge deleted file mode 100644 index bc24144..0000000 --- a/bodge/TF_D1D2_tb_writer.vhd.bodge +++ /dev/null @@ -1,16 +0,0 @@ - -- A bodge for TrackBuilder to write TF concatenated track+stub data for L1L2. - -- (Needed to compare with emData/). - writeTF_D1D2_297 : entity work.FileWriterFIFO - generic map ( - FILE_NAME => FILE_OUT_TF&memory_enum_to_string(D1D2)&outputFileNameEnding, - FIFO_WIDTH => 297 - ) - port map ( - CLK => CLK, - DONE => FT_DONE, - WRITE_EN => (TW_D1D2_stream_A_write and TW_D1D2_stream_AV_din(103)), - FULL_NEG => TW_D1D2_stream_A_full_neg, - --DATA => TW_D1D2_stream_AV_din&BW_D1D2_L1_stream_AV_din&BW_D1D2_D3_stream_AV_din&BW_D1D2_D4_stream_AV_din&BW_D1D2_D5_stream_AV_din - DATA => TW_D1D2_stream_AV_din&BW_D1D2_L1_stream_AV_din&emptyDiskStub&emptyDiskStub&emptyDiskStub - ); - diff --git a/bodge/TF_D3D4_tb_writer.vhd.bodge b/bodge/TF_D3D4_tb_writer.vhd.bodge deleted file mode 100644 index 57b27eb..0000000 --- a/bodge/TF_D3D4_tb_writer.vhd.bodge +++ /dev/null @@ -1,15 +0,0 @@ - -- A bodge for TrackBuilder to write TF concatenated track+stub data for L1L2. - -- (Needed to compare with emData/). - writeTF_D3D4_297 : entity work.FileWriterFIFO - generic map ( - FILE_NAME => FILE_OUT_TF&memory_enum_to_string(D3D4)&outputFileNameEnding, - FIFO_WIDTH => 297 - ) - port map ( - CLK => CLK, - DONE => FT_DONE, - WRITE_EN => (TW_D3D4_stream_A_write and TW_D3D4_stream_AV_din(103)), - FULL_NEG => TW_D3D4_stream_A_full_neg, - DATA => TW_D3D4_stream_AV_din&BW_D3D4_L1_stream_AV_din&emptyDiskStub&emptyDiskStub&emptyDiskStub - ); - diff --git a/bodge/TF_L1D1_tb_writer.vhd.bodge b/bodge/TF_L1D1_tb_writer.vhd.bodge deleted file mode 100644 index 2072b44..0000000 --- a/bodge/TF_L1D1_tb_writer.vhd.bodge +++ /dev/null @@ -1,15 +0,0 @@ - -- A bodge for TrackBuilder to write TF concatenated track+stub data for L1L2. - -- (Needed to compare with emData/). - writeTF_L1D1_300 : entity work.FileWriterFIFO - generic map ( - FILE_NAME => FILE_OUT_TF&memory_enum_to_string(L1D1)&outputFileNameEnding, - FIFO_WIDTH => 300 - ) - port map ( - CLK => CLK, - DONE => FT_DONE, - WRITE_EN => (TW_L1D1_stream_A_write and TW_L1D1_stream_AV_din(103)), - FULL_NEG => TW_L1D1_stream_A_full_neg, - DATA => TW_L1D1_stream_AV_din&emptyDiskStub&emptyDiskStub&emptyDiskStub&emptyDiskStub - ); - diff --git a/bodge/TF_L1L2_tb_writer.vhd.bodge b/bodge/TF_L1L2_tb_writer.vhd.bodge deleted file mode 100644 index 0e88c66..0000000 --- a/bodge/TF_L1L2_tb_writer.vhd.bodge +++ /dev/null @@ -1,15 +0,0 @@ - -- A bodge for TrackBuilder to write TF concatenated track+stub data for L1L2. - -- (Needed to compare with emData/). - writeTF_L1L2_484 : entity work.FileWriterFIFO - generic map ( - FILE_NAME => FILE_OUT_TF&"L1L2"&outputFileNameEnding, - FIFO_WIDTH => 484 - ) - port map ( - CLK => CLK, - DONE => FT_DONE, - WRITE_EN => (TW_L1L2_stream_A_write and TW_L1L2_stream_AV_din(103)), - FULL_NEG => TW_L1L2_stream_A_full_neg, - DATA => TW_L1L2_stream_AV_din&BW_L1L2_L3_stream_AV_din&BW_L1L2_L4_stream_AV_din&BW_L1L2_L5_stream_AV_din&BW_L1L2_L6_stream_AV_din&emptyDiskStub&emptyDiskStub&emptyDiskStub&emptyDiskStub - ); - diff --git a/bodge/TF_L2D1_tb_writer.vhd.bodge b/bodge/TF_L2D1_tb_writer.vhd.bodge deleted file mode 100644 index 5d07e40..0000000 --- a/bodge/TF_L2D1_tb_writer.vhd.bodge +++ /dev/null @@ -1,15 +0,0 @@ - -- A bodge for TrackBuilder to write TF concatenated track+stub data for L1L2. - -- (Needed to compare with emData/). - writeTF_L2D1_346 : entity work.FileWriterFIFO - generic map ( - FILE_NAME => FILE_OUT_TF&memory_enum_to_string(L2D1)&outputFileNameEnding, - FIFO_WIDTH => 346 - ) - port map ( - CLK => CLK, - DONE => FT_DONE, - WRITE_EN => (TW_L2D1_stream_A_write and TW_L2D1_stream_AV_din(103)), - FULL_NEG => TW_L2D1_stream_A_full_neg, - DATA => TW_L2D1_stream_AV_din&BW_L2D1_L1_stream_AV_din&emptyDiskStub&emptyDiskStub&emptyDiskStub&emptyDiskStub - ); - diff --git a/bodge/TF_L2L3_tb_writer.vhd.bodge b/bodge/TF_L2L3_tb_writer.vhd.bodge deleted file mode 100644 index 402b6e1..0000000 --- a/bodge/TF_L2L3_tb_writer.vhd.bodge +++ /dev/null @@ -1,15 +0,0 @@ - -- A bodge for TrackBuilder to write TF concatenated track+stub data for L2L3. - -- (Needed to compare with emData/). - writeTF_L2L3_438 : entity work.FileWriterFIFO - generic map ( - FILE_NAME => FILE_OUT_TF&"L2L3"&outputFileNameEnding, - FIFO_WIDTH => 438 - ) - port map ( - CLK => CLK, - DONE => FT_DONE, - WRITE_EN => (TW_L2L3_stream_A_write and TW_L2L3_stream_AV_din(103)), - FULL_NEG => TW_L2L3_stream_A_full_neg, - DATA => TW_L2L3_stream_AV_din&BW_L2L3_L1_stream_AV_din&BW_L2L3_L4_stream_AV_din&BW_L2L3_L5_stream_AV_din&emptyDiskStub&emptyDiskStub&emptyDiskStub&emptyDiskStub - ); - diff --git a/bodge/TF_L3L4_tb_writer.vhd.bodge b/bodge/TF_L3L4_tb_writer.vhd.bodge deleted file mode 100644 index c3b994b..0000000 --- a/bodge/TF_L3L4_tb_writer.vhd.bodge +++ /dev/null @@ -1,15 +0,0 @@ - -- A bodge for TrackBuilder to write TF concatenated track+stub data for L3L4. - -- (Needed to compare with emData/). - writeTF_L3L4_386 : entity work.FileWriterFIFO - generic map ( - FILE_NAME => FILE_OUT_TF&"L3L4"&outputFileNameEnding, - FIFO_WIDTH => 386 - ) - port map ( - CLK => CLK, - DONE => FT_DONE, - WRITE_EN => (TW_L3L4_stream_A_write and TW_L3L4_stream_AV_din(103)), - FULL_NEG => TW_L3L4_stream_A_full_neg, - DATA => TW_L3L4_stream_AV_din&BW_L3L4_L1_stream_AV_din&BW_L3L4_L2_stream_AV_din&BW_L3L4_L5_stream_AV_din&BW_L3L4_L6_stream_AV_din&emptyDiskStub&emptyDiskStub - ); - diff --git a/bodge/TF_L5L6_tb_writer.vhd.bodge b/bodge/TF_L5L6_tb_writer.vhd.bodge deleted file mode 100644 index 5196fa0..0000000 --- a/bodge/TF_L5L6_tb_writer.vhd.bodge +++ /dev/null @@ -1,15 +0,0 @@ - -- A bodge for TrackBuilder to write TF concatenated track+stub data for L5L6. - -- (Needed to compare with emData/). - writeTF_L5L6_288 : entity work.FileWriterFIFO - generic map ( - FILE_NAME => FILE_OUT_TF&"L5L6"&outputFileNameEnding, - FIFO_WIDTH => 288 - ) - port map ( - CLK => CLK, - DONE => FT_DONE, - WRITE_EN => (TW_L5L6_stream_A_write and TW_L5L6_stream_AV_din(103)), - FULL_NEG => TW_L5L6_stream_A_full_neg, - DATA => TW_L5L6_stream_AV_din&BW_L5L6_L1_stream_AV_din&BW_L5L6_L2_stream_AV_din&BW_L5L6_L3_stream_AV_din&BW_L5L6_L4_stream_AV_din - ); - diff --git a/generator_hdl.py b/generator_hdl.py index 66ee73b..42d93a9 100755 --- a/generator_hdl.py +++ b/generator_hdl.py @@ -290,16 +290,27 @@ def writeTBMemoryWrites(memDict, memInfoDict, notfinal_procs,split, MPARdict): if memInfo.isFIFO: string_tmp = writeTBMemoryWriteFIFOInstance(mtypeB, memDict, proc) - # A bodge for TrackBuilder to write TF concatenated track+stub data. + # Code for TrackBuilder to write TF concatenated track+stub data. # (Needed to compare with emData/). - if mtypeB == 'TW_104': + if mtypeB == 'TW_113': for m in memDict[mtypeB]: memName = m.inst seed = memName[-4:] - fileTF = open("bodge/TF_" + seed + "_tb_writer.vhd.bodge") - string_tmp += fileTF.read(); - fileTF.close() - + string_tmp += "-- Clode for TrackBuilder to write TF concatenated track+stub data.\n"; + string_tmp += "-- (Needed to compare with emData/).\n"; + string_tmp += "writeTF_"+seed+"_634 : entity work.FileWriterFIFO\n"; + string_tmp += "generic map (\n"; + string_tmp += " FILE_NAME => FILE_OUT_TF&\""+seed+"\"&outputFileNameEnding,\n"; + string_tmp += " FIFO_WIDTH => 634\n"; + string_tmp += ")\n"; + string_tmp += "port map (\n"; + string_tmp += " CLK => CLK,\n" + string_tmp += " DONE => TB_DONE,\n"; + string_tmp += " WRITE_EN => (TW_"+seed+"_stream_A_write and TW_"+seed+"_stream_AV_din(112)),\n"; + string_tmp += " FULL_NEG => TW_"+seed+"_stream_A_full_neg,\n"; + string_tmp += " DATA => TW_"+seed+"_stream_AV_din&BW_"+seed+"_L1_stream_AV_din&BW_"+seed+"_L2_stream_AV_din&BW_"+seed+"_L3_stream_AV_din&BW_"+seed+"_L4_stream_AV_din&BW_"+seed+"_L5_stream_AV_din&BW_"+seed+"_L6_stream_AV_din&DW_"+seed+"_D1_stream_AV_din&DW_"+seed+"_D2_stream_AV_din&DW_"+seed+"_D3_stream_AV_din&DW_"+seed+"_D4_stream_AV_din&DW_"+seed+"_D5_stream_AV_din\n"; + string_tmp += ");\n"; + if memInfo.is_final: if memInfo.isFIFO: string_final += string_tmp @@ -355,12 +366,9 @@ def writeTestBench(tbfunc, topfunc, process_list, memDict, memInfoDict, memPrint string_header += writeTBOpener(tbfunc) string_constants = writeTBConstants(memDict, memInfoDict, notfinal_procs+[final_procs[-1].mtype_short()], memPrintsDir, sector, split) - # A bodge for TrackBuilder to write TF concatenated track+stub data. - # (Needed to compare with emData/). - if 'TW_104' in memInfoDict.keys(): - fileTF = open("bodge/TF_tb_constants.vhd.bodge") - string_constants += fileTF.read(); - + if 'TW_113' in memInfoDict.keys(): + string_constants += 'constant FILE_OUT_TF : string := dataOutDir&"TF_";'; + string_ctrl_signals = writeTBControlSignals(memDict, memInfoDict, initial_proc, final_procs, notfinal_procs,split, MPARdict) string_begin = writeTBEntityBegin() From 5a08387f246fb11ddbd7845d1601c2596411303b Mon Sep 17 00:00:00 2001 From: Anders Ryd Date: Sun, 8 Dec 2024 05:25:52 -0500 Subject: [PATCH 03/14] Remove the 'bodge' files as no longer needed --- bodge/TF_tb_constants.vhd.bodge | 6 ------ 1 file changed, 6 deletions(-) delete mode 100644 bodge/TF_tb_constants.vhd.bodge diff --git a/bodge/TF_tb_constants.vhd.bodge b/bodge/TF_tb_constants.vhd.bodge deleted file mode 100644 index 14c8155..0000000 --- a/bodge/TF_tb_constants.vhd.bodge +++ /dev/null @@ -1,6 +0,0 @@ - -- A bodge for TrackBuilder to write TF concatenated track+stub data. - -- (Needed to compare with emData/). - constant FILE_OUT_TF : string := dataOutDir&"TF_"; - -- Empty field in the output from barrel-only TrackBuilders corresponding to - -- disk matches - constant emptyDiskStub : std_logic_vector(48 downto 0) := (others => '0'); From bba0f12e54d4dc44d258bf6809022d8527dcd939 Mon Sep 17 00:00:00 2001 From: Anders Ryd Date: Sat, 14 Dec 2024 07:58:13 -0500 Subject: [PATCH 04/14] Minor logic fix in string parsing --- TrackletGraph.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/TrackletGraph.py b/TrackletGraph.py index 738e88a..28db3dc 100644 --- a/TrackletGraph.py +++ b/TrackletGraph.py @@ -504,7 +504,7 @@ def split_track_fit_streams(p_dict, m_dict): for up_m in up_p.upstreams: if up_m.mtype != "FullMatch": continue - layer = up_m.inst.split("_")[-1][0:2] + layer = up_m.inst.split("_")[2][0:2] assert(layer.startswith("L") or layer.startswith("D")) layers.add(layer) From 7cfb7e0d6a2bfc2bf211baa36732dc4f75a56d7e Mon Sep 17 00:00:00 2001 From: Anders Ryd Date: Tue, 28 Jan 2025 18:09:44 -0500 Subject: [PATCH 05/14] Changes so that each trackword has all layers --- TrackletGraph.py | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/TrackletGraph.py b/TrackletGraph.py index 28db3dc..948c809 100644 --- a/TrackletGraph.py +++ b/TrackletGraph.py @@ -497,16 +497,8 @@ def split_track_fit_streams(p_dict, m_dict): down_p.upstreams.append(new_mem) down_p.input_port_names.append("trackwordin") - # Determine the layers/disks from the associated full match - # memories. - layers = set() - if up_p is not None: - for up_m in up_p.upstreams: - if up_m.mtype != "FullMatch": - continue - layer = up_m.inst.split("_")[2][0:2] - assert(layer.startswith("L") or layer.startswith("D")) - layers.add(layer) + # We will have all layers now for each TrackWord + layers = {'L6', 'D5', 'L4', 'D2', 'D1', 'L2', 'L5', 'L1', 'L3', 'D4', 'D3'} # Replace the old memory with a stub word for each of the # layers/disks that can have matches. From 03d0072f689bee960579c413e5fc81df812d2595 Mon Sep 17 00:00:00 2001 From: Anders Ryd Date: Tue, 28 Jan 2025 18:16:03 -0500 Subject: [PATCH 06/14] Changes so that each trackword has all layers --- TrackletGraph.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/TrackletGraph.py b/TrackletGraph.py index 948c809..afcc5f1 100644 --- a/TrackletGraph.py +++ b/TrackletGraph.py @@ -497,7 +497,7 @@ def split_track_fit_streams(p_dict, m_dict): down_p.upstreams.append(new_mem) down_p.input_port_names.append("trackwordin") - # We will have all layers now for each TrackWord + # We will have all layers for each TrackWord layers = {'L6', 'D5', 'L4', 'D2', 'D1', 'L2', 'L5', 'L1', 'L3', 'D4', 'D3'} # Replace the old memory with a stub word for each of the From a47e0a6881a9f2b014f25e708fbdd84806d7ba5d Mon Sep 17 00:00:00 2001 From: Anders Ryd Date: Mon, 10 Feb 2025 10:19:37 -0500 Subject: [PATCH 07/14] Updates for new bin mask interface in VMStub memories --- WriteVHDLSyntax.py | 64 ++++++++++++++++++++++++---------------------- 1 file changed, 34 insertions(+), 30 deletions(-) diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index 4b22e53..a8b67bf 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -346,6 +346,15 @@ def writeMemoryUtil(memDict, memInfoDict): tName = "t_"+mtypeB+"_NENTADDRDISK" nentaddrbits = "4" ss += " subtype "+tName+" is std_logic_vector("+nentaddrbits+" downto 0);\n" + #FIXME - hardcoded number + tName = "t_"+mtypeB+"_ADDRBINMASK" + ss += " subtype "+tName+" is std_logic_vector(3 downto 0);\n" + tName = "t_"+mtypeB+"_ADDRBINMASKDISK" + ss += " subtype "+tName+" is std_logic_vector(4 downto 0);\n" + tName = "t_"+mtypeB+"_BINMASK" + ss += " subtype "+tName+" is std_logic_vector(7 downto 0);\n" + tName = "t_"+mtypeB+"_BINMASKDISK" + ss += " subtype "+tName+" is std_logic_vector(7 downto 0);\n" else: #FIXME tpages = 1 @@ -544,6 +553,18 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl wirelist += "t_"+mtypeB+"_DATA_"+str(nmem)+";\n" wirelist += " signal "+mem+"_V_masktmp : " wirelist += "t_"+mtypeB+"_MASK"+disk+"_"+str(num_pages)+";\n" + wirelist += " signal "+mem+"_V_addr_binmaskA : " + wirelist += "t_"+mtypeB+"_ADDRBINMASK"+disk+";\n" + wirelist += " signal "+mem+"_V_binmaskA : " + wirelist += "t_"+mtypeB+"_BINMASK"+disk+";\n" + wirelist += " signal "+mem+"_enb_binmaskA : " + wirelist += "t_"+mtypeB+"_1b;\n" + wirelist += " signal "+mem+"_V_addr_binmaskB : " + wirelist += "t_"+mtypeB+"_ADDRBINMASK"+disk+";\n" + wirelist += " signal "+mem+"_V_binmaskB : " + wirelist += "t_"+mtypeB+"_BINMASK"+disk+";\n" + wirelist += " signal "+mem+"_enb_binmaskB : " + wirelist += "t_"+mtypeB+"_1b;\n" else: wirelist += " signal "+mem+"_AV_dout_nent : " wirelist += "t_"+mtypeB+"_NENT; -- (#page)\n" @@ -746,7 +767,12 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl portlist += " enb_nent => "+mem+"_enb_nent,\n" portlist += " addr_nent => "+mem+"_V_addr_nent,\n" portlist += " dout_nent => "+mem+"_AV_dout_nent,\n" - portlist += " mask_o => "+mem+"_V_masktmp,\n" + portlist += " enb_binmaska => "+mem+"_enb_binmaska,\n" + portlist += " addr_binmaska => "+mem+"_V_addr_binmaska,\n" + portlist += " binmaska_o => "+mem+"_V_binmaska,\n" + portlist += " enb_binmaskb => "+mem+"_enb_binmaskb,\n" + portlist += " addr_binmaskb => "+mem+"_V_addr_binmaskb,\n" + portlist += " binmaskb_o => "+mem+"_V_binmaskb,\n" else: portlist += " nent_o => "+mem+"_AV_dout_nent,\n" if "MPROJ" in mem: @@ -768,18 +794,6 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl else: mem_str += " dataout"+str(i)+" => "+mem+"_AV_dout("+str(i)+")\n" mem_str += " );\n\n" - disk = "" - if "VMSME_D" in mem: - disk = "DISK" - mem_str += " "+mem+"_maskformat : entity work.vmstub"+str(nbx)+"mask"+disk+"\n" - mem_str += " port map (\n" - mem_str += " datain => "+mem+"_V_masktmp,\n" - for i in range(0, nbx) : - if i < nbx-1 : - mem_str += " dataout"+str(i)+" => "+mem+"_AV_dout_mask("+str(i)+"),\n" - else: - mem_str += " dataout"+str(i)+" => "+mem+"_AV_dout_mask("+str(i)+")\n" - mem_str += " );\n\n" mem_str += " "+mem+" : entity work.tf_mem_bin\n" else: if "MPROJ" in mem: @@ -916,7 +930,6 @@ def writeMemoryRHSPorts_interface(mtypeB, memInfo, memDict, split, MPARdict = 0) string_output_mems += " "+mem+"_A_enb : in t_"+mtypeB+"_A1b;\n" string_output_mems += " "+mem+"_AV_readaddr : in t_"+mtypeB+"_AADDR"+disk+";\n" string_output_mems += " "+mem+"_AV_dout : out t_"+mtypeB+"_ADATA;\n" - string_output_mems += " "+mem+"_AV_dout_mask : out t_"+mtypeB+"_MASK"+disk+";\n" string_output_mems += " "+mem+"_enb_nent : out t_"+mtypeB+"_1b;\n" string_output_mems += " "+mem+"_V_addr_nent : out t_"+mtypeB+"_NENTADDR"+disk+";\n" string_output_mems += " "+mem+"_AV_dout_nent : out t_"+mtypeB+"_NENT;\n" @@ -937,8 +950,6 @@ def writeMemoryRHSPorts_interface(mtypeB, memInfo, memDict, split, MPARdict = 0) if memInfo.is_binned: string_output_mems += " "+mem+"_AV_dout_nent : " string_output_mems += "out t_"+mtypeB+"_NENT;\n" - string_output_mems += " "+mem+"_AV_dout_mask : " - string_output_mems += "out t_"+mtypeB+"_MASK;\n" else: string_output_mems += " "+mem+"_AV_dout_nent : " string_output_mems += "out t_"+mtypeB+"_NENT;\n" @@ -1138,8 +1149,6 @@ def writeTBControlSignals(memDict, memInfoDict, initial_proc, final_procs, notfi string_ctrl_signals += ("t_"+mtypeB+"_ADATA").ljust(str_len2)+":= (others => (others => '0'));\n" string_ctrl_signals += (" signal "+mem+"_AAV_dout_nent").ljust(str_len)+": " string_ctrl_signals += ("t_"+mtypeB+"_NENT").ljust(str_len2)+":= (others => '0'); -- (#page)(#bin)\n" - string_ctrl_signals += (" signal "+mem+"_AV_dout_mask").ljust(str_len)+": " - string_ctrl_signals += ("t_"+mtypeB+"_MASK").ljust(str_len2)+":= (others => (others => '0')); -- (#page)(#bin)\n" elif split == 1 and "TPAR" in mem: seed = mem.split("_")[1][:-1] itc = mem.split("_")[1][-1] @@ -1271,7 +1280,7 @@ def writeFWBlockInstance(topfunc, memDict, memInfoDict, initial_proc, final_proc string_output += (" "+mem+"_A_enb").ljust(str_len) + "=> "+mem+"_enb,\n" string_output += (" "+mem+"_AV_readaddr").ljust(str_len) + "=> "+mem+"_readaddr,\n" string_output += (" "+mem+"_AV_dout").ljust(str_len) + "=> "+mem+"_dout,\n" - string_output += (" "+mem+"_AV_dout_mask").ljust(str_len) + "=> open,\n" #FIXME + #string_output += (" "+mem+"_AV_dout_mask").ljust(str_len) + "=> open,\n" #FIXME string_output += (" "+mem+"_enb_nent").ljust(str_len) + "=> open,\n" string_output += (" "+mem+"_V_addr_nent").ljust(str_len) + "=> open,\n" string_output += (" "+mem+"_AV_dout_nent").ljust(str_len) + "=> open,\n" @@ -1735,17 +1744,12 @@ def writeProcMemoryRHSPorts(argname,mem,portindex=0, split = 0): string_mem_ports += " "+argname+"_nentries_V_ce0 => "+mem.mtype_short()+"_"+mem.var()+"_enb_nent,\n" string_mem_ports += " "+argname+"_nentries_V_address0 => "+mem.mtype_short()+"_"+mem.var()+"_V_addr_nent,\n" string_mem_ports += " "+argname+"_nentries_V_q0 => "+mem.mtype_short()+"_"+mem.var()+"_AV_dout_nent,\n" - for i in range(0,2**mem.bxbitwidth): - nrz = 8 - if mem.var()[0] == "D" and split == 2: - nrz = 16 - for j in range(0,nrz): - string_mem_ports += " "+argname+"_binmask8_"+str(i)+"_V_"+str(j)+" => (" - for k in range(0,8): - if k != 0 : - string_mem_ports += ", " - string_mem_ports += mem.mtype_short()+"_"+mem.var()+"_AV_dout_mask("+str(i)+")("+str((j+1)*8-k-1)+")" - string_mem_ports += "),\n" + string_mem_ports += " "+argname+"_binmaskA_V_address0 => "+mem.mtype_short()+"_"+mem.var()+"_V_addr_binmaskA,\n" + string_mem_ports += " "+argname+"_binmaskA_V_ce0 => "+mem.mtype_short()+"_"+mem.var()+"_enb_binmaskA,\n" + string_mem_ports += " "+argname+"_binmaskA_V_q0 => "+mem.mtype_short()+"_"+mem.var()+"_V_binmaskA,\n" + string_mem_ports += " "+argname+"_binmaskB_V_address0 => "+mem.mtype_short()+"_"+mem.var()+"_V_addr_binmaskB,\n" + string_mem_ports += " "+argname+"_binmaskB_V_ce0 => "+mem.mtype_short()+"_"+mem.var()+"_enb_binmaskB,\n" + string_mem_ports += " "+argname+"_binmaskB_V_q0 => "+mem.mtype_short()+"_"+mem.var()+"_V_binmaskB,\n" else: tpage = 1 if "MPROJ" in mem.mtype_short() : From f6a2805d6ac8bc5948d2482a822d1dfb7151c0b0 Mon Sep 17 00:00:00 2001 From: Anders Ryd Date: Wed, 12 Feb 2025 12:43:41 -0500 Subject: [PATCH 08/14] Fix review comments to remove some hardcoded values --- generator_hdl.py | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/generator_hdl.py b/generator_hdl.py index 42d93a9..1a11858 100755 --- a/generator_hdl.py +++ b/generator_hdl.py @@ -292,21 +292,30 @@ def writeTBMemoryWrites(memDict, memInfoDict, notfinal_procs,split, MPARdict): string_tmp = writeTBMemoryWriteFIFOInstance(mtypeB, memDict, proc) # Code for TrackBuilder to write TF concatenated track+stub data. # (Needed to compare with emData/). - if mtypeB == 'TW_113': + if mtypeB.startswith('TW_'): for m in memDict[mtypeB]: memName = m.inst seed = memName[-4:] - string_tmp += "-- Clode for TrackBuilder to write TF concatenated track+stub data.\n"; + bw_keys = [key for key in memDict if key.startswith('BW_')] + bw_width = memDict[bw_keys[0]][0].bitwidth if len(bw_keys) > 0 else 0 + n_bw = len(memDict[bw_keys[0]]) if len(bw_keys) > 0 else 0 + dw_keys = [key for key in memDict if key.startswith('DW_')] + dw_width = memDict[dw_keys[0]][0].bitwidth if len(dw_keys) > 0 else 0 + n_dw = len(memDict[dw_keys[0]]) if len(dw_keys) > 0 else 0 + # Calculate total width of track word plus stub words + total_width = str(m.bitwidth + n_bw * bw_width + n_dw * dw_width) + + string_tmp += "-- Code for TrackBuilder to write TF concatenated track+stub data.\n"; string_tmp += "-- (Needed to compare with emData/).\n"; - string_tmp += "writeTF_"+seed+"_634 : entity work.FileWriterFIFO\n"; + string_tmp += "writeTF_"+seed+"_" + total_width + " : entity work.FileWriterFIFO\n"; string_tmp += "generic map (\n"; string_tmp += " FILE_NAME => FILE_OUT_TF&\""+seed+"\"&outputFileNameEnding,\n"; - string_tmp += " FIFO_WIDTH => 634\n"; + string_tmp += " FIFO_WIDTH => " + total_width + "\n"; string_tmp += ")\n"; string_tmp += "port map (\n"; string_tmp += " CLK => CLK,\n" string_tmp += " DONE => TB_DONE,\n"; - string_tmp += " WRITE_EN => (TW_"+seed+"_stream_A_write and TW_"+seed+"_stream_AV_din(112)),\n"; + string_tmp += " WRITE_EN => (TW_"+seed+"_stream_A_write and TW_"+seed+"_stream_AV_din("+str(m.bitwidth-1)+")),\n"; string_tmp += " FULL_NEG => TW_"+seed+"_stream_A_full_neg,\n"; string_tmp += " DATA => TW_"+seed+"_stream_AV_din&BW_"+seed+"_L1_stream_AV_din&BW_"+seed+"_L2_stream_AV_din&BW_"+seed+"_L3_stream_AV_din&BW_"+seed+"_L4_stream_AV_din&BW_"+seed+"_L5_stream_AV_din&BW_"+seed+"_L6_stream_AV_din&DW_"+seed+"_D1_stream_AV_din&DW_"+seed+"_D2_stream_AV_din&DW_"+seed+"_D3_stream_AV_din&DW_"+seed+"_D4_stream_AV_din&DW_"+seed+"_D5_stream_AV_din\n"; string_tmp += ");\n"; @@ -366,7 +375,7 @@ def writeTestBench(tbfunc, topfunc, process_list, memDict, memInfoDict, memPrint string_header += writeTBOpener(tbfunc) string_constants = writeTBConstants(memDict, memInfoDict, notfinal_procs+[final_procs[-1].mtype_short()], memPrintsDir, sector, split) - if 'TW_113' in memInfoDict.keys(): + if len([key for key in memInfoDict if key.startswith('TW_')]) > 0: string_constants += 'constant FILE_OUT_TF : string := dataOutDir&"TF_";'; string_ctrl_signals = writeTBControlSignals(memDict, memInfoDict, initial_proc, final_procs, notfinal_procs,split, MPARdict) From 8d21feacbae0e28f50302be75a15a2ec8e84d1a0 Mon Sep 17 00:00:00 2001 From: Anders Ryd Date: Mon, 24 Feb 2025 22:31:33 -0500 Subject: [PATCH 09/14] Updates in WriteVHDLSyntax to write correct memory page size for the TPROJ and TPAR memories --- WriteVHDLSyntax.py | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index a8b67bf..2086987 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -202,6 +202,8 @@ def writeTBMemoryReadInstance(mtypeB, memDict, bxbitwidth, is_initial, is_binned memtmp = memtmp.replace("n1","") # memtmp = "T"+mem[1:10] string_mem += " FILE_NAME".ljust(str_len) + "=> FILE_IN_" + mtypeB+"&\""+ memtmp + "\"&inputFileNameEnding,\n" + if "MPAR" in mem: + string_mem += " PAGE_LENGTH".ljust(str_len) + "=> 128,\n" string_mem += " DELAY".ljust(str_len) + "=> " + mtypeB.split("_")[0] + "_DELAY*MAX_ENTRIES,\n" string_mem += " RAM_WIDTH".ljust(str_len) + "=> " + mtypeB.split("_")[1] + ",\n" string_mem += " NUM_PAGES".ljust(str_len) + "=> " + str(2**bxbitwidth) + ",\n" @@ -317,6 +319,7 @@ def writeMemoryUtil(memDict, memInfoDict): if "MPAR" in mtypeB: tName = "t_"+mtypeB+"_ADDR" ss += " subtype "+tName+" is std_logic_vector("+str(8+memInfo.bxbitwidth)+" downto 0);\n" + #ss += " subtype "+tName+" is std_logic_vector("+str(7+memInfo.bxbitwidth)+" downto 0);\n" elif "MPROJ" in mtypeB: tName = "t_"+mtypeB+"_ADDR" ss += " subtype "+tName+" is std_logic_vector("+str(7+memInfo.bxbitwidth)+" downto 0);\n" @@ -584,8 +587,10 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl # Write parameters parameterlist += " RAM_WIDTH => "+bitwidth+",\n" parameterlist += " NUM_PAGES => "+str(num_pages)+",\n" - if "MPROJ" in mem: + if "MPROJ" in mem : parameterlist += " PAGE_LENGTH => 64,\n" + if "MPAR" in mem: + parameterlist += " PAGE_LENGTH => 128,\n" if "MPROJ" in mem or "MPAR" in mem: parameterlist += " NUM_TPAGES => 4,\n" parameterlist += " INIT_FILE => \"\",\n" @@ -1369,7 +1374,7 @@ def writeTBMemoryWriteInstance(mtypeB, memList, proc, proc_up, bxbitwidth, is_bi string_mem += " ADDR".ljust(str_len)+"=> "+mem+"_writeaddr,\n" string_mem += " DATA".ljust(str_len)+"=> "+mem+"_din,\n" string_mem += " WRITE_EN".ljust(str_len)+"=> "+mem+"_wea,\n" - if proc == "VMSMER" : + if proc == "VMSMER" or proc == "PC": string_mem += " START".ljust(str_len)+"=> PC_START,\n" else: string_mem += " START".ljust(str_len)+"=> "+(proc+"_START,\n" if not proc_up else proc_up+"_DONE,\n") @@ -1489,6 +1494,7 @@ def writeProcCombination(module, str_ctrl_func, str_ports): if "PC_" in module.inst: module_str += " " + module.inst + "_mem_reader : entity work.mem_reader\n" module_str += " generic map (\n" + module_str += " PAGE_LENGTH => 128,\n" module_str += " RAM_WIDTH => " + str(module.upstreams[0].bitwidth) + ",\n" module_str += " NUM_TPAGES => 4,\n" module_str += " NAME => \""+module.inst+"_mem_reader\"\n" From 4ac45bcc128f16c8db80e65d6c03c53eed706276 Mon Sep 17 00:00:00 2001 From: Anders Ryd Date: Sun, 2 Mar 2025 10:24:29 -0500 Subject: [PATCH 10/14] Various fixes for BX alignment to get agreement for reduced project with emulation --- WriteVHDLSyntax.py | 80 ++++++++++++++++++++++++---------------------- 1 file changed, 42 insertions(+), 38 deletions(-) diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index 2086987..0ee5ae0 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -132,7 +132,7 @@ def writeTBMemoryStimulusProcess(initial_proc): string_mem += " -- Process to start first module in chain & generate its BX counter input.\n" string_mem += " -- Also releases reset flag.\n" string_mem += " constant CLK_RESET : natural := 5; -- Any low number OK.\n" - string_mem += " variable CLK_COUNT : natural := 1;\n" if "IR" not in initial_proc else " variable CLK_COUNT : natural := MAX_ENTRIES - CLK_RESET;\n" + string_mem += " variable CLK_COUNT : natural := 4; -- Magic adjustment (ryd)\n" if "IR" not in initial_proc else " variable CLK_COUNT : natural := MAX_ENTRIES - CLK_RESET;\n" string_mem += " variable EVENT_COUNT : integer := -1;\n" string_mem += " variable v_line : line; -- Line for debug\n" string_mem += " begin\n\n" @@ -480,9 +480,8 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl merge_portlist = "" # Write wires if delay > 0: - if not memInfo.is_binned: - wirelist += " signal "+mem+"_bx : " - wirelist += "std_logic_vector(2 downto 0);\n" + wirelist += " signal "+mem+"_bx : " + wirelist += "std_logic_vector(2 downto 0);\n" wirelist += " signal "+mem+"_start : " wirelist += "std_logic;\n" wirelist += " signal "+mem+"_wea_delay_0 : " @@ -598,7 +597,10 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl parameterlist += " RAM_PERFORMANCE => \"HIGH_PERFORMANCE\",\n" parameterlist += " NAME => \""+mem+"\",\n" if delay > 0: - delay2_parameterlist +=" DELAY => " + str(delay*2) +",\n" + if "in" in mem : + delay2_parameterlist +=" DELAY => " + str(2+delay*2) +",\n" + else: + delay2_parameterlist +=" DELAY => " + str(delay*2) +",\n" delay_parameterlist +=" DELAY => " + str(delay) +",\n" delay_parameterlist_0 +=" DELAY => " + str(delay+1) +",\n" #enable to use non-default delay value @@ -665,6 +667,8 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl else: delay2_portlist += " done => "+memmod.upstreams[0].mtype_short()+"_done,\n" delay2_portlist += " bx_out => "+memmod.upstreams[0].mtype_short()+"_bx_out,\n" + else: + delay2_portlist += " done => PC_start,\n" delay2_portlist += " bx => "+mem+"_bx,\n" delay2_portlist += " start => "+mem+"_start,\n" delay_portlist_0 += " clk => clk,\n" @@ -743,16 +747,14 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl portlist += " enb => "+mem+"_enb,\n" portlist += " addrb => "+mem+"_V_readaddr,\n" portlist += " doutb => "+mem+"_V_dout,\n" - if ("AS" in mem or "MPAR" in mem) and "in" in mem: - portlist += " sync_nent => PC_start,\n" - elif "MPAR" in mem and "in" not in mem: + if "MPAR" in mem and "in" not in mem: portlist += " sync_nent => "+mem+"_start,\n" elif "AS" in mem and "n1" in mem and split == 1: portlist += " sync_nent => TP_L1L2A_start,\n" elif "TPAR" in mem and split == 1: portlist += " sync_nent => TP_done,\n" else: - portlist += " sync_nent => "+sync_signal+",\n" + portlist += " sync_nent => "+mem+"_start,\n" if memmod.has_numEntries_out or ("n1" in mem and split == 1): if memList[0].is_binned: ncopy = getVMStubNCopy(memmod); @@ -810,10 +812,9 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl mem_str += " generic map (\n"+parameterlist.rstrip(",\n")+"\n )\n" mem_str += " port map (\n"+portlist.rstrip(",\n")+"\n );\n\n" if delay > 0: - if not memInfo.is_binned and not "in" in mem and not "AS_" in mem: - mem_str += " "+mem+"_BX_GEN : entity work.CreateStartSignal\n" - mem_str += " generic map (\n"+delay2_parameterlist.rstrip(",\n")+"\n )\n" - mem_str += " port map (\n"+delay2_portlist.rstrip(",\n")+"\n );\n\n" + mem_str += " "+mem+"_BX_GEN : entity work.CreateStartSignal\n" + mem_str += " generic map (\n"+delay2_parameterlist.rstrip(",\n")+"\n )\n" + mem_str += " port map (\n"+delay2_portlist.rstrip(",\n")+"\n );\n\n" mem_str += " "+mem+"_DELAY : entity work.tf_pipe_delay\n" mem_str += " generic map (\n"+delay_parameterlist.rstrip(",\n")+"\n )\n" mem_str += " port map (\n"+delay_portlist.rstrip(",\n")+"\n );\n\n" @@ -1364,6 +1365,8 @@ def writeTBMemoryWriteInstance(mtypeB, memList, proc, proc_up, bxbitwidth, is_bi string_mem += " PAGE_LENGTH".ljust(str_len)+"=> 2048,\n" else: string_mem += " PAGE_LENGTH".ljust(str_len)+"=> 1024,\n" + if "VMSME" in mem: + string_mem += " CLK_CNT_INIT".ljust(str_len)+"=> -17,\n" #-17 is emperically determined to allign the FileWriter BX with the data stream if "MPROJ" in mem : string_mem += " NUM_TPAGES".ljust(str_len)+"=> 4,\n" string_mem += " PAGE_LENGTH".ljust(str_len)+"=> 64,\n" @@ -1567,7 +1570,7 @@ def writeStartSwitchAndInternalBX(module,mem,extraports=False, delay = 0, first_ if "PC_" in mtype and first_of_type : int_ctrl_func += " LATCH_PC_VMSMER: entity work.CreateStartSignal\n" - startsignal_parameter_list = " DELAY => " + str(110) +",\n" + startsignal_parameter_list = " DELAY => " + str(123) +",\n" int_ctrl_func += " generic map (\n"+startsignal_parameter_list.rstrip(",\n")+"\n )\n" int_ctrl_func += " port map (\n" @@ -1588,31 +1591,32 @@ def writeStartSwitchAndInternalBX(module,mem,extraports=False, delay = 0, first_ int_ctrl_wire += " signal "+mtype_up+"_done : std_logic := '0';\n" int_ctrl_wire += " signal "+mtype_up+"_bx_out : std_logic_vector(2 downto 0);\n" int_ctrl_wire += " signal "+mtype_up+"_bx_out_vld : std_logic;\n" - int_ctrl_wire += " signal "+mtype+"_bx_in : std_logic_vector(2 downto 0);\n" - int_ctrl_wire += " signal "+mtype+"_start : std_logic := '0';\n" - int_ctrl_func += " LATCH_"+mtype+": entity work.CreateStartSignal\n" - if delay > 0: - startsignal_parameter_list = " DELAY => " + str(delay*2) +",\n" - int_ctrl_func += " generic map (\n"+startsignal_parameter_list.rstrip(",\n")+"\n )\n" - - int_ctrl_func += " port map (\n" - int_ctrl_func += " clk => clk,\n" - int_ctrl_func += " reset => reset,\n" - if "MP_" in mtype : - int_ctrl_func += " done => PC_done,\n" - int_ctrl_func += " bx_out => PC_bx_out,\n" - else: - if first_proc: - if mtype_up == "VMSMER": - mtype_up = "PC" - int_ctrl_func += " done => "+mtype_up+"_start,\n" - int_ctrl_func += " bx_out => "+mtype_up+"_bx_in,\n" + if "VMSMER" not in mtype: + int_ctrl_wire += " signal "+mtype+"_bx_in : std_logic_vector(2 downto 0);\n" + int_ctrl_wire += " signal "+mtype+"_start : std_logic := '0';\n" + int_ctrl_func += " LATCH_"+mtype+": entity work.CreateStartSignal\n" + if delay > 0: + startsignal_parameter_list = " DELAY => " + str(delay*2) +",\n" + int_ctrl_func += " generic map (\n"+startsignal_parameter_list.rstrip(",\n")+"\n )\n" + + int_ctrl_func += " port map (\n" + int_ctrl_func += " clk => clk,\n" + int_ctrl_func += " reset => reset,\n" + if "MP_" in mtype : + int_ctrl_func += " done => PC_done,\n" + int_ctrl_func += " bx_out => PC_bx_out,\n" else: - int_ctrl_func += " done => "+mtype_up+"_done,\n" - int_ctrl_func += " bx_out => "+mtype_up+"_bx_out,\n" - int_ctrl_func += " bx => "+mtype+"_bx_in,\n" - int_ctrl_func += " start => "+mtype+"_start\n" - int_ctrl_func += " );\n\n" + if first_proc: + if mtype_up == "VMSMER": + mtype_up = "PC" + int_ctrl_func += " done => "+mtype_up+"_start,\n" + int_ctrl_func += " bx_out => "+mtype_up+"_bx_in,\n" + else: + int_ctrl_func += " done => "+mtype_up+"_done,\n" + int_ctrl_func += " bx_out => "+mtype_up+"_bx_out,\n" + int_ctrl_func += " bx => "+mtype+"_bx_in,\n" + int_ctrl_func += " start => "+mtype+"_start\n" + int_ctrl_func += " );\n\n" return int_ctrl_wire,int_ctrl_func From 7e1b9b7777bbdc2f150f765c9e0a44c3d07b97d0 Mon Sep 17 00:00:00 2001 From: Anders Ryd Date: Sun, 2 Mar 2025 10:38:54 -0500 Subject: [PATCH 11/14] Fix PR comments from A. Hart --- TrackletGraph.py | 2 +- WriteVHDLSyntax.py | 7 ------- 2 files changed, 1 insertion(+), 8 deletions(-) diff --git a/TrackletGraph.py b/TrackletGraph.py index afcc5f1..c2b348b 100644 --- a/TrackletGraph.py +++ b/TrackletGraph.py @@ -498,7 +498,7 @@ def split_track_fit_streams(p_dict, m_dict): down_p.input_port_names.append("trackwordin") # We will have all layers for each TrackWord - layers = {'L6', 'D5', 'L4', 'D2', 'D1', 'L2', 'L5', 'L1', 'L3', 'D4', 'D3'} + layers = {'L1', 'L2', 'L3', 'L4', 'L5', 'L6', 'D1', 'D2', 'D3', 'D4', 'D5'} # Replace the old memory with a stub word for each of the # layers/disks that can have matches. diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index 0ee5ae0..2027ef7 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -202,8 +202,6 @@ def writeTBMemoryReadInstance(mtypeB, memDict, bxbitwidth, is_initial, is_binned memtmp = memtmp.replace("n1","") # memtmp = "T"+mem[1:10] string_mem += " FILE_NAME".ljust(str_len) + "=> FILE_IN_" + mtypeB+"&\""+ memtmp + "\"&inputFileNameEnding,\n" - if "MPAR" in mem: - string_mem += " PAGE_LENGTH".ljust(str_len) + "=> 128,\n" string_mem += " DELAY".ljust(str_len) + "=> " + mtypeB.split("_")[0] + "_DELAY*MAX_ENTRIES,\n" string_mem += " RAM_WIDTH".ljust(str_len) + "=> " + mtypeB.split("_")[1] + ",\n" string_mem += " NUM_PAGES".ljust(str_len) + "=> " + str(2**bxbitwidth) + ",\n" @@ -319,7 +317,6 @@ def writeMemoryUtil(memDict, memInfoDict): if "MPAR" in mtypeB: tName = "t_"+mtypeB+"_ADDR" ss += " subtype "+tName+" is std_logic_vector("+str(8+memInfo.bxbitwidth)+" downto 0);\n" - #ss += " subtype "+tName+" is std_logic_vector("+str(7+memInfo.bxbitwidth)+" downto 0);\n" elif "MPROJ" in mtypeB: tName = "t_"+mtypeB+"_ADDR" ss += " subtype "+tName+" is std_logic_vector("+str(7+memInfo.bxbitwidth)+" downto 0);\n" @@ -588,8 +585,6 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl parameterlist += " NUM_PAGES => "+str(num_pages)+",\n" if "MPROJ" in mem : parameterlist += " PAGE_LENGTH => 64,\n" - if "MPAR" in mem: - parameterlist += " PAGE_LENGTH => 128,\n" if "MPROJ" in mem or "MPAR" in mem: parameterlist += " NUM_TPAGES => 4,\n" parameterlist += " INIT_FILE => \"\",\n" @@ -1286,7 +1281,6 @@ def writeFWBlockInstance(topfunc, memDict, memInfoDict, initial_proc, final_proc string_output += (" "+mem+"_A_enb").ljust(str_len) + "=> "+mem+"_enb,\n" string_output += (" "+mem+"_AV_readaddr").ljust(str_len) + "=> "+mem+"_readaddr,\n" string_output += (" "+mem+"_AV_dout").ljust(str_len) + "=> "+mem+"_dout,\n" - #string_output += (" "+mem+"_AV_dout_mask").ljust(str_len) + "=> open,\n" #FIXME string_output += (" "+mem+"_enb_nent").ljust(str_len) + "=> open,\n" string_output += (" "+mem+"_V_addr_nent").ljust(str_len) + "=> open,\n" string_output += (" "+mem+"_AV_dout_nent").ljust(str_len) + "=> open,\n" @@ -1497,7 +1491,6 @@ def writeProcCombination(module, str_ctrl_func, str_ports): if "PC_" in module.inst: module_str += " " + module.inst + "_mem_reader : entity work.mem_reader\n" module_str += " generic map (\n" - module_str += " PAGE_LENGTH => 128,\n" module_str += " RAM_WIDTH => " + str(module.upstreams[0].bitwidth) + ",\n" module_str += " NUM_TPAGES => 4,\n" module_str += " NAME => \""+module.inst+"_mem_reader\"\n" From 21fdb1164247950f60344dcbd10391e01dc4a025 Mon Sep 17 00:00:00 2001 From: Anders Ryd Date: Sat, 8 Mar 2025 08:42:07 -0500 Subject: [PATCH 12/14] Fix to use the hit mask for the mpar memory --- WriteVHDLSyntax.py | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index 2027ef7..c61533e 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -527,6 +527,8 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl wirelist += "STD_LOGIC_VECTOR(8 downto 0);\n" wirelist += " signal "+mem+"_AV_dout_nent : " wirelist += "t_arr_7b(0 to 31);\n" + wirelist += " signal "+mem+"_AV_dout_mask : " + wirelist += "t_arr_4b(0 to 7);\n" #FIXME this is a hack if "AS" in mem and "in" in mem : wirelist += " signal "+mem+"_V_as : " @@ -779,6 +781,8 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl portlist += " nent_o => "+mem+"_AV_dout_nent,\n" if "MPROJ" in mem: portlist += " mask_o => "+mem+"_AV_dout_mask,\n" + if "MPAR" in mem: + portlist += " mask_o => "+mem+"_AV_dout_mask,\n" else: portlist += " nent_o => open,\n" @@ -1505,7 +1509,8 @@ def writeProcCombination(module, str_ctrl_func, str_ports): module_str += " dout => MPAR_"+module.inst[3:]+"in_V_tpar,\n" module_str += " valid => MPAR_"+module.inst[3:]+"in_valid,\n" module_str += " index => MPAR_"+module.inst[3:]+"in_trackletindex,\n" - module_str += " nent => MPAR_"+module.inst[3:]+"in_AV_dout_nent\n" + module_str += " nent => MPAR_"+module.inst[3:]+"in_AV_dout_nent,\n" + module_str += " mask => MPAR_"+module.inst[3:]+"in_AV_dout_mask\n" module_str += " );\n\n" if "VMSMER_" in module.inst: @@ -1524,7 +1529,8 @@ def writeProcCombination(module, str_ctrl_func, str_ports): module_str += " dout => AS_"+module.inst[7:]+"in_V_as,\n" module_str += " valid => AS_"+module.inst[7:]+"in_valid,\n" module_str += " index => AS_"+module.inst[7:]+"in_index(6 downto 0),\n" - module_str += " nent => AS_"+module.inst[7:]+"in_AV_dout_nent\n" + module_str += " nent => AS_"+module.inst[7:]+"in_AV_dout_nent,\n" + module_str += " mask => (others => (others => '1'))\n" module_str += " );\n\n" module_str += str_ctrl_func From c9c1de56607aab1b4036c829824986910b0536ea Mon Sep 17 00:00:00 2001 From: Anders Ryd Date: Sun, 9 Mar 2025 11:15:20 -0400 Subject: [PATCH 13/14] Correct calculation of number of stub words for writing TB memories --- generator_hdl.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/generator_hdl.py b/generator_hdl.py index 1a11858..4ee22fa 100755 --- a/generator_hdl.py +++ b/generator_hdl.py @@ -298,10 +298,10 @@ def writeTBMemoryWrites(memDict, memInfoDict, notfinal_procs,split, MPARdict): seed = memName[-4:] bw_keys = [key for key in memDict if key.startswith('BW_')] bw_width = memDict[bw_keys[0]][0].bitwidth if len(bw_keys) > 0 else 0 - n_bw = len(memDict[bw_keys[0]]) if len(bw_keys) > 0 else 0 + n_bw = len([key for key in memDict[bw_keys[0]] if seed in key.inst]) if len(bw_keys) > 0 else 0 dw_keys = [key for key in memDict if key.startswith('DW_')] dw_width = memDict[dw_keys[0]][0].bitwidth if len(dw_keys) > 0 else 0 - n_dw = len(memDict[dw_keys[0]]) if len(dw_keys) > 0 else 0 + n_dw = len([key for key in memDict[dw_keys[0]] if seed in key.inst]) if len(dw_keys) > 0 else 0 # Calculate total width of track word plus stub words total_width = str(m.bitwidth + n_bw * bw_width + n_dw * dw_width) From de1050e80ce029a0cac9c460f2d515be8aad7f69 Mon Sep 17 00:00:00 2001 From: Anders Ryd Date: Mon, 10 Mar 2025 09:39:19 -0400 Subject: [PATCH 14/14] Fixes to writing of debug files --- WriteVHDLSyntax.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index c61533e..ddc90b0 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -1368,6 +1368,9 @@ def writeTBMemoryWriteInstance(mtypeB, memList, proc, proc_up, bxbitwidth, is_bi if "MPROJ" in mem : string_mem += " NUM_TPAGES".ljust(str_len)+"=> 4,\n" string_mem += " PAGE_LENGTH".ljust(str_len)+"=> 64,\n" + string_mem += " CLK_CNT_INIT".ljust(str_len)+"=> -17,\n" #-17 is emperically determined to allign the FileWriter BX with the data stream + if "FM" in mem : + string_mem += " CLK_CNT_INIT".ljust(str_len)+"=> -17,\n" #-17 is emperically determined to allign the FileWriter BX with the data stream string_mem += " NUM_PAGES".ljust(str_len)+"=> " + str(2**bxbitwidth) + "\n" string_mem += " )\n" string_mem += " port map (\n"