From 9262bed75c0e213eddfb9cfaccbd0b1e41427a11 Mon Sep 17 00:00:00 2001 From: Andrew Hart Date: Tue, 7 Oct 2025 07:31:10 -0400 Subject: [PATCH 01/14] Updated project_generation_scripts submodule. --- emData/project_generation_scripts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/emData/project_generation_scripts b/emData/project_generation_scripts index 19207361591..5a0daad0d9f 160000 --- a/emData/project_generation_scripts +++ b/emData/project_generation_scripts @@ -1 +1 @@ -Subproject commit 19207361591d7062bf42d076bf93323b58005ed3 +Subproject commit 5a0daad0d9f3dd47174ebb22f1d597147870a08b From 4079e20b3a5f5c82d38d10e6e22c79769b832156 Mon Sep 17 00:00:00 2001 From: Andrew Hart Date: Wed, 18 Jun 2025 11:10:54 -0400 Subject: [PATCH 02/14] Made kMaxProc into a function with a clock multiplier argument. --- TestBenches/FileReadUtility.h | 8 ++++---- TestBenches/InputRouter_test.cpp | 4 ++-- TestBenches/ProjectionCalculator_test.cpp | 2 +- TestBenches/TrackBuilder_test.cpp | 18 +++++++++--------- TestBenches/VMStubMERouter_test.cpp | 2 +- TrackletAlgorithm/Constants.h | 4 +++- TrackletAlgorithm/InputRouter.h | 2 +- TrackletAlgorithm/MatchProcessor.h | 2 +- TrackletAlgorithm/TrackBuilder.h | 6 +++--- TrackletAlgorithm/VMRouterCM.h | 2 +- emData/generate_IR.py | 4 ++-- emData/generate_TB.py | 10 +++++----- 12 files changed, 33 insertions(+), 31 deletions(-) diff --git a/TestBenches/FileReadUtility.h b/TestBenches/FileReadUtility.h index cf254a63e95..2c51c850eca 100644 --- a/TestBenches/FileReadUtility.h +++ b/TestBenches/FileReadUtility.h @@ -326,7 +326,7 @@ unsigned int compareMemWithFile(const MemType& memory, std::ifstream& fout, int ievt, const std::string& label, const bool truncated = false, const bool print_empty = false, - int maxProc = kMaxProc) + int maxProc = kMaxProc()) { //////////////////////////////////////// // Read from file @@ -362,7 +362,7 @@ template unsigned int compareBinnedMemWithFile(const MemType& memory, std::ifstream& fout, int ievt, const std::string& label, - const bool truncated = false, int maxProc = kMaxProc) + const bool truncated = false, int maxProc = kMaxProc()) { unsigned int err_count = 0; @@ -419,7 +419,7 @@ template unsigned int compareBinnedMemCMWithFile(const MemType& memory, std::ifstream& fout, int ievt, const std::string& label, - const bool truncated = false, int maxProc = kMaxProc) + const bool truncated = false, int maxProc = kMaxProc()) { unsigned int err_count = 0; @@ -594,7 +594,7 @@ template& foutVec, int ievt, const std::string& label, const bool truncated = false, const bool print_empty = false, - int maxProc = kMaxProc) + int maxProc = kMaxProc()) { //////////////////////////////////////// // Read from file diff --git a/TestBenches/InputRouter_test.cpp b/TestBenches/InputRouter_test.cpp index db1a08d7e00..a89c531e6cd 100644 --- a/TestBenches/InputRouter_test.cpp +++ b/TestBenches/InputRouter_test.cpp @@ -651,8 +651,8 @@ int main(int argc, char * argv[]) std::cout << "Event#" << std::dec << +cEvId << "\n"; // prepare input stub stream - ap_uint hInputStubs[kMaxProc]; - for( size_t cStubIndx=0; cStubIndx < kMaxProc; cStubIndx++) + ap_uint hInputStubs[kMaxProc()]; + for( size_t cStubIndx=0; cStubIndx < kMaxProc(); cStubIndx++) hInputStubs[cStubIndx]=ap_uint(0); writeArrayFromFile>(hInputStubs , cLinkDataStream, cEvId); diff --git a/TestBenches/ProjectionCalculator_test.cpp b/TestBenches/ProjectionCalculator_test.cpp index c2687b88bdf..e5b88aaad97 100644 --- a/TestBenches/ProjectionCalculator_test.cpp +++ b/TestBenches/ProjectionCalculator_test.cpp @@ -102,7 +102,7 @@ int main() const int NPAGE = 4; for (int ipage = 0; ipage < NPAGE; ipage++) { - for (int ipar = 0; ipar < kMaxProc; ipar++) { + for (int ipar = 0; ipar < kMaxProc(); ipar++) { const bool valid = ipar < trackletParameters.getEntries(bx, ipage); TOP_FUNC_(bx, bx_o, trackletParameters.read_mem(bx, ipar, ipage), ipage*128+ipar, valid, trackletParametersOut, tproj_barrel_ps, tproj_barrel_2s, tproj_disk); diff --git a/TestBenches/TrackBuilder_test.cpp b/TestBenches/TrackBuilder_test.cpp index 87262dd20df..c7ad9420c4f 100644 --- a/TestBenches/TrackBuilder_test.cpp +++ b/TestBenches/TrackBuilder_test.cpp @@ -30,23 +30,23 @@ constexpr int InputBase = 16; constexpr int OutputBase = 16; template -void setBarrelStubs(TrackFit_t &track, const TrackFit_t::BarrelStubWord stubWords[][kMaxProc], const unsigned i) { +void setBarrelStubs(TrackFit_t &track, const TrackFit_t::BarrelStubWord stubWords[][kMaxProc()], const unsigned i) { track.setBarrelStubWord(stubWords[I][i]); setBarrelStubs(track, stubWords, i); } template<> -void setBarrelStubs<-1>(TrackFit_t &track, const TrackFit_t::BarrelStubWord stubWords[][kMaxProc], const unsigned i) { +void setBarrelStubs<-1>(TrackFit_t &track, const TrackFit_t::BarrelStubWord stubWords[][kMaxProc()], const unsigned i) { } template -void setDiskStubs(TrackFit_t &track, const TrackFit_t::DiskStubWord stubWords[][kMaxProc], const unsigned i) { +void setDiskStubs(TrackFit_t &track, const TrackFit_t::DiskStubWord stubWords[][kMaxProc()], const unsigned i) { track.setDiskStubWord(stubWords[I][i]); setDiskStubs(track, stubWords, i); } template<> -void setDiskStubs<-1>(TrackFit_t &track, const TrackFit_t::DiskStubWord stubWords[][kMaxProc], const unsigned i) { +void setDiskStubs<-1>(TrackFit_t &track, const TrackFit_t::DiskStubWord stubWords[][kMaxProc()], const unsigned i) { } template @@ -109,9 +109,9 @@ int main() vector> diskFullMatches(nFMDiskMems); // output memories - TrackFit_t::TrackWord trackWord[kMaxProc]; - TrackFit_t::BarrelStubWord barrelStubWords[trklet::N_LAYER][kMaxProc]; - TrackFit_t::DiskStubWord diskStubWords[trklet::N_DISK][kMaxProc]; + TrackFit_t::TrackWord trackWord[kMaxProc()]; + TrackFit_t::BarrelStubWord barrelStubWords[trklet::N_LAYER][kMaxProc()]; + TrackFit_t::DiskStubWord diskStubWords[trklet::N_DISK][kMaxProc()]; TrackFitMemory_t tracksMem; /////////////////////////// @@ -121,7 +121,7 @@ int main() cout << "Event: " << dec << ievt << endl; // Clear all output memories before starting. - for (unsigned short i = 0; i < kMaxProc; i++) { + for (unsigned short i = 0; i < kMaxProc(); i++) { trackWord[i] = TrackFit_t::TrackWord(0); for (short j = 0; j < trklet::N_LAYER; j++) barrelStubWords[j][i] = TrackFit_t::BarrelStubWord(0); @@ -165,7 +165,7 @@ int main() done ); - for (unsigned short i = 0; i < kMaxProc; i++) { + for (unsigned short i = 0; i < kMaxProc(); i++) { TrackFit_t track; track.setTrackWord(trackWord[i]); setBarrelStubs(track, barrelStubWords, i); diff --git a/TestBenches/VMStubMERouter_test.cpp b/TestBenches/VMStubMERouter_test.cpp index 8f98990522b..23d57bef3fb 100644 --- a/TestBenches/VMStubMERouter_test.cpp +++ b/TestBenches/VMStubMERouter_test.cpp @@ -80,7 +80,7 @@ int main() { // Read event and write to memories writeMemFromFile(memoriesAS, fin_allstubs[0], ievt); - for (int index = 0; index < kMaxProc; ++index){ + for (int index = 0; index < kMaxProc(); ++index){ // bx - bunch crossing BXType bx = ievt; diff --git a/TrackletAlgorithm/Constants.h b/TrackletAlgorithm/Constants.h index f258cf3fe37..30bef5b624d 100644 --- a/TrackletAlgorithm/Constants.h +++ b/TrackletAlgorithm/Constants.h @@ -79,7 +79,9 @@ constexpr int kNbitsphibin = 3; constexpr int kMaxStubsFromLink = 256; constexpr int kTMUX = 18; //For hourglass project -constexpr int kMaxProc = kTMUX * 6; +constexpr int kMaxProc(const int clockMult = 6) { + return (kTMUX * clockMult); +} constexpr unsigned int kNbitszfinebintable = 7; constexpr unsigned int kNbitsrfinebintable = 4; diff --git a/TrackletAlgorithm/InputRouter.h b/TrackletAlgorithm/InputRouter.h index ef682a5a307..c1ab39a7486 100644 --- a/TrackletAlgorithm/InputRouter.h +++ b/TrackletAlgorithm/InputRouter.h @@ -301,7 +301,7 @@ void InputRouter( const BXType bx CountMemories(hPhBnWord, nMems, nMemsPerLyr); LOOP_ProcessIR: - for (int cStubCounter = 0; cStubCounter < kMaxProc; cStubCounter++) + for (int cStubCounter = 0; cStubCounter < kMaxProc(); cStubCounter++) { #pragma HLS pipeline II = 1 rewind #pragma HLS latency min=6 max=6 diff --git a/TrackletAlgorithm/MatchProcessor.h b/TrackletAlgorithm/MatchProcessor.h index d5c124dcb63..3d04230ad77 100644 --- a/TrackletAlgorithm/MatchProcessor.h +++ b/TrackletAlgorithm/MatchProcessor.h @@ -1283,7 +1283,7 @@ void MatchProcessor(BXType bx, constexpr int NUM_PHI_BINS = 1 << kNbitsphibin; constexpr int BIN_ADDR_WIDTH = 4; - PROC_LOOP: for (ap_uint istep = 0; istep < kMaxProc - kMaxProcOffset(module::MP); istep++) { + PROC_LOOP: for (ap_uint istep = 0; istep < kMaxProc() - kMaxProcOffset(module::MP); istep++) { #pragma HLS PIPELINE II=1 rewind if (hasMatch) { diff --git a/TrackletAlgorithm/TrackBuilder.h b/TrackletAlgorithm/TrackBuilder.h index 2745312e89d..06309b3bf87 100644 --- a/TrackletAlgorithm/TrackBuilder.h +++ b/TrackletAlgorithm/TrackBuilder.h @@ -117,8 +117,8 @@ void TrackBuilder( const FullMatchMemory diskFullMatches[], BXType &bx_o, typename TrackFit::TrackWord trackWord[], - typename TrackFit::BarrelStubWord barrelStubWords[][kMaxProc], - typename TrackFit::DiskStubWord diskStubWords[][kMaxProc], + typename TrackFit::BarrelStubWord barrelStubWords[][kMaxProc()], + typename TrackFit::DiskStubWord diskStubWords[][kMaxProc()], bool &done ) { @@ -246,7 +246,7 @@ void TrackBuilder( } - full_matches : for (unsigned short i = 0; i < kMaxProc; i++) { + full_matches : for (unsigned short i = 0; i < kMaxProc(); i++) { #pragma HLS pipeline II=1 rewind #pragma HLS latency min=6 max=6 diff --git a/TrackletAlgorithm/VMRouterCM.h b/TrackletAlgorithm/VMRouterCM.h index 26ffaef4105..f205ce2a35d 100644 --- a/TrackletAlgorithm/VMRouterCM.h +++ b/TrackletAlgorithm/VMRouterCM.h @@ -223,7 +223,7 @@ void VMRouterCM(const BXType bx, BXType& bx_o, ///////////////////////////////////// // Main Loop - constexpr int maxLoop = kMaxProc; + constexpr int maxLoop = kMaxProc(); TOPLEVEL: for (int i = 0; i < maxLoop; ++i) { #pragma HLS PIPELINE II=1 rewind diff --git a/emData/generate_IR.py b/emData/generate_IR.py index 1c506c6375d..f64b89814e8 100755 --- a/emData/generate_IR.py +++ b/emData/generate_IR.py @@ -38,7 +38,7 @@ def createDefinitionsTemplate(): " const BXType bx\n" " , const ap_uint hLinkWord // input link LUT \n" " , const ap_uint hPhBnWord // n phi bins LUT \n" - " , ap_uint hInputStubs[kMaxProc]//input stubs \n" + " , ap_uint hInputStubs[kMaxProc()]//input stubs \n" " , BXType & bx_o // output bx \n" " , DTCStubMemory hOutputStubs[cNMemories_IR_{LinkName}])" "\n{{\n" @@ -64,7 +64,7 @@ def createDeclarationTemplate(): " const BXType bx\n" " , const ap_uint hLinkWord // input link LUT \n" " , const ap_uint hPhBnWord // n phi bins LUT \n" - " , ap_uint hInputStubs[kMaxProc]//input stubs \n" + " , ap_uint hInputStubs[kMaxProc()]//input stubs \n" " , BXType & bx_o // output bx \n" " , DTCStubMemory hOutputStubs[cNMemories_IR_{LinkName}]" ");\n") diff --git a/emData/generate_TB.py b/emData/generate_TB.py index e7e610b7c37..f950333299e 100755 --- a/emData/generate_TB.py +++ b/emData/generate_TB.py @@ -278,8 +278,8 @@ class ITC(Enum): " const FullMatchMemory diskFullMatches[],\n" " BXType &bx_o,\n" " TrackFit::TrackWord trackWord[],\n" - " TrackFit::BarrelStubWord barrelStubWords[][kMaxProc],\n" - " TrackFit::DiskStubWord diskStubWords[][kMaxProc],\n" + " TrackFit::BarrelStubWord barrelStubWords[][kMaxProc()],\n" + " TrackFit::DiskStubWord diskStubWords[][kMaxProc()],\n" " bool &done\n" ");\n" ) @@ -329,9 +329,9 @@ class ITC(Enum): " const FullMatchMemory barrelFullMatches[" + str(nBarrelFMMem) + "],\n" " const FullMatchMemory diskFullMatches[" + str(nDiskFMMem) + "],\n" " BXType &bx_o,\n" - " TrackFit::TrackWord trackWord[kMaxProc],\n" - " TrackFit::BarrelStubWord barrelStubWords[trklet::N_LAYER][kMaxProc],\n" - " TrackFit::DiskStubWord diskStubWords[trklet::N_DISK][kMaxProc],\n" + " TrackFit::TrackWord trackWord[kMaxProc()],\n" + " TrackFit::BarrelStubWord barrelStubWords[trklet::N_LAYER][kMaxProc()],\n" + " TrackFit::DiskStubWord diskStubWords[trklet::N_DISK][kMaxProc()],\n" " bool &done\n" ") {\n" "#pragma HLS inline recursive\n" From 07231eaea7516dbeb47f98c5806f987d94fa1fb6 Mon Sep 17 00:00:00 2001 From: Andrew Hart Date: Mon, 16 Jun 2025 13:01:22 -0400 Subject: [PATCH 03/14] Added extra registers to tf_mem for nent_o. --- IntegrationTests/common/hdl/tf_mem.vhd | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/IntegrationTests/common/hdl/tf_mem.vhd b/IntegrationTests/common/hdl/tf_mem.vhd index b1a58861770..c021ff21d91 100644 --- a/IntegrationTests/common/hdl/tf_mem.vhd +++ b/IntegrationTests/common/hdl/tf_mem.vhd @@ -38,6 +38,7 @@ entity tf_mem is NAME : string := "MEMNAME"; --! Name of mem for printout DEBUG : boolean := false; --! If true prints debug info MEM_TYPE : string := "block"; --! specifies RAM type (block/ultra) + NENT_SYNC : boolean := false; --! Enable synchronizer for nent_o FILE_WRITE : boolean := true --! If set to true will --write debug output for memory ); @@ -62,6 +63,7 @@ architecture rtl of tf_mem is -- ########################### Types ########################### type t_arr_1d_slv_mem is array(0 to RAM_DEPTH-1) of std_logic_vector(RAM_WIDTH-1 downto 0); --! 1D array of slv +type t_arr_2d_7b is array(0 to 1) of t_arr_7b(0 to NUM_PAGES-1); -- ########################### Function ########################## --! @brief TextIO function to read memory data to initialize tf_mem. Needed here because of variable slv width! @@ -103,6 +105,7 @@ end read_tf_mem_data; signal sa_RAM_data : t_arr_1d_slv_mem := read_tf_mem_data(INIT_FILE, INIT_HEX); --! RAM data content signal sv_RAM_row : std_logic_vector(RAM_WIDTH-1 downto 0) := (others =>'0'); --! RAM data row signal enb_reg : std_logic; --! Enable register +signal nent_reg : t_arr_2d_7b := (others => (others => (others => '0'))); -- ########################### Attributes ########################### attribute ram_style : string; @@ -155,7 +158,7 @@ begin slv_page_cnt := (others => '0'); end if; --report time'image(now)&" tf_mem "&NAME&" will zero nent"; - nent_o(to_integer(unsigned(slv_page_cnt))) <= (others => '0'); + nent_reg(0)(to_integer(unsigned(slv_page_cnt))) <= (others => '0'); end if; if (rsta='1') then init := '1'; @@ -172,9 +175,9 @@ begin overwrite := addra(0); --vi_page_cnt_slv := std_logic_vector(to_unsigned(vi_page_cnt_save,vi_page_cnt_slv'length)); if (overwrite = '0') then - address := slv_page_cnt_save&nent_o(to_integer(unsigned(slv_page_cnt_save))); + address := slv_page_cnt_save&nent_reg(0)(to_integer(unsigned(slv_page_cnt_save))); else - address := slv_page_cnt_save&std_logic_vector(to_unsigned(to_integer(unsigned(nent_o(to_integer(unsigned(slv_page_cnt_save)))))-1,nent_o(to_integer(unsigned(slv_page_cnt_save)))'length)); + address := slv_page_cnt_save&std_logic_vector(to_unsigned(to_integer(unsigned(nent_reg(0)(to_integer(unsigned(slv_page_cnt_save)))))-1,nent_reg(0)(to_integer(unsigned(slv_page_cnt_save)))'length)); end if; --report "tf_mem "&time'image(now)&" "&NAME&" page writeaddr "&" "&to_bstring(slv_page_cnt_save)&" "&to_bstring(address)&" "&to_bstring(overwrite)&" "&to_bstring(dina)&" addra "&to_bstring(addra); sa_RAM_data(to_integer(unsigned(address))) <= dina; -- Write data @@ -184,7 +187,7 @@ begin initialized := true; if (overwrite = '0') then - nent_o(to_integer(unsigned(slv_page_cnt_save))) <= std_logic_vector(to_unsigned(to_integer(unsigned(nent_o(to_integer(unsigned(slv_page_cnt_save))))) + 1, nent_o(to_integer(unsigned(slv_page_cnt_save)))'length)); -- + 1 (slv) + nent_reg(0)(to_integer(unsigned(slv_page_cnt_save))) <= std_logic_vector(to_unsigned(to_integer(unsigned(nent_reg(0)(to_integer(unsigned(slv_page_cnt_save))))) + 1, nent_reg(0)(to_integer(unsigned(slv_page_cnt_save)))'length)); -- + 1 (slv) end if; end if; end if; @@ -209,6 +212,18 @@ begin end if; end process; +SYNCHRONIZER : if NENT_SYNC generate + process(clkb) + begin + if rising_edge(clkb) then + nent_reg(1) <= nent_reg(0); + nent_o <= nent_reg(1); + end if; + end process; +else generate + nent_o <= nent_reg(0); +end generate SYNCHRONIZER; + -- The following code generates HIGH_PERFORMANCE (use output register) or LOW_LATENCY (no output register) MODE : if (RAM_PERFORMANCE = "LOW_LATENCY") generate -- no_output_register; 1 clock cycle read latency at the cost of a longer clock-to-out timing doutb <= sv_RAM_row; From 0e89c060e58c27abc6dd0fff09caf04c7912b7f0 Mon Sep 17 00:00:00 2001 From: Andrew Hart Date: Tue, 7 Oct 2025 07:23:04 -0400 Subject: [PATCH 04/14] Added MAX_ENTRIES parameters. --- IntegrationTests/common/hdl/FileReaderFIFO.vhd | 3 ++- IntegrationTests/common/hdl/tf_mem.vhd | 5 +++-- IntegrationTests/common/hdl/tf_pkg.vhd | 1 + 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/IntegrationTests/common/hdl/FileReaderFIFO.vhd b/IntegrationTests/common/hdl/FileReaderFIFO.vhd index d449d9b6306..a2ba0c1fee0 100644 --- a/IntegrationTests/common/hdl/FileReaderFIFO.vhd +++ b/IntegrationTests/common/hdl/FileReaderFIFO.vhd @@ -28,7 +28,8 @@ entity FileReaderFIFO is DELAY : natural := 0; --! Delay output signals by this many clocks. FIFO_WIDTH : natural := 39; --! Data width DEBUG : boolean := false; --! Debug printout - FILE_NAME_DEBUG : string := "" --! Name of .txt file for debug printout. + FILE_NAME_DEBUG : string := ""; --! Name of .txt file for debug printout. + MAX_ENTRIES : natural := MAX_ENTRIES --! Period in clock ticks for switching pages ); port ( CLK : in std_logic; diff --git a/IntegrationTests/common/hdl/tf_mem.vhd b/IntegrationTests/common/hdl/tf_mem.vhd index c021ff21d91..d56609db655 100644 --- a/IntegrationTests/common/hdl/tf_mem.vhd +++ b/IntegrationTests/common/hdl/tf_mem.vhd @@ -39,6 +39,7 @@ entity tf_mem is DEBUG : boolean := false; --! If true prints debug info MEM_TYPE : string := "block"; --! specifies RAM type (block/ultra) NENT_SYNC : boolean := false; --! Enable synchronizer for nent_o + MAX_ENTRIES : natural := MAX_ENTRIES; --! Period in clock ticks for switching pages FILE_WRITE : boolean := true --! If set to true will --write debug output for memory ); @@ -121,8 +122,8 @@ process(clka) variable initialized : boolean := false; variable init : std_logic := '1'; --FIXME hardcoded number - variable slv_clk_cnt : std_logic_vector(6 downto 0) := (others => '0'); -- Clock counter - variable slv_clk_cnt_save : std_logic_vector(6 downto 0) := (others => '0'); -- Clock counter + variable slv_clk_cnt : std_logic_vector(7 downto 0) := (others => '0'); -- Clock counter + variable slv_clk_cnt_save : std_logic_vector(7 downto 0) := (others => '0'); -- Clock counter variable slv_page_cnt_save : std_logic_vector(clogb2(NUM_PAGES)-1 downto 0) := (others => '0'); -- Page counter save variable slv_page_cnt : std_logic_vector(clogb2(NUM_PAGES)-1 downto 0) := (others => '0'); variable bx : integer := 0; diff --git a/IntegrationTests/common/hdl/tf_pkg.vhd b/IntegrationTests/common/hdl/tf_pkg.vhd index 157e8240660..5e4f7e42123 100644 --- a/IntegrationTests/common/hdl/tf_pkg.vhd +++ b/IntegrationTests/common/hdl/tf_pkg.vhd @@ -34,6 +34,7 @@ package tf_pkg is constant DEBUG : boolean := true; --! Debug off/on constant MAX_EVENTS : natural := 100; --! Max. number of BX events constant MAX_ENTRIES : natural := 108; --! Max. number of entries: 108 = BX period with 240 MHz + constant MAX_ENTRIES_360 : natural := 162; --! Max. number of entries: 162 = BX period with 360 MHz constant EMDATA_WIDTH : natural := 80; --! Max. bit width of emData constant N_MEM_BINS : natural := 8; --! Number of memory bins constant N_ENTRIES_PER_MEM_BINS : natural := 16; --! Number of entries per memory bin From 7dda7ab69df09b4f1cfeaf60745eba9c77f2e893 Mon Sep 17 00:00:00 2001 From: Andrew Hart Date: Tue, 24 Jun 2025 12:54:26 -0400 Subject: [PATCH 05/14] Added port to start reading when clocks are locked. --- IntegrationTests/common/hdl/FileReader.vhd | 8 ++------ IntegrationTests/common/hdl/FileReaderFIFO.vhd | 10 +++------- 2 files changed, 5 insertions(+), 13 deletions(-) diff --git a/IntegrationTests/common/hdl/FileReader.vhd b/IntegrationTests/common/hdl/FileReader.vhd index 65331da0435..617ba68795a 100644 --- a/IntegrationTests/common/hdl/FileReader.vhd +++ b/IntegrationTests/common/hdl/FileReader.vhd @@ -26,7 +26,6 @@ entity FileReader is generic ( FILE_NAME : string; --! Name of .txt file corresponding to memory content PAGE_LENGTH : natural := PAGE_LENGTH; --! Page size - DELAY : natural := 0; --! Delay output signals by this many clocks. RAM_WIDTH : natural := 18; --! RAM data width NUM_PAGES : natural := 2; --! Number of pages in RAM memory NUM_TPAGES : natural := 1; --! Number of bins in RAM memory (1 if unbinned) @@ -40,6 +39,7 @@ entity FileReader is ); port ( CLK : in std_logic; + LOCKED : in std_logic; ADDR : out std_logic_vector(ADDR_WIDTH-1 downto 0); DATA : out std_logic_vector(RAM_WIDTH-1 downto 0); START : out std_logic; @@ -221,14 +221,10 @@ end process procFile; procDelay : process(CLK) -- Process to delay start of first event output by required amount. - variable COUNT : natural := 0; begin if rising_edge(CLK) then - if (COUNT < DELAY) then - COUNT := COUNT + 1; - WAITING <= true; - else + if (LOCKED = '1') then WAITING <= false; end if; end if; diff --git a/IntegrationTests/common/hdl/FileReaderFIFO.vhd b/IntegrationTests/common/hdl/FileReaderFIFO.vhd index a2ba0c1fee0..ccfe344169e 100644 --- a/IntegrationTests/common/hdl/FileReaderFIFO.vhd +++ b/IntegrationTests/common/hdl/FileReaderFIFO.vhd @@ -25,7 +25,6 @@ use work.tf_pkg.all; entity FileReaderFIFO is generic ( FILE_NAME : string; --! Name of .txt file corresponding to memory content - DELAY : natural := 0; --! Delay output signals by this many clocks. FIFO_WIDTH : natural := 39; --! Data width DEBUG : boolean := false; --! Debug printout FILE_NAME_DEBUG : string := ""; --! Name of .txt file for debug printout. @@ -33,6 +32,7 @@ entity FileReaderFIFO is ); port ( CLK : in std_logic; + LOCKED : in std_logic; READ_EN : in std_logic; EMPTY_NEG : out std_logic; DATA : out std_logic_vector(FIFO_WIDTH-1 downto 0); @@ -202,15 +202,11 @@ end process procFile; procDelay : process(CLK) - -- Process to delay start of first event output by required amount. - variable COUNT : natural := 0; + -- Process to delay start of first event output until clocks locked begin if rising_edge(CLK) then - if (COUNT < DELAY) then - COUNT := COUNT + 1; - WAITING <= true; - else + if (LOCKED = '1') then WAITING <= false; end if; end if; From 7073aa91ccabb528aef0f9a0f475d1840fd8c813 Mon Sep 17 00:00:00 2001 From: Andrew Hart Date: Wed, 25 Jun 2025 06:20:28 -0600 Subject: [PATCH 06/14] Added extra ports to get two clocks to SectorProcessor. --- IntegrationTests/DualFPGA/firmware/hdl/payload_f1.vhd | 5 ++++- IntegrationTests/DualFPGA/firmware/hdl/tf1_wrapper.vhd | 6 ++++-- IntegrationTests/DualFPGA/firmware/hdl/tf2_wrapper.vhd | 5 ++++- 3 files changed, 12 insertions(+), 4 deletions(-) diff --git a/IntegrationTests/DualFPGA/firmware/hdl/payload_f1.vhd b/IntegrationTests/DualFPGA/firmware/hdl/payload_f1.vhd index e430c31a90d..87c9fa94125 100644 --- a/IntegrationTests/DualFPGA/firmware/hdl/payload_f1.vhd +++ b/IntegrationTests/DualFPGA/firmware/hdl/payload_f1.vhd @@ -81,7 +81,10 @@ begin ----------------------------------------------------------------------------- tf1_wrapper_1 : entity work.tf1_wrapper port map ( - clk => clk_p, + -- FIXME: for now, the same 240 MHz clock goes to both ports; should be + -- updated with 360 MHz clock from EMP framework + clk240 => clk_p, + clk360 => clk_p, reset => sp_reset, IR_start => s_ir_start, IR_bx_in => s_bx, diff --git a/IntegrationTests/DualFPGA/firmware/hdl/tf1_wrapper.vhd b/IntegrationTests/DualFPGA/firmware/hdl/tf1_wrapper.vhd index 7e704b33d8b..020514f0ae2 100644 --- a/IntegrationTests/DualFPGA/firmware/hdl/tf1_wrapper.vhd +++ b/IntegrationTests/DualFPGA/firmware/hdl/tf1_wrapper.vhd @@ -26,7 +26,8 @@ use work.memUtil_aux_pkg_f1.all; entity tf1_wrapper is port ( - clk : in std_logic; + clk240 : in std_logic; + clk360 : in std_logic; reset : in std_logic; IR_start : in std_logic; IR_bx_in : in std_logic_vector(2 downto 0); @@ -47,7 +48,8 @@ begin -- architecture rtl SectorProcessor_1 : entity work.SectorProcessor port map ( - clk => clk, + clk240 => clk240, + clk360 => clk360, reset => reset, IR_start => IR_start, IR_bx_in => IR_bx_in, diff --git a/IntegrationTests/DualFPGA/firmware/hdl/tf2_wrapper.vhd b/IntegrationTests/DualFPGA/firmware/hdl/tf2_wrapper.vhd index d77764ff6b7..bbee5160ab6 100644 --- a/IntegrationTests/DualFPGA/firmware/hdl/tf2_wrapper.vhd +++ b/IntegrationTests/DualFPGA/firmware/hdl/tf2_wrapper.vhd @@ -62,7 +62,10 @@ begin -- architecture rtl SectorProcessor_1 : entity work.SectorProcessor port map ( - clk => clk, + -- Two clock ports are available on the SectorProcessor for FPGA2, + -- although only the 240-MHz clock is currently used. + clk240 => clk, + clk360 => clk, reset => reset, PC_start => PC_start, PC_bx_in => PC_bx_in, From c44c70f21a831ea5ea69fed295d7b8d7f05e69ea Mon Sep 17 00:00:00 2001 From: Andrew Hart Date: Thu, 26 Jun 2025 11:59:44 -0400 Subject: [PATCH 07/14] Added IP to generate 240 and 360 MHz clocks in TB. --- .../script/makeProject.tcl | 5 + .../CombinedConfig_FPGA1/script/runSim.tcl | 3 + .../script/makeProject.tcl | 5 + .../CombinedConfig_FPGA2/script/runSim.tcl | 3 + .../script/makeProject.tcl | 5 + .../script/runSim.tcl | 3 + .../script/makeProject.tcl | 5 + .../script/runSim.tcl | 3 + .../common/ip/clk_wiz_240_360.xci | 730 ++++++++++++++++++ .../common/script/synth_clk_wiz_240_360.tcl | 12 + 10 files changed, 774 insertions(+) create mode 100644 IntegrationTests/common/ip/clk_wiz_240_360.xci create mode 100644 IntegrationTests/common/script/synth_clk_wiz_240_360.tcl diff --git a/IntegrationTests/CombinedConfig_FPGA1/script/makeProject.tcl b/IntegrationTests/CombinedConfig_FPGA1/script/makeProject.tcl index deaececf372..2607579b8b5 100644 --- a/IntegrationTests/CombinedConfig_FPGA1/script/makeProject.tcl +++ b/IntegrationTests/CombinedConfig_FPGA1/script/makeProject.tcl @@ -171,6 +171,10 @@ add_files -fileset utils_1 [glob common/script/post.tcl] # Add HDL for TB add_files -fileset sim_1 [glob ../tb/tb_tf_top.vhd] +# Add clock wizard IP for TB +import_ip [glob common/ip/*.xci] +upgrade_ip [get_ips clk_wiz_240_360] + # Add constraints (clock etc.) add_files -fileset constrs_1 [glob common/hdl/constraints.xdc] add_files -fileset constrs_1 [glob soft_floorplan.xdc] @@ -179,6 +183,7 @@ add_files -fileset constrs_1 [glob soft_floorplan.xdc] set_property file_type {VHDL 2008} [get_files -filter {FILE_TYPE == VHDL}] set_property top -value ${topLevelHDL} -objects [get_filesets sim_1] set_property top -value "tb_tf_top" -objects [get_filesets sim_1] +set_property used_in_implementation false [get_files clk_wiz_240_360.xci] set_property xsim.simulate.runtime -value "0us" -objects [get_filesets sim_1] # Set 'synth_1` fileset properties diff --git a/IntegrationTests/CombinedConfig_FPGA1/script/runSim.tcl b/IntegrationTests/CombinedConfig_FPGA1/script/runSim.tcl index b019a0571fc..7e127a24bde 100644 --- a/IntegrationTests/CombinedConfig_FPGA1/script/runSim.tcl +++ b/IntegrationTests/CombinedConfig_FPGA1/script/runSim.tcl @@ -5,6 +5,9 @@ open_project $projName/$projName.xpr set_property simulator_language VHDL [current_project] reset_simulation sim_1 +# Run OOC synthesis for clock wizard +source ./common/script/synth_clk_wiz_240_360.tcl + # Create directory for output .txt file file delete -force dataOut/ file mkdir dataOut/ diff --git a/IntegrationTests/CombinedConfig_FPGA2/script/makeProject.tcl b/IntegrationTests/CombinedConfig_FPGA2/script/makeProject.tcl index 686bf911a47..c31e1098d75 100644 --- a/IntegrationTests/CombinedConfig_FPGA2/script/makeProject.tcl +++ b/IntegrationTests/CombinedConfig_FPGA2/script/makeProject.tcl @@ -157,6 +157,10 @@ add_files -fileset utils_1 [glob common/script/post.tcl] # Add HDL for TB add_files -fileset sim_1 [glob ../tb/tb_tf_top.vhd] +# Add clock wizard IP for TB +import_ip [glob common/ip/*.xci] +upgrade_ip [get_ips clk_wiz_240_360] + # Add constraints (clock etc.) add_files -fileset constrs_1 [glob common/hdl/constraints.xdc] add_files -fileset constrs_1 [glob floorplan.xdc] @@ -166,6 +170,7 @@ add_files -fileset constrs_1 [glob soft_floorplan.xdc] set_property file_type {VHDL 2008} [get_files -filter {FILE_TYPE == VHDL}] set_property top -value ${topLevelHDL} -objects [get_filesets sim_1] set_property top -value "tb_tf_top" -objects [get_filesets sim_1] +set_property used_in_implementation false [get_files clk_wiz_240_360.xci] set_property xsim.simulate.runtime -value "0us" -objects [get_filesets sim_1] # Set 'synth_1` fileset properties diff --git a/IntegrationTests/CombinedConfig_FPGA2/script/runSim.tcl b/IntegrationTests/CombinedConfig_FPGA2/script/runSim.tcl index 5462728dc2f..9f05890833e 100644 --- a/IntegrationTests/CombinedConfig_FPGA2/script/runSim.tcl +++ b/IntegrationTests/CombinedConfig_FPGA2/script/runSim.tcl @@ -5,6 +5,9 @@ open_project $projName/$projName.xpr set_property simulator_language VHDL [current_project] reset_simulation sim_1 +# Run OOC synthesis for clock wizard +source ./common/script/synth_clk_wiz_240_360.tcl + # Create directory for output .txt file file delete -force dataOut/ file mkdir dataOut/ diff --git a/IntegrationTests/ReducedCombinedConfig_FPGA1/script/makeProject.tcl b/IntegrationTests/ReducedCombinedConfig_FPGA1/script/makeProject.tcl index 82ec926c144..325fde96615 100644 --- a/IntegrationTests/ReducedCombinedConfig_FPGA1/script/makeProject.tcl +++ b/IntegrationTests/ReducedCombinedConfig_FPGA1/script/makeProject.tcl @@ -96,6 +96,10 @@ remove_files -fileset sources_1 [glob common/hdl/tf_mem_new.vhd] # Add HDL for TB add_files -fileset sim_1 [glob ../tb/tb_tf_top.vhd] +# Add clock wizard IP for TB +import_ip [glob common/ip/*.xci] +upgrade_ip [get_ips clk_wiz_240_360] + # Add constraints (clock etc.) add_files -fileset constrs_1 [glob common/hdl/constraints.xdc] add_files -fileset constrs_1 [glob soft_floorplan.xdc] @@ -104,6 +108,7 @@ add_files -fileset constrs_1 [glob soft_floorplan.xdc] set_property file_type {VHDL 2008} [get_files -filter {FILE_TYPE == VHDL}] set_property top -value ${topLevelHDL} -objects [get_filesets sim_1] set_property top -value "tb_tf_top" -objects [get_filesets sim_1] +set_property used_in_implementation false [get_files clk_wiz_240_360.xci] set_property xsim.simulate.runtime -value "0us" -objects [get_filesets sim_1] update_compile_order -fileset sources_1 diff --git a/IntegrationTests/ReducedCombinedConfig_FPGA1/script/runSim.tcl b/IntegrationTests/ReducedCombinedConfig_FPGA1/script/runSim.tcl index 5462728dc2f..9f05890833e 100644 --- a/IntegrationTests/ReducedCombinedConfig_FPGA1/script/runSim.tcl +++ b/IntegrationTests/ReducedCombinedConfig_FPGA1/script/runSim.tcl @@ -5,6 +5,9 @@ open_project $projName/$projName.xpr set_property simulator_language VHDL [current_project] reset_simulation sim_1 +# Run OOC synthesis for clock wizard +source ./common/script/synth_clk_wiz_240_360.tcl + # Create directory for output .txt file file delete -force dataOut/ file mkdir dataOut/ diff --git a/IntegrationTests/ReducedCombinedConfig_FPGA2/script/makeProject.tcl b/IntegrationTests/ReducedCombinedConfig_FPGA2/script/makeProject.tcl index 9c66a3f95dd..71bb1c63b7c 100644 --- a/IntegrationTests/ReducedCombinedConfig_FPGA2/script/makeProject.tcl +++ b/IntegrationTests/ReducedCombinedConfig_FPGA2/script/makeProject.tcl @@ -72,6 +72,10 @@ remove_files -fileset sources_1 [glob common/hdl/tf_mem_new.vhd] # Add HDL for TB add_files -fileset sim_1 [glob ../tb/tb_tf_top.vhd] +# Add clock wizard IP for TB +import_ip [glob common/ip/*.xci] +upgrade_ip [get_ips clk_wiz_240_360] + # Add constraints (clock etc.) add_files -fileset constrs_1 [glob common/hdl/constraints.xdc] add_files -fileset constrs_1 [glob floorplan.xdc] @@ -81,6 +85,7 @@ add_files -fileset constrs_1 [glob soft_floorplan.xdc] set_property file_type {VHDL 2008} [get_files -filter {FILE_TYPE == VHDL}] set_property top -value ${topLevelHDL} -objects [get_filesets sim_1] set_property top -value "tb_tf_top" -objects [get_filesets sim_1] +set_property used_in_implementation false [get_files clk_wiz_240_360.xci] set_property xsim.simulate.runtime -value "0us" -objects [get_filesets sim_1] update_compile_order -fileset sources_1 diff --git a/IntegrationTests/ReducedCombinedConfig_FPGA2/script/runSim.tcl b/IntegrationTests/ReducedCombinedConfig_FPGA2/script/runSim.tcl index 7aafdc895d2..e15c6f621d1 100644 --- a/IntegrationTests/ReducedCombinedConfig_FPGA2/script/runSim.tcl +++ b/IntegrationTests/ReducedCombinedConfig_FPGA2/script/runSim.tcl @@ -5,6 +5,9 @@ open_project $projName/$projName.xpr set_property simulator_language VHDL [current_project] reset_simulation sim_1 +# Run OOC synthesis for clock wizard +source ./common/script/synth_clk_wiz_240_360.tcl + # Create directory for output .txt file file delete -force dataOut/ file mkdir dataOut/ diff --git a/IntegrationTests/common/ip/clk_wiz_240_360.xci b/IntegrationTests/common/ip/clk_wiz_240_360.xci new file mode 100644 index 00000000000..7518d22ffb1 --- /dev/null +++ b/IntegrationTests/common/ip/clk_wiz_240_360.xci @@ -0,0 +1,730 @@ + + + xilinx.com + xci + unknown + 1.0 + + + clk_wiz_240_360 + + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + 1 + LEVEL_HIGH + + + + 100000000 + 0 + 0.000 + 0 + 0 + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + MMCM + cddcdone + cddcreq + 0000 + 0000 + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 250.0 + 100.0 + 0000 + 0000 + 240.00000 + 0000 + 0000 + 360.00000 + BUFG + 50.0 + false + 240.00000 + 0.000 + 50.000 + 240.000 + 0.000 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.0 + false + 360.00000 + 0.000 + 50.000 + 360.000 + 0.000 + 1 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + clk_in_sel + clk240 + clk360 + clk_out3 + clk_out4 + clk_out5 + clk_out6 + clk_out7 + CLK_VALID + NA + daddr + dclk + den + din + 0000 + 1 + 0.6666666666666666 + 2.4 + 2.4 + 2.4 + 2.4 + 2.4 + dout + drdy + dwe + 93.000 + 1.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + FDBK_AUTO + 0000 + 0000 + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary__________40.000____________0.010 + no_secondary_input_clock + input_clk_stopped + 0 + Units_MHz + No_Jitter + locked + 0000 + 0000 + 0000 + false + false + false + false + false + false + false + false + OPTIMIZED + 27.000 + 0.000 + FALSE + 25.000 + 10.0 + 4.500 + 0.500 + 0.000 + FALSE + 3 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + AUTO + 1 + None + 0.010 + 0.010 + FALSE + 128.000 + 2.000 + 2 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + __clk240__240.00000______0.000______50.0______145.640____181.935 + __clk360__360.00000______0.000______50.0______137.012____181.935 + no_CLK_OUT3_output + no_CLK_OUT4_output + no_CLK_OUT5_output + no_CLK_OUT6_output + no_CLK_OUT7_output + 0 + 0 + 128.000 + 1.000 + LATENCY + UNKNOWN + false + false + false + false + false + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + power_down + 0000 + 1 + clk + MMCM + AUTO + 40.000 + 0.010 + 10.000 + Single_ended_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + 0 + reset + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 100.0 + 100.0 + 100.0 + 100.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1600.000 + 800.000 + clk_wiz_240_360 + MMCM + false + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 250.0 + 0.010 + 100.0 + 0.010 + Buffer + 145.640 + false + 181.935 + 50.000 + 240.000 + 0.000 + 1 + true + Buffer + 137.012 + false + 181.935 + 50.000 + 360.000 + 0.000 + 1 + true + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + clk_in_sel + clk240 + false + clk360 + false + clk_out3 + false + clk_out4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + auto + clk_wiz_240_360 + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + false + false + false + false + false + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + locked + OPTIMIZED + 27.000 + 0.000 + false + 25.000 + 10.0 + 4.500 + 0.500 + 0.000 + false + 3 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + AUTO + 1 + None + 0.010 + 0.010 + false + 2 + false + false + LATENCY + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + 1 + clk + MMCM + mmcm_adv + 40.000 + 0.010 + 10.000 + Single_ended_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + REL_PRIMARY + Custom + reset + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + true + false + false + false + true + false + false + false + false + false + virtexuplus + + + xcvu13p + flga2577 + VHDL + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2019.2.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/IntegrationTests/common/script/synth_clk_wiz_240_360.tcl b/IntegrationTests/common/script/synth_clk_wiz_240_360.tcl new file mode 100644 index 00000000000..0a10f7f2042 --- /dev/null +++ b/IntegrationTests/common/script/synth_clk_wiz_240_360.tcl @@ -0,0 +1,12 @@ +# Run OOC synthesis for clock wizard +# (happens automatically when launching simulation from GUI, but not from CLI) +if {[get_filesets -quiet clk_wiz_240_360] eq ""} { + generate_target all [get_files clk_wiz_240_360.xci] + export_ip_user_files -of_objects [get_files clk_wiz_240_360.xci] -no_script -sync -force -quiet + export_simulation -of_objects [get_files clk_wiz_240_360.xci] -directory $projName/$projName.ip_user_files/sim_scripts -ip_user_files_dir $projName/$projName.ip_user_files -ipstatic_source_dir $projName/$projName.ip_user_files/ipstatic -lib_map_path [list {modelsim=$projName/$projName.cache/compile_simlib/modelsim} {questa=$projName/$projName.cache/compile_simlib/questa} {ies=$projName/$projName.cache/compile_simlib/ies} {xcelium=$projName/$projName.cache/compile_simlib/xcelium} {vcs=$projName/$projName.cache/compile_simlib/vcs} {riviera=$projName/$projName.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet + create_fileset -blockset clk_wiz_240_360 + set_property top clk_wiz_240_360 [get_fileset clk_wiz_240_360] + move_files -fileset [get_fileset clk_wiz_240_360] [get_files -of_objects [get_fileset sources_1] clk_wiz_240_360.xci] + launch_run clk_wiz_240_360_synth_1 + wait_on_run clk_wiz_240_360_synth_1 +} From db818ce641dfa0330380804ee8ad6d13ca83d2f8 Mon Sep 17 00:00:00 2001 From: Andrew Hart Date: Mon, 16 Jun 2025 12:50:57 -0400 Subject: [PATCH 08/14] Added 360 MHz clock and multicycle path constraints. --- IntegrationTests/common/hdl/constraints.xdc | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/IntegrationTests/common/hdl/constraints.xdc b/IntegrationTests/common/hdl/constraints.xdc index 501dc2011c9..4312a80f396 100644 --- a/IntegrationTests/common/hdl/constraints.xdc +++ b/IntegrationTests/common/hdl/constraints.xdc @@ -1,3 +1,9 @@ # 240 MHz -create_clock -period 4.160 -name clk -waveform {0.000 2.080} [get_ports clk] +create_clock -period 4.166 -name clk240 [get_ports clk240] +# 360 MHz +create_clock -period 2.777 -name clk360 [get_ports clk360] + +# Multicycle constraints from 360 to 240 MHz +set_multicycle_path 2 -setup -start -from [get_clocks clk360] -to [get_clocks clk240] +set_multicycle_path 1 -hold -from [get_clocks clk360] -to [get_clocks clk240] From 25c09c1ce1b3606ecebdcd967aba1ad217a7de3f Mon Sep 17 00:00:00 2001 From: Andrew Hart Date: Fri, 18 Jul 2025 09:29:57 -0400 Subject: [PATCH 09/14] Removed delay argument from calls to generator_hdl.py. --- emData/download.sh | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/emData/download.sh b/emData/download.sh index 2647abd58e8..adfa45be07b 100755 --- a/emData/download.sh +++ b/emData/download.sh @@ -172,30 +172,30 @@ sed -i 's/VMStubMERouter/VMSMERouter/g' fpga1_processingmodules.dat echo "Reduced CM FPGA1" -./generator_hdl.py ../../ --no_graph --mut IR -u 0 -d 2 -w fpga1_reducedcm_wires.dat -p fpga1_reducedcm_processingmodules.dat -m fpga1_reducedcm_memorymodules.dat -de 1 -sp 1 -./generator_hdl.py ../../ --no_graph --mut IR -u 0 -d 2 -w fpga1_reducedcm_wires.dat -p fpga1_reducedcm_processingmodules.dat -m fpga1_reducedcm_memorymodules.dat -de 1 -x -sp 1 +./generator_hdl.py ../../ --no_graph --mut IR -u 0 -d 2 -w fpga1_reducedcm_wires.dat -p fpga1_reducedcm_processingmodules.dat -m fpga1_reducedcm_memorymodules.dat -sp 1 +./generator_hdl.py ../../ --no_graph --mut IR -u 0 -d 2 -w fpga1_reducedcm_wires.dat -p fpga1_reducedcm_processingmodules.dat -m fpga1_reducedcm_memorymodules.dat -x -sp 1 ls -ltr *.vhd mkdir -p ../../IntegrationTests/ReducedCombinedConfig_FPGA1/{hdl,tb} mv -fv memUtil_pkg.vhd SectorProcessor.vhd SectorProcessorFull.vhd ../../IntegrationTests/ReducedCombinedConfig_FPGA1/hdl/ mv -fv tb_tf_top.vhd ../../IntegrationTests/ReducedCombinedConfig_FPGA1/tb/ echo "CM FPGA1" -./generator_hdl.py ../../ --no_graph --mut IR -u 0 -d 2 -w fpga1_wires.dat -p fpga1_processingmodules.dat -m fpga1_memorymodules.dat -de 1 -sp 1 -./generator_hdl.py ../../ --no_graph --mut IR -u 0 -d 2 -w fpga1_wires.dat -p fpga1_processingmodules.dat -m fpga1_memorymodules.dat -de 1 -x -sp 1 +./generator_hdl.py ../../ --no_graph --mut IR -u 0 -d 2 -w fpga1_wires.dat -p fpga1_processingmodules.dat -m fpga1_memorymodules.dat -sp 1 +./generator_hdl.py ../../ --no_graph --mut IR -u 0 -d 2 -w fpga1_wires.dat -p fpga1_processingmodules.dat -m fpga1_memorymodules.dat -x -sp 1 mkdir -p ../../IntegrationTests/CombinedConfig_FPGA1/{hdl,tb} mv -fv memUtil_pkg.vhd SectorProcessor.vhd SectorProcessorFull.vhd ../../IntegrationTests/CombinedConfig_FPGA1/hdl/ mv -fv tb_tf_top.vhd ../../IntegrationTests/CombinedConfig_FPGA1/tb/ echo "Reduced CM FPGA2" -./generator_hdl.py ../../ --no_graph --sp 2 --mut PC -u 0 -d 2 -w fpga2_reducedcm_wires.dat -p fpga2_reducedcm_processingmodules.dat -m fpga2_reducedcm_memorymodules.dat -de 1 -./generator_hdl.py ../../ --no_graph --sp 2 --mut PC -u 0 -d 2 -w fpga2_reducedcm_wires.dat -p fpga2_reducedcm_processingmodules.dat -m fpga2_reducedcm_memorymodules.dat -de 1 -x +./generator_hdl.py ../../ --no_graph --sp 2 --mut PC -u 0 -d 2 -w fpga2_reducedcm_wires.dat -p fpga2_reducedcm_processingmodules.dat -m fpga2_reducedcm_memorymodules.dat +./generator_hdl.py ../../ --no_graph --sp 2 --mut PC -u 0 -d 2 -w fpga2_reducedcm_wires.dat -p fpga2_reducedcm_processingmodules.dat -m fpga2_reducedcm_memorymodules.dat -x mkdir -p ../../IntegrationTests/ReducedCombinedConfig_FPGA2/{hdl,tb} mv -fv memUtil_pkg.vhd SectorProcessor.vhd SectorProcessorFull.vhd ../../IntegrationTests/ReducedCombinedConfig_FPGA2/hdl/ mv -fv tb_tf_top.vhd ../../IntegrationTests/ReducedCombinedConfig_FPGA2/tb/ echo "CM FPGA2" -./generator_hdl.py ../../ --no_graph --sp 2 --mut PC -u 0 -d 2 -w fpga2_wires.dat -p fpga2_processingmodules.dat -m fpga2_memorymodules.dat -de 2 -./generator_hdl.py ../../ --no_graph --sp 2 --mut PC -u 0 -d 2 -w fpga2_wires.dat -p fpga2_processingmodules.dat -m fpga2_memorymodules.dat -de 2 -x +./generator_hdl.py ../../ --no_graph --sp 2 --mut PC -u 0 -d 2 -w fpga2_wires.dat -p fpga2_processingmodules.dat -m fpga2_memorymodules.dat +./generator_hdl.py ../../ --no_graph --sp 2 --mut PC -u 0 -d 2 -w fpga2_wires.dat -p fpga2_processingmodules.dat -m fpga2_memorymodules.dat -x mkdir -p ../../IntegrationTests/CombinedConfig_FPGA2/{hdl,tb} mv -fv memUtil_pkg.vhd SectorProcessor.vhd SectorProcessorFull.vhd ../../IntegrationTests/CombinedConfig_FPGA2/hdl/ mv -fv tb_tf_top.vhd ../../IntegrationTests/CombinedConfig_FPGA2/tb/ From e645a3d08bd610567833da1c948063f297643eed Mon Sep 17 00:00:00 2001 From: Andrew Hart Date: Tue, 22 Jul 2025 10:56:53 -0400 Subject: [PATCH 10/14] Updated floorplan for FPGA1. --- .../script/soft_floorplan.xdc | 444 ++++++++++++++---- 1 file changed, 348 insertions(+), 96 deletions(-) diff --git a/IntegrationTests/CombinedConfig_FPGA1/script/soft_floorplan.xdc b/IntegrationTests/CombinedConfig_FPGA1/script/soft_floorplan.xdc index db70f03b9b4..9c90443e455 100644 --- a/IntegrationTests/CombinedConfig_FPGA1/script/soft_floorplan.xdc +++ b/IntegrationTests/CombinedConfig_FPGA1/script/soft_floorplan.xdc @@ -781,6 +781,10 @@ set_property USER_SLR_ASSIGNMENT AS_D1PHIAn1_DELAY_MEM_1 [get_cells {AS_D1PHIAn1 set_property USER_SLR_ASSIGNMENT AS_D1PHIAn1_DELAY_START_BX_1 [get_cells {AS_D1PHIAn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D1PHIAn1_DELAY_MEM_2 [get_cells {AS_D1PHIAn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D1PHIAn1_DELAY_START_BX_2 [get_cells {AS_D1PHIAn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D1PHIAn1_STREAM_DELAY_MEM_1 [get_cells {AS_D1PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D1PHIAn1_STREAM_DELAY_START_BX_1 [get_cells {AS_D1PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D1PHIAn1_STREAM_DELAY_MEM_2 [get_cells {AS_D1PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D1PHIAn1_STREAM_DELAY_START_BX_2 [get_cells {AS_D1PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D1PHIB_DM_DELAY_MEM_1 [get_cells {AS_D1PHIB_DM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D1PHIB_DM_DELAY_START_BX_1 [get_cells {AS_D1PHIB_DM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D1PHIB_DM_DELAY_MEM_2 [get_cells {AS_D1PHIB_DM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -805,6 +809,10 @@ set_property USER_SLR_ASSIGNMENT AS_D1PHIBn1_DELAY_MEM_1 [get_cells {AS_D1PHIBn1 set_property USER_SLR_ASSIGNMENT AS_D1PHIBn1_DELAY_START_BX_1 [get_cells {AS_D1PHIBn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D1PHIBn1_DELAY_MEM_2 [get_cells {AS_D1PHIBn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D1PHIBn1_DELAY_START_BX_2 [get_cells {AS_D1PHIBn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D1PHIBn1_STREAM_DELAY_MEM_1 [get_cells {AS_D1PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D1PHIBn1_STREAM_DELAY_START_BX_1 [get_cells {AS_D1PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D1PHIBn1_STREAM_DELAY_MEM_2 [get_cells {AS_D1PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D1PHIBn1_STREAM_DELAY_START_BX_2 [get_cells {AS_D1PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D1PHIC_DL_DELAY_MEM_1 [get_cells {AS_D1PHIC_DL_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D1PHIC_DL_DELAY_START_BX_1 [get_cells {AS_D1PHIC_DL_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D1PHIC_DL_DELAY_MEM_2 [get_cells {AS_D1PHIC_DL_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -829,6 +837,10 @@ set_property USER_SLR_ASSIGNMENT AS_D1PHICn1_DELAY_MEM_1 [get_cells {AS_D1PHICn1 set_property USER_SLR_ASSIGNMENT AS_D1PHICn1_DELAY_START_BX_1 [get_cells {AS_D1PHICn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D1PHICn1_DELAY_MEM_2 [get_cells {AS_D1PHICn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D1PHICn1_DELAY_START_BX_2 [get_cells {AS_D1PHICn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D1PHICn1_STREAM_DELAY_MEM_1 [get_cells {AS_D1PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D1PHICn1_STREAM_DELAY_START_BX_1 [get_cells {AS_D1PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D1PHICn1_STREAM_DELAY_MEM_2 [get_cells {AS_D1PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D1PHICn1_STREAM_DELAY_START_BX_2 [get_cells {AS_D1PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D1PHID_DM_DELAY_MEM_1 [get_cells {AS_D1PHID_DM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D1PHID_DM_DELAY_START_BX_1 [get_cells {AS_D1PHID_DM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D1PHID_DM_DELAY_MEM_2 [get_cells {AS_D1PHID_DM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -849,6 +861,10 @@ set_property USER_SLR_ASSIGNMENT AS_D1PHIDn1_DELAY_MEM_1 [get_cells {AS_D1PHIDn1 set_property USER_SLR_ASSIGNMENT AS_D1PHIDn1_DELAY_START_BX_1 [get_cells {AS_D1PHIDn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D1PHIDn1_DELAY_MEM_2 [get_cells {AS_D1PHIDn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D1PHIDn1_DELAY_START_BX_2 [get_cells {AS_D1PHIDn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D1PHIDn1_STREAM_DELAY_MEM_1 [get_cells {AS_D1PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D1PHIDn1_STREAM_DELAY_START_BX_1 [get_cells {AS_D1PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D1PHIDn1_STREAM_DELAY_MEM_2 [get_cells {AS_D1PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D1PHIDn1_STREAM_DELAY_START_BX_2 [get_cells {AS_D1PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D2PHIA_D_D1A_DELAY_MEM_1 [get_cells {AS_D2PHIA_D_D1A_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D2PHIA_D_D1A_DELAY_START_BX_1 [get_cells {AS_D2PHIA_D_D1A_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D2PHIA_D_D1A_DELAY_MEM_2 [get_cells {AS_D2PHIA_D_D1A_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -857,6 +873,10 @@ set_property USER_SLR_ASSIGNMENT AS_D2PHIAn1_DELAY_MEM_1 [get_cells {AS_D2PHIAn1 set_property USER_SLR_ASSIGNMENT AS_D2PHIAn1_DELAY_START_BX_1 [get_cells {AS_D2PHIAn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D2PHIAn1_DELAY_MEM_2 [get_cells {AS_D2PHIAn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D2PHIAn1_DELAY_START_BX_2 [get_cells {AS_D2PHIAn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D2PHIAn1_STREAM_DELAY_MEM_1 [get_cells {AS_D2PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D2PHIAn1_STREAM_DELAY_START_BX_1 [get_cells {AS_D2PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D2PHIAn1_STREAM_DELAY_MEM_2 [get_cells {AS_D2PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D2PHIAn1_STREAM_DELAY_START_BX_2 [get_cells {AS_D2PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D2PHIB_D_D1B_DELAY_MEM_1 [get_cells {AS_D2PHIB_D_D1B_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D2PHIB_D_D1B_DELAY_START_BX_1 [get_cells {AS_D2PHIB_D_D1B_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D2PHIB_D_D1B_DELAY_MEM_2 [get_cells {AS_D2PHIB_D_D1B_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -865,6 +885,10 @@ set_property USER_SLR_ASSIGNMENT AS_D2PHIBn1_DELAY_MEM_1 [get_cells {AS_D2PHIBn1 set_property USER_SLR_ASSIGNMENT AS_D2PHIBn1_DELAY_START_BX_1 [get_cells {AS_D2PHIBn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D2PHIBn1_DELAY_MEM_2 [get_cells {AS_D2PHIBn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D2PHIBn1_DELAY_START_BX_2 [get_cells {AS_D2PHIBn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D2PHIBn1_STREAM_DELAY_MEM_1 [get_cells {AS_D2PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D2PHIBn1_STREAM_DELAY_START_BX_1 [get_cells {AS_D2PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D2PHIBn1_STREAM_DELAY_MEM_2 [get_cells {AS_D2PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D2PHIBn1_STREAM_DELAY_START_BX_2 [get_cells {AS_D2PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D2PHIC_D_D1C_DELAY_MEM_1 [get_cells {AS_D2PHIC_D_D1C_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D2PHIC_D_D1C_DELAY_START_BX_1 [get_cells {AS_D2PHIC_D_D1C_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D2PHIC_D_D1C_DELAY_MEM_2 [get_cells {AS_D2PHIC_D_D1C_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -873,6 +897,10 @@ set_property USER_SLR_ASSIGNMENT AS_D2PHICn1_DELAY_MEM_1 [get_cells {AS_D2PHICn1 set_property USER_SLR_ASSIGNMENT AS_D2PHICn1_DELAY_START_BX_1 [get_cells {AS_D2PHICn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D2PHICn1_DELAY_MEM_2 [get_cells {AS_D2PHICn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D2PHICn1_DELAY_START_BX_2 [get_cells {AS_D2PHICn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D2PHICn1_STREAM_DELAY_MEM_1 [get_cells {AS_D2PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D2PHICn1_STREAM_DELAY_START_BX_1 [get_cells {AS_D2PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D2PHICn1_STREAM_DELAY_MEM_2 [get_cells {AS_D2PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D2PHICn1_STREAM_DELAY_START_BX_2 [get_cells {AS_D2PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D2PHID_D_D1D_DELAY_MEM_1 [get_cells {AS_D2PHID_D_D1D_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D2PHID_D_D1D_DELAY_START_BX_1 [get_cells {AS_D2PHID_D_D1D_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D2PHID_D_D1D_DELAY_MEM_2 [get_cells {AS_D2PHID_D_D1D_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -881,6 +909,10 @@ set_property USER_SLR_ASSIGNMENT AS_D2PHIDn1_DELAY_MEM_1 [get_cells {AS_D2PHIDn1 set_property USER_SLR_ASSIGNMENT AS_D2PHIDn1_DELAY_START_BX_1 [get_cells {AS_D2PHIDn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D2PHIDn1_DELAY_MEM_2 [get_cells {AS_D2PHIDn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D2PHIDn1_DELAY_START_BX_2 [get_cells {AS_D2PHIDn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D2PHIDn1_STREAM_DELAY_MEM_1 [get_cells {AS_D2PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D2PHIDn1_STREAM_DELAY_START_BX_1 [get_cells {AS_D2PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D2PHIDn1_STREAM_DELAY_MEM_2 [get_cells {AS_D2PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D2PHIDn1_STREAM_DELAY_START_BX_2 [get_cells {AS_D2PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D3PHIA_DM_DELAY_MEM_1 [get_cells {AS_D3PHIA_DM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D3PHIA_DM_DELAY_START_BX_1 [get_cells {AS_D3PHIA_DM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D3PHIA_DM_DELAY_MEM_2 [get_cells {AS_D3PHIA_DM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -889,6 +921,10 @@ set_property USER_SLR_ASSIGNMENT AS_D3PHIAn1_DELAY_MEM_1 [get_cells {AS_D3PHIAn1 set_property USER_SLR_ASSIGNMENT AS_D3PHIAn1_DELAY_START_BX_1 [get_cells {AS_D3PHIAn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D3PHIAn1_DELAY_MEM_2 [get_cells {AS_D3PHIAn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D3PHIAn1_DELAY_START_BX_2 [get_cells {AS_D3PHIAn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D3PHIAn1_STREAM_DELAY_MEM_1 [get_cells {AS_D3PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D3PHIAn1_STREAM_DELAY_START_BX_1 [get_cells {AS_D3PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D3PHIAn1_STREAM_DELAY_MEM_2 [get_cells {AS_D3PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D3PHIAn1_STREAM_DELAY_START_BX_2 [get_cells {AS_D3PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D3PHIB_DM_DELAY_MEM_1 [get_cells {AS_D3PHIB_DM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D3PHIB_DM_DELAY_START_BX_1 [get_cells {AS_D3PHIB_DM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D3PHIB_DM_DELAY_MEM_2 [get_cells {AS_D3PHIB_DM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -901,6 +937,10 @@ set_property USER_SLR_ASSIGNMENT AS_D3PHIBn1_DELAY_MEM_1 [get_cells {AS_D3PHIBn1 set_property USER_SLR_ASSIGNMENT AS_D3PHIBn1_DELAY_START_BX_1 [get_cells {AS_D3PHIBn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D3PHIBn1_DELAY_MEM_2 [get_cells {AS_D3PHIBn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D3PHIBn1_DELAY_START_BX_2 [get_cells {AS_D3PHIBn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D3PHIBn1_STREAM_DELAY_MEM_1 [get_cells {AS_D3PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D3PHIBn1_STREAM_DELAY_START_BX_1 [get_cells {AS_D3PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D3PHIBn1_STREAM_DELAY_MEM_2 [get_cells {AS_D3PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D3PHIBn1_STREAM_DELAY_START_BX_2 [get_cells {AS_D3PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D3PHIC_DL_DELAY_MEM_1 [get_cells {AS_D3PHIC_DL_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D3PHIC_DL_DELAY_START_BX_1 [get_cells {AS_D3PHIC_DL_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D3PHIC_DL_DELAY_MEM_2 [get_cells {AS_D3PHIC_DL_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -913,6 +953,10 @@ set_property USER_SLR_ASSIGNMENT AS_D3PHICn1_DELAY_MEM_1 [get_cells {AS_D3PHICn1 set_property USER_SLR_ASSIGNMENT AS_D3PHICn1_DELAY_START_BX_1 [get_cells {AS_D3PHICn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D3PHICn1_DELAY_MEM_2 [get_cells {AS_D3PHICn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D3PHICn1_DELAY_START_BX_2 [get_cells {AS_D3PHICn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D3PHICn1_STREAM_DELAY_MEM_1 [get_cells {AS_D3PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D3PHICn1_STREAM_DELAY_START_BX_1 [get_cells {AS_D3PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D3PHICn1_STREAM_DELAY_MEM_2 [get_cells {AS_D3PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D3PHICn1_STREAM_DELAY_START_BX_2 [get_cells {AS_D3PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D3PHID_DM_DELAY_MEM_1 [get_cells {AS_D3PHID_DM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D3PHID_DM_DELAY_START_BX_1 [get_cells {AS_D3PHID_DM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D3PHID_DM_DELAY_MEM_2 [get_cells {AS_D3PHID_DM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -921,6 +965,10 @@ set_property USER_SLR_ASSIGNMENT AS_D3PHIDn1_DELAY_MEM_1 [get_cells {AS_D3PHIDn1 set_property USER_SLR_ASSIGNMENT AS_D3PHIDn1_DELAY_START_BX_1 [get_cells {AS_D3PHIDn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D3PHIDn1_DELAY_MEM_2 [get_cells {AS_D3PHIDn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D3PHIDn1_DELAY_START_BX_2 [get_cells {AS_D3PHIDn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D3PHIDn1_STREAM_DELAY_MEM_1 [get_cells {AS_D3PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D3PHIDn1_STREAM_DELAY_START_BX_1 [get_cells {AS_D3PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D3PHIDn1_STREAM_DELAY_MEM_2 [get_cells {AS_D3PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D3PHIDn1_STREAM_DELAY_START_BX_2 [get_cells {AS_D3PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D4PHIA_D_D3A_DELAY_MEM_1 [get_cells {AS_D4PHIA_D_D3A_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D4PHIA_D_D3A_DELAY_START_BX_1 [get_cells {AS_D4PHIA_D_D3A_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D4PHIA_D_D3A_DELAY_MEM_2 [get_cells {AS_D4PHIA_D_D3A_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -929,6 +977,10 @@ set_property USER_SLR_ASSIGNMENT AS_D4PHIAn1_DELAY_MEM_1 [get_cells {AS_D4PHIAn1 set_property USER_SLR_ASSIGNMENT AS_D4PHIAn1_DELAY_START_BX_1 [get_cells {AS_D4PHIAn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D4PHIAn1_DELAY_MEM_2 [get_cells {AS_D4PHIAn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D4PHIAn1_DELAY_START_BX_2 [get_cells {AS_D4PHIAn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D4PHIAn1_STREAM_DELAY_MEM_1 [get_cells {AS_D4PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D4PHIAn1_STREAM_DELAY_START_BX_1 [get_cells {AS_D4PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D4PHIAn1_STREAM_DELAY_MEM_2 [get_cells {AS_D4PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D4PHIAn1_STREAM_DELAY_START_BX_2 [get_cells {AS_D4PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D4PHIB_D_D3B_DELAY_MEM_1 [get_cells {AS_D4PHIB_D_D3B_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D4PHIB_D_D3B_DELAY_START_BX_1 [get_cells {AS_D4PHIB_D_D3B_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D4PHIB_D_D3B_DELAY_MEM_2 [get_cells {AS_D4PHIB_D_D3B_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -937,6 +989,10 @@ set_property USER_SLR_ASSIGNMENT AS_D4PHIBn1_DELAY_MEM_1 [get_cells {AS_D4PHIBn1 set_property USER_SLR_ASSIGNMENT AS_D4PHIBn1_DELAY_START_BX_1 [get_cells {AS_D4PHIBn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D4PHIBn1_DELAY_MEM_2 [get_cells {AS_D4PHIBn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D4PHIBn1_DELAY_START_BX_2 [get_cells {AS_D4PHIBn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D4PHIBn1_STREAM_DELAY_MEM_1 [get_cells {AS_D4PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D4PHIBn1_STREAM_DELAY_START_BX_1 [get_cells {AS_D4PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D4PHIBn1_STREAM_DELAY_MEM_2 [get_cells {AS_D4PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D4PHIBn1_STREAM_DELAY_START_BX_2 [get_cells {AS_D4PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D4PHIC_D_D3C_DELAY_MEM_1 [get_cells {AS_D4PHIC_D_D3C_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D4PHIC_D_D3C_DELAY_START_BX_1 [get_cells {AS_D4PHIC_D_D3C_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D4PHIC_D_D3C_DELAY_MEM_2 [get_cells {AS_D4PHIC_D_D3C_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -945,6 +1001,10 @@ set_property USER_SLR_ASSIGNMENT AS_D4PHICn1_DELAY_MEM_1 [get_cells {AS_D4PHICn1 set_property USER_SLR_ASSIGNMENT AS_D4PHICn1_DELAY_START_BX_1 [get_cells {AS_D4PHICn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D4PHICn1_DELAY_MEM_2 [get_cells {AS_D4PHICn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D4PHICn1_DELAY_START_BX_2 [get_cells {AS_D4PHICn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D4PHICn1_STREAM_DELAY_MEM_1 [get_cells {AS_D4PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D4PHICn1_STREAM_DELAY_START_BX_1 [get_cells {AS_D4PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D4PHICn1_STREAM_DELAY_MEM_2 [get_cells {AS_D4PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D4PHICn1_STREAM_DELAY_START_BX_2 [get_cells {AS_D4PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D4PHID_D_D3D_DELAY_MEM_1 [get_cells {AS_D4PHID_D_D3D_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D4PHID_D_D3D_DELAY_START_BX_1 [get_cells {AS_D4PHID_D_D3D_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D4PHID_D_D3D_DELAY_MEM_2 [get_cells {AS_D4PHID_D_D3D_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -953,22 +1013,42 @@ set_property USER_SLR_ASSIGNMENT AS_D4PHIDn1_DELAY_MEM_1 [get_cells {AS_D4PHIDn1 set_property USER_SLR_ASSIGNMENT AS_D4PHIDn1_DELAY_START_BX_1 [get_cells {AS_D4PHIDn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D4PHIDn1_DELAY_MEM_2 [get_cells {AS_D4PHIDn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D4PHIDn1_DELAY_START_BX_2 [get_cells {AS_D4PHIDn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D4PHIDn1_STREAM_DELAY_MEM_1 [get_cells {AS_D4PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D4PHIDn1_STREAM_DELAY_START_BX_1 [get_cells {AS_D4PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D4PHIDn1_STREAM_DELAY_MEM_2 [get_cells {AS_D4PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D4PHIDn1_STREAM_DELAY_START_BX_2 [get_cells {AS_D4PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D5PHIAn1_DELAY_MEM_1 [get_cells {AS_D5PHIAn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D5PHIAn1_DELAY_START_BX_1 [get_cells {AS_D5PHIAn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D5PHIAn1_DELAY_MEM_2 [get_cells {AS_D5PHIAn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D5PHIAn1_DELAY_START_BX_2 [get_cells {AS_D5PHIAn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D5PHIAn1_STREAM_DELAY_MEM_1 [get_cells {AS_D5PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D5PHIAn1_STREAM_DELAY_START_BX_1 [get_cells {AS_D5PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D5PHIAn1_STREAM_DELAY_MEM_2 [get_cells {AS_D5PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D5PHIAn1_STREAM_DELAY_START_BX_2 [get_cells {AS_D5PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D5PHIBn1_DELAY_MEM_1 [get_cells {AS_D5PHIBn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D5PHIBn1_DELAY_START_BX_1 [get_cells {AS_D5PHIBn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D5PHIBn1_DELAY_MEM_2 [get_cells {AS_D5PHIBn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D5PHIBn1_DELAY_START_BX_2 [get_cells {AS_D5PHIBn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D5PHIBn1_STREAM_DELAY_MEM_1 [get_cells {AS_D5PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D5PHIBn1_STREAM_DELAY_START_BX_1 [get_cells {AS_D5PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D5PHIBn1_STREAM_DELAY_MEM_2 [get_cells {AS_D5PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D5PHIBn1_STREAM_DELAY_START_BX_2 [get_cells {AS_D5PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D5PHICn1_DELAY_MEM_1 [get_cells {AS_D5PHICn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D5PHICn1_DELAY_START_BX_1 [get_cells {AS_D5PHICn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D5PHICn1_DELAY_MEM_2 [get_cells {AS_D5PHICn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D5PHICn1_DELAY_START_BX_2 [get_cells {AS_D5PHICn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D5PHICn1_STREAM_DELAY_MEM_1 [get_cells {AS_D5PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D5PHICn1_STREAM_DELAY_START_BX_1 [get_cells {AS_D5PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D5PHICn1_STREAM_DELAY_MEM_2 [get_cells {AS_D5PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D5PHICn1_STREAM_DELAY_START_BX_2 [get_cells {AS_D5PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D5PHIDn1_DELAY_MEM_1 [get_cells {AS_D5PHIDn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D5PHIDn1_DELAY_START_BX_1 [get_cells {AS_D5PHIDn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_D5PHIDn1_DELAY_MEM_2 [get_cells {AS_D5PHIDn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_D5PHIDn1_DELAY_START_BX_2 [get_cells {AS_D5PHIDn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D5PHIDn1_STREAM_DELAY_MEM_1 [get_cells {AS_D5PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D5PHIDn1_STREAM_DELAY_START_BX_1 [get_cells {AS_D5PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_D5PHIDn1_STREAM_DELAY_MEM_2 [get_cells {AS_D5PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_D5PHIDn1_STREAM_DELAY_START_BX_2 [get_cells {AS_D5PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L1PHIA_BE_DELAY_MEM_1 [get_cells {AS_L1PHIA_BE_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L1PHIA_BE_DELAY_START_BX_1 [get_cells {AS_L1PHIA_BE_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L1PHIA_BE_DELAY_MEM_2 [get_cells {AS_L1PHIA_BE_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -985,6 +1065,10 @@ set_property USER_SLR_ASSIGNMENT AS_L1PHIAn1_DELAY_MEM_1 [get_cells {AS_L1PHIAn1 set_property USER_SLR_ASSIGNMENT AS_L1PHIAn1_DELAY_START_BX_1 [get_cells {AS_L1PHIAn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L1PHIAn1_DELAY_MEM_2 [get_cells {AS_L1PHIAn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L1PHIAn1_DELAY_START_BX_2 [get_cells {AS_L1PHIAn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L1PHIAn1_STREAM_DELAY_MEM_1 [get_cells {AS_L1PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L1PHIAn1_STREAM_DELAY_START_BX_1 [get_cells {AS_L1PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L1PHIAn1_STREAM_DELAY_MEM_2 [get_cells {AS_L1PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L1PHIAn1_STREAM_DELAY_START_BX_2 [get_cells {AS_L1PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L1PHIB_BA_DELAY_MEM_1 [get_cells {AS_L1PHIB_BA_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L1PHIB_BA_DELAY_START_BX_1 [get_cells {AS_L1PHIB_BA_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L1PHIB_BA_DELAY_MEM_2 [get_cells {AS_L1PHIB_BA_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -1009,6 +1093,10 @@ set_property USER_SLR_ASSIGNMENT AS_L1PHIBn1_DELAY_MEM_1 [get_cells {AS_L1PHIBn1 set_property USER_SLR_ASSIGNMENT AS_L1PHIBn1_DELAY_START_BX_1 [get_cells {AS_L1PHIBn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L1PHIBn1_DELAY_MEM_2 [get_cells {AS_L1PHIBn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L1PHIBn1_DELAY_START_BX_2 [get_cells {AS_L1PHIBn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L1PHIBn1_STREAM_DELAY_MEM_1 [get_cells {AS_L1PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L1PHIBn1_STREAM_DELAY_START_BX_1 [get_cells {AS_L1PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L1PHIBn1_STREAM_DELAY_MEM_2 [get_cells {AS_L1PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L1PHIBn1_STREAM_DELAY_START_BX_2 [get_cells {AS_L1PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L1PHIC_BB_DELAY_MEM_1 [get_cells {AS_L1PHIC_BB_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L1PHIC_BB_DELAY_START_BX_1 [get_cells {AS_L1PHIC_BB_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L1PHIC_BB_DELAY_MEM_2 [get_cells {AS_L1PHIC_BB_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -1033,6 +1121,10 @@ set_property USER_SLR_ASSIGNMENT AS_L1PHICn1_DELAY_MEM_1 [get_cells {AS_L1PHICn1 set_property USER_SLR_ASSIGNMENT AS_L1PHICn1_DELAY_START_BX_1 [get_cells {AS_L1PHICn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L1PHICn1_DELAY_MEM_2 [get_cells {AS_L1PHICn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L1PHICn1_DELAY_START_BX_2 [get_cells {AS_L1PHICn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L1PHICn1_STREAM_DELAY_MEM_1 [get_cells {AS_L1PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L1PHICn1_STREAM_DELAY_START_BX_1 [get_cells {AS_L1PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L1PHICn1_STREAM_DELAY_MEM_2 [get_cells {AS_L1PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L1PHICn1_STREAM_DELAY_START_BX_2 [get_cells {AS_L1PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L1PHID_BA_DELAY_MEM_1 [get_cells {AS_L1PHID_BA_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L1PHID_BA_DELAY_START_BX_1 [get_cells {AS_L1PHID_BA_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L1PHID_BA_DELAY_MEM_2 [get_cells {AS_L1PHID_BA_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -1057,6 +1149,10 @@ set_property USER_SLR_ASSIGNMENT AS_L1PHIDn1_DELAY_MEM_1 [get_cells {AS_L1PHIDn1 set_property USER_SLR_ASSIGNMENT AS_L1PHIDn1_DELAY_START_BX_1 [get_cells {AS_L1PHIDn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L1PHIDn1_DELAY_MEM_2 [get_cells {AS_L1PHIDn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L1PHIDn1_DELAY_START_BX_2 [get_cells {AS_L1PHIDn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L1PHIDn1_STREAM_DELAY_MEM_1 [get_cells {AS_L1PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L1PHIDn1_STREAM_DELAY_START_BX_1 [get_cells {AS_L1PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L1PHIDn1_STREAM_DELAY_MEM_2 [get_cells {AS_L1PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L1PHIDn1_STREAM_DELAY_START_BX_2 [get_cells {AS_L1PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L1PHIE_BB_DELAY_MEM_1 [get_cells {AS_L1PHIE_BB_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L1PHIE_BB_DELAY_START_BX_1 [get_cells {AS_L1PHIE_BB_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L1PHIE_BB_DELAY_MEM_2 [get_cells {AS_L1PHIE_BB_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -1081,6 +1177,10 @@ set_property USER_SLR_ASSIGNMENT AS_L1PHIEn1_DELAY_MEM_1 [get_cells {AS_L1PHIEn1 set_property USER_SLR_ASSIGNMENT AS_L1PHIEn1_DELAY_START_BX_1 [get_cells {AS_L1PHIEn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L1PHIEn1_DELAY_MEM_2 [get_cells {AS_L1PHIEn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L1PHIEn1_DELAY_START_BX_2 [get_cells {AS_L1PHIEn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L1PHIEn1_STREAM_DELAY_MEM_1 [get_cells {AS_L1PHIEn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L1PHIEn1_STREAM_DELAY_START_BX_1 [get_cells {AS_L1PHIEn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L1PHIEn1_STREAM_DELAY_MEM_2 [get_cells {AS_L1PHIEn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L1PHIEn1_STREAM_DELAY_START_BX_2 [get_cells {AS_L1PHIEn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L1PHIF_BA_DELAY_MEM_1 [get_cells {AS_L1PHIF_BA_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L1PHIF_BA_DELAY_START_BX_1 [get_cells {AS_L1PHIF_BA_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L1PHIF_BA_DELAY_MEM_2 [get_cells {AS_L1PHIF_BA_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -1105,6 +1205,10 @@ set_property USER_SLR_ASSIGNMENT AS_L1PHIFn1_DELAY_MEM_1 [get_cells {AS_L1PHIFn1 set_property USER_SLR_ASSIGNMENT AS_L1PHIFn1_DELAY_START_BX_1 [get_cells {AS_L1PHIFn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L1PHIFn1_DELAY_MEM_2 [get_cells {AS_L1PHIFn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L1PHIFn1_DELAY_START_BX_2 [get_cells {AS_L1PHIFn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L1PHIFn1_STREAM_DELAY_MEM_1 [get_cells {AS_L1PHIFn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L1PHIFn1_STREAM_DELAY_START_BX_1 [get_cells {AS_L1PHIFn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L1PHIFn1_STREAM_DELAY_MEM_2 [get_cells {AS_L1PHIFn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L1PHIFn1_STREAM_DELAY_START_BX_2 [get_cells {AS_L1PHIFn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L1PHIG_BB_DELAY_MEM_1 [get_cells {AS_L1PHIG_BB_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L1PHIG_BB_DELAY_START_BX_1 [get_cells {AS_L1PHIG_BB_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L1PHIG_BB_DELAY_MEM_2 [get_cells {AS_L1PHIG_BB_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -1129,6 +1233,10 @@ set_property USER_SLR_ASSIGNMENT AS_L1PHIGn1_DELAY_MEM_1 [get_cells {AS_L1PHIGn1 set_property USER_SLR_ASSIGNMENT AS_L1PHIGn1_DELAY_START_BX_1 [get_cells {AS_L1PHIGn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L1PHIGn1_DELAY_MEM_2 [get_cells {AS_L1PHIGn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L1PHIGn1_DELAY_START_BX_2 [get_cells {AS_L1PHIGn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L1PHIGn1_STREAM_DELAY_MEM_1 [get_cells {AS_L1PHIGn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L1PHIGn1_STREAM_DELAY_START_BX_1 [get_cells {AS_L1PHIGn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L1PHIGn1_STREAM_DELAY_MEM_2 [get_cells {AS_L1PHIGn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L1PHIGn1_STREAM_DELAY_START_BX_2 [get_cells {AS_L1PHIGn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L1PHIH_BC_DELAY_MEM_1 [get_cells {AS_L1PHIH_BC_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L1PHIH_BC_DELAY_START_BX_1 [get_cells {AS_L1PHIH_BC_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L1PHIH_BC_DELAY_MEM_2 [get_cells {AS_L1PHIH_BC_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -1145,6 +1253,10 @@ set_property USER_SLR_ASSIGNMENT AS_L1PHIHn1_DELAY_MEM_1 [get_cells {AS_L1PHIHn1 set_property USER_SLR_ASSIGNMENT AS_L1PHIHn1_DELAY_START_BX_1 [get_cells {AS_L1PHIHn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L1PHIHn1_DELAY_MEM_2 [get_cells {AS_L1PHIHn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L1PHIHn1_DELAY_START_BX_2 [get_cells {AS_L1PHIHn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L1PHIHn1_STREAM_DELAY_MEM_1 [get_cells {AS_L1PHIHn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L1PHIHn1_STREAM_DELAY_START_BX_1 [get_cells {AS_L1PHIHn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L1PHIHn1_STREAM_DELAY_MEM_2 [get_cells {AS_L1PHIHn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L1PHIHn1_STREAM_DELAY_START_BX_2 [get_cells {AS_L1PHIHn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L2PHIA_BM_DELAY_MEM_1 [get_cells {AS_L2PHIA_BM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L2PHIA_BM_DELAY_START_BX_1 [get_cells {AS_L2PHIA_BM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L2PHIA_BM_DELAY_MEM_2 [get_cells {AS_L2PHIA_BM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -1169,6 +1281,10 @@ set_property USER_SLR_ASSIGNMENT AS_L2PHIAn1_DELAY_MEM_1 [get_cells {AS_L2PHIAn1 set_property USER_SLR_ASSIGNMENT AS_L2PHIAn1_DELAY_START_BX_1 [get_cells {AS_L2PHIAn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L2PHIAn1_DELAY_MEM_2 [get_cells {AS_L2PHIAn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L2PHIAn1_DELAY_START_BX_2 [get_cells {AS_L2PHIAn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L2PHIAn1_STREAM_DELAY_MEM_1 [get_cells {AS_L2PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L2PHIAn1_STREAM_DELAY_START_BX_1 [get_cells {AS_L2PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L2PHIAn1_STREAM_DELAY_MEM_2 [get_cells {AS_L2PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L2PHIAn1_STREAM_DELAY_START_BX_2 [get_cells {AS_L2PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L2PHIB_BM_DELAY_MEM_1 [get_cells {AS_L2PHIB_BM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L2PHIB_BM_DELAY_START_BX_1 [get_cells {AS_L2PHIB_BM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L2PHIB_BM_DELAY_MEM_2 [get_cells {AS_L2PHIB_BM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -1201,6 +1317,10 @@ set_property USER_SLR_ASSIGNMENT AS_L2PHIBn1_DELAY_MEM_1 [get_cells {AS_L2PHIBn1 set_property USER_SLR_ASSIGNMENT AS_L2PHIBn1_DELAY_START_BX_1 [get_cells {AS_L2PHIBn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L2PHIBn1_DELAY_MEM_2 [get_cells {AS_L2PHIBn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L2PHIBn1_DELAY_START_BX_2 [get_cells {AS_L2PHIBn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L2PHIBn1_STREAM_DELAY_MEM_1 [get_cells {AS_L2PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L2PHIBn1_STREAM_DELAY_START_BX_1 [get_cells {AS_L2PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L2PHIBn1_STREAM_DELAY_MEM_2 [get_cells {AS_L2PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L2PHIBn1_STREAM_DELAY_START_BX_2 [get_cells {AS_L2PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L2PHIC_BL_DELAY_MEM_1 [get_cells {AS_L2PHIC_BL_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L2PHIC_BL_DELAY_START_BX_1 [get_cells {AS_L2PHIC_BL_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L2PHIC_BL_DELAY_MEM_2 [get_cells {AS_L2PHIC_BL_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -1233,6 +1353,10 @@ set_property USER_SLR_ASSIGNMENT AS_L2PHICn1_DELAY_MEM_1 [get_cells {AS_L2PHICn1 set_property USER_SLR_ASSIGNMENT AS_L2PHICn1_DELAY_START_BX_1 [get_cells {AS_L2PHICn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L2PHICn1_DELAY_MEM_2 [get_cells {AS_L2PHICn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L2PHICn1_DELAY_START_BX_2 [get_cells {AS_L2PHICn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L2PHICn1_STREAM_DELAY_MEM_1 [get_cells {AS_L2PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L2PHICn1_STREAM_DELAY_START_BX_1 [get_cells {AS_L2PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L2PHICn1_STREAM_DELAY_MEM_2 [get_cells {AS_L2PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L2PHICn1_STREAM_DELAY_START_BX_2 [get_cells {AS_L2PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L2PHID_BM_DELAY_MEM_1 [get_cells {AS_L2PHID_BM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L2PHID_BM_DELAY_START_BX_1 [get_cells {AS_L2PHID_BM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L2PHID_BM_DELAY_MEM_2 [get_cells {AS_L2PHID_BM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -1257,6 +1381,10 @@ set_property USER_SLR_ASSIGNMENT AS_L2PHIDn1_DELAY_MEM_1 [get_cells {AS_L2PHIDn1 set_property USER_SLR_ASSIGNMENT AS_L2PHIDn1_DELAY_START_BX_1 [get_cells {AS_L2PHIDn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L2PHIDn1_DELAY_MEM_2 [get_cells {AS_L2PHIDn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L2PHIDn1_DELAY_START_BX_2 [get_cells {AS_L2PHIDn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L2PHIDn1_STREAM_DELAY_MEM_1 [get_cells {AS_L2PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L2PHIDn1_STREAM_DELAY_START_BX_1 [get_cells {AS_L2PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L2PHIDn1_STREAM_DELAY_MEM_2 [get_cells {AS_L2PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L2PHIDn1_STREAM_DELAY_START_BX_2 [get_cells {AS_L2PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L3PHIA_BM_DELAY_MEM_1 [get_cells {AS_L3PHIA_BM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L3PHIA_BM_DELAY_START_BX_1 [get_cells {AS_L3PHIA_BM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L3PHIA_BM_DELAY_MEM_2 [get_cells {AS_L3PHIA_BM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -1269,6 +1397,10 @@ set_property USER_SLR_ASSIGNMENT AS_L3PHIAn1_DELAY_MEM_1 [get_cells {AS_L3PHIAn1 set_property USER_SLR_ASSIGNMENT AS_L3PHIAn1_DELAY_START_BX_1 [get_cells {AS_L3PHIAn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L3PHIAn1_DELAY_MEM_2 [get_cells {AS_L3PHIAn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L3PHIAn1_DELAY_START_BX_2 [get_cells {AS_L3PHIAn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L3PHIAn1_STREAM_DELAY_MEM_1 [get_cells {AS_L3PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L3PHIAn1_STREAM_DELAY_START_BX_1 [get_cells {AS_L3PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L3PHIAn1_STREAM_DELAY_MEM_2 [get_cells {AS_L3PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L3PHIAn1_STREAM_DELAY_START_BX_2 [get_cells {AS_L3PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L3PHIB_BM_DELAY_MEM_1 [get_cells {AS_L3PHIB_BM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L3PHIB_BM_DELAY_START_BX_1 [get_cells {AS_L3PHIB_BM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L3PHIB_BM_DELAY_MEM_2 [get_cells {AS_L3PHIB_BM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -1285,6 +1417,10 @@ set_property USER_SLR_ASSIGNMENT AS_L3PHIBn1_DELAY_MEM_1 [get_cells {AS_L3PHIBn1 set_property USER_SLR_ASSIGNMENT AS_L3PHIBn1_DELAY_START_BX_1 [get_cells {AS_L3PHIBn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L3PHIBn1_DELAY_MEM_2 [get_cells {AS_L3PHIBn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L3PHIBn1_DELAY_START_BX_2 [get_cells {AS_L3PHIBn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L3PHIBn1_STREAM_DELAY_MEM_1 [get_cells {AS_L3PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L3PHIBn1_STREAM_DELAY_START_BX_1 [get_cells {AS_L3PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L3PHIBn1_STREAM_DELAY_MEM_2 [get_cells {AS_L3PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L3PHIBn1_STREAM_DELAY_START_BX_2 [get_cells {AS_L3PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L3PHIC_BL_DELAY_MEM_1 [get_cells {AS_L3PHIC_BL_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L3PHIC_BL_DELAY_START_BX_1 [get_cells {AS_L3PHIC_BL_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L3PHIC_BL_DELAY_MEM_2 [get_cells {AS_L3PHIC_BL_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -1301,6 +1437,10 @@ set_property USER_SLR_ASSIGNMENT AS_L3PHICn1_DELAY_MEM_1 [get_cells {AS_L3PHICn1 set_property USER_SLR_ASSIGNMENT AS_L3PHICn1_DELAY_START_BX_1 [get_cells {AS_L3PHICn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L3PHICn1_DELAY_MEM_2 [get_cells {AS_L3PHICn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L3PHICn1_DELAY_START_BX_2 [get_cells {AS_L3PHICn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L3PHICn1_STREAM_DELAY_MEM_1 [get_cells {AS_L3PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L3PHICn1_STREAM_DELAY_START_BX_1 [get_cells {AS_L3PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L3PHICn1_STREAM_DELAY_MEM_2 [get_cells {AS_L3PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L3PHICn1_STREAM_DELAY_START_BX_2 [get_cells {AS_L3PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L3PHID_BM_DELAY_MEM_1 [get_cells {AS_L3PHID_BM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L3PHID_BM_DELAY_START_BX_1 [get_cells {AS_L3PHID_BM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L3PHID_BM_DELAY_MEM_2 [get_cells {AS_L3PHID_BM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -1313,6 +1453,10 @@ set_property USER_SLR_ASSIGNMENT AS_L3PHIDn1_DELAY_MEM_1 [get_cells {AS_L3PHIDn1 set_property USER_SLR_ASSIGNMENT AS_L3PHIDn1_DELAY_START_BX_1 [get_cells {AS_L3PHIDn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L3PHIDn1_DELAY_MEM_2 [get_cells {AS_L3PHIDn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L3PHIDn1_DELAY_START_BX_2 [get_cells {AS_L3PHIDn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L3PHIDn1_STREAM_DELAY_MEM_1 [get_cells {AS_L3PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L3PHIDn1_STREAM_DELAY_START_BX_1 [get_cells {AS_L3PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L3PHIDn1_STREAM_DELAY_MEM_2 [get_cells {AS_L3PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L3PHIDn1_STREAM_DELAY_START_BX_2 [get_cells {AS_L3PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L4PHIA_B_L3A_DELAY_MEM_1 [get_cells {AS_L4PHIA_B_L3A_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L4PHIA_B_L3A_DELAY_START_BX_1 [get_cells {AS_L4PHIA_B_L3A_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L4PHIA_B_L3A_DELAY_MEM_2 [get_cells {AS_L4PHIA_B_L3A_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -1321,6 +1465,10 @@ set_property USER_SLR_ASSIGNMENT AS_L4PHIAn1_DELAY_MEM_1 [get_cells {AS_L4PHIAn1 set_property USER_SLR_ASSIGNMENT AS_L4PHIAn1_DELAY_START_BX_1 [get_cells {AS_L4PHIAn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L4PHIAn1_DELAY_MEM_2 [get_cells {AS_L4PHIAn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L4PHIAn1_DELAY_START_BX_2 [get_cells {AS_L4PHIAn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L4PHIAn1_STREAM_DELAY_MEM_1 [get_cells {AS_L4PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L4PHIAn1_STREAM_DELAY_START_BX_1 [get_cells {AS_L4PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L4PHIAn1_STREAM_DELAY_MEM_2 [get_cells {AS_L4PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L4PHIAn1_STREAM_DELAY_START_BX_2 [get_cells {AS_L4PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L4PHIB_B_L3B_DELAY_MEM_1 [get_cells {AS_L4PHIB_B_L3B_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L4PHIB_B_L3B_DELAY_START_BX_1 [get_cells {AS_L4PHIB_B_L3B_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L4PHIB_B_L3B_DELAY_MEM_2 [get_cells {AS_L4PHIB_B_L3B_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -1329,6 +1477,10 @@ set_property USER_SLR_ASSIGNMENT AS_L4PHIBn1_DELAY_MEM_1 [get_cells {AS_L4PHIBn1 set_property USER_SLR_ASSIGNMENT AS_L4PHIBn1_DELAY_START_BX_1 [get_cells {AS_L4PHIBn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L4PHIBn1_DELAY_MEM_2 [get_cells {AS_L4PHIBn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L4PHIBn1_DELAY_START_BX_2 [get_cells {AS_L4PHIBn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L4PHIBn1_STREAM_DELAY_MEM_1 [get_cells {AS_L4PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L4PHIBn1_STREAM_DELAY_START_BX_1 [get_cells {AS_L4PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L4PHIBn1_STREAM_DELAY_MEM_2 [get_cells {AS_L4PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L4PHIBn1_STREAM_DELAY_START_BX_2 [get_cells {AS_L4PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L4PHIC_B_L3C_DELAY_MEM_1 [get_cells {AS_L4PHIC_B_L3C_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L4PHIC_B_L3C_DELAY_START_BX_1 [get_cells {AS_L4PHIC_B_L3C_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L4PHIC_B_L3C_DELAY_MEM_2 [get_cells {AS_L4PHIC_B_L3C_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -1337,6 +1489,10 @@ set_property USER_SLR_ASSIGNMENT AS_L4PHICn1_DELAY_MEM_1 [get_cells {AS_L4PHICn1 set_property USER_SLR_ASSIGNMENT AS_L4PHICn1_DELAY_START_BX_1 [get_cells {AS_L4PHICn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L4PHICn1_DELAY_MEM_2 [get_cells {AS_L4PHICn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L4PHICn1_DELAY_START_BX_2 [get_cells {AS_L4PHICn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L4PHICn1_STREAM_DELAY_MEM_1 [get_cells {AS_L4PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L4PHICn1_STREAM_DELAY_START_BX_1 [get_cells {AS_L4PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L4PHICn1_STREAM_DELAY_MEM_2 [get_cells {AS_L4PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L4PHICn1_STREAM_DELAY_START_BX_2 [get_cells {AS_L4PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L4PHID_B_L3D_DELAY_MEM_1 [get_cells {AS_L4PHID_B_L3D_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L4PHID_B_L3D_DELAY_START_BX_1 [get_cells {AS_L4PHID_B_L3D_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L4PHID_B_L3D_DELAY_MEM_2 [get_cells {AS_L4PHID_B_L3D_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -1345,6 +1501,10 @@ set_property USER_SLR_ASSIGNMENT AS_L4PHIDn1_DELAY_MEM_1 [get_cells {AS_L4PHIDn1 set_property USER_SLR_ASSIGNMENT AS_L4PHIDn1_DELAY_START_BX_1 [get_cells {AS_L4PHIDn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L4PHIDn1_DELAY_MEM_2 [get_cells {AS_L4PHIDn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L4PHIDn1_DELAY_START_BX_2 [get_cells {AS_L4PHIDn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L4PHIDn1_STREAM_DELAY_MEM_1 [get_cells {AS_L4PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L4PHIDn1_STREAM_DELAY_START_BX_1 [get_cells {AS_L4PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L4PHIDn1_STREAM_DELAY_MEM_2 [get_cells {AS_L4PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L4PHIDn1_STREAM_DELAY_START_BX_2 [get_cells {AS_L4PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L5PHIA_BM_DELAY_MEM_1 [get_cells {AS_L5PHIA_BM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L5PHIA_BM_DELAY_START_BX_1 [get_cells {AS_L5PHIA_BM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L5PHIA_BM_DELAY_MEM_2 [get_cells {AS_L5PHIA_BM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -1353,6 +1513,10 @@ set_property USER_SLR_ASSIGNMENT AS_L5PHIAn1_DELAY_MEM_1 [get_cells {AS_L5PHIAn1 set_property USER_SLR_ASSIGNMENT AS_L5PHIAn1_DELAY_START_BX_1 [get_cells {AS_L5PHIAn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L5PHIAn1_DELAY_MEM_2 [get_cells {AS_L5PHIAn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L5PHIAn1_DELAY_START_BX_2 [get_cells {AS_L5PHIAn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L5PHIAn1_STREAM_DELAY_MEM_1 [get_cells {AS_L5PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L5PHIAn1_STREAM_DELAY_START_BX_1 [get_cells {AS_L5PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L5PHIAn1_STREAM_DELAY_MEM_2 [get_cells {AS_L5PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L5PHIAn1_STREAM_DELAY_START_BX_2 [get_cells {AS_L5PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L5PHIB_BM_DELAY_MEM_1 [get_cells {AS_L5PHIB_BM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L5PHIB_BM_DELAY_START_BX_1 [get_cells {AS_L5PHIB_BM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L5PHIB_BM_DELAY_MEM_2 [get_cells {AS_L5PHIB_BM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -1365,6 +1529,10 @@ set_property USER_SLR_ASSIGNMENT AS_L5PHIBn1_DELAY_MEM_1 [get_cells {AS_L5PHIBn1 set_property USER_SLR_ASSIGNMENT AS_L5PHIBn1_DELAY_START_BX_1 [get_cells {AS_L5PHIBn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L5PHIBn1_DELAY_MEM_2 [get_cells {AS_L5PHIBn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L5PHIBn1_DELAY_START_BX_2 [get_cells {AS_L5PHIBn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L5PHIBn1_STREAM_DELAY_MEM_1 [get_cells {AS_L5PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L5PHIBn1_STREAM_DELAY_START_BX_1 [get_cells {AS_L5PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L5PHIBn1_STREAM_DELAY_MEM_2 [get_cells {AS_L5PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L5PHIBn1_STREAM_DELAY_START_BX_2 [get_cells {AS_L5PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L5PHIC_BL_DELAY_MEM_1 [get_cells {AS_L5PHIC_BL_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L5PHIC_BL_DELAY_START_BX_1 [get_cells {AS_L5PHIC_BL_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L5PHIC_BL_DELAY_MEM_2 [get_cells {AS_L5PHIC_BL_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -1377,6 +1545,10 @@ set_property USER_SLR_ASSIGNMENT AS_L5PHICn1_DELAY_MEM_1 [get_cells {AS_L5PHICn1 set_property USER_SLR_ASSIGNMENT AS_L5PHICn1_DELAY_START_BX_1 [get_cells {AS_L5PHICn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L5PHICn1_DELAY_MEM_2 [get_cells {AS_L5PHICn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L5PHICn1_DELAY_START_BX_2 [get_cells {AS_L5PHICn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L5PHICn1_STREAM_DELAY_MEM_1 [get_cells {AS_L5PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L5PHICn1_STREAM_DELAY_START_BX_1 [get_cells {AS_L5PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L5PHICn1_STREAM_DELAY_MEM_2 [get_cells {AS_L5PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L5PHICn1_STREAM_DELAY_START_BX_2 [get_cells {AS_L5PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L5PHID_BM_DELAY_MEM_1 [get_cells {AS_L5PHID_BM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L5PHID_BM_DELAY_START_BX_1 [get_cells {AS_L5PHID_BM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L5PHID_BM_DELAY_MEM_2 [get_cells {AS_L5PHID_BM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -1385,6 +1557,10 @@ set_property USER_SLR_ASSIGNMENT AS_L5PHIDn1_DELAY_MEM_1 [get_cells {AS_L5PHIDn1 set_property USER_SLR_ASSIGNMENT AS_L5PHIDn1_DELAY_START_BX_1 [get_cells {AS_L5PHIDn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L5PHIDn1_DELAY_MEM_2 [get_cells {AS_L5PHIDn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L5PHIDn1_DELAY_START_BX_2 [get_cells {AS_L5PHIDn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L5PHIDn1_STREAM_DELAY_MEM_1 [get_cells {AS_L5PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L5PHIDn1_STREAM_DELAY_START_BX_1 [get_cells {AS_L5PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L5PHIDn1_STREAM_DELAY_MEM_2 [get_cells {AS_L5PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L5PHIDn1_STREAM_DELAY_START_BX_2 [get_cells {AS_L5PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L6PHIA_B_L5A_DELAY_MEM_1 [get_cells {AS_L6PHIA_B_L5A_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L6PHIA_B_L5A_DELAY_START_BX_1 [get_cells {AS_L6PHIA_B_L5A_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L6PHIA_B_L5A_DELAY_MEM_2 [get_cells {AS_L6PHIA_B_L5A_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -1393,6 +1569,10 @@ set_property USER_SLR_ASSIGNMENT AS_L6PHIAn1_DELAY_MEM_1 [get_cells {AS_L6PHIAn1 set_property USER_SLR_ASSIGNMENT AS_L6PHIAn1_DELAY_START_BX_1 [get_cells {AS_L6PHIAn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L6PHIAn1_DELAY_MEM_2 [get_cells {AS_L6PHIAn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L6PHIAn1_DELAY_START_BX_2 [get_cells {AS_L6PHIAn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L6PHIAn1_STREAM_DELAY_MEM_1 [get_cells {AS_L6PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L6PHIAn1_STREAM_DELAY_START_BX_1 [get_cells {AS_L6PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L6PHIAn1_STREAM_DELAY_MEM_2 [get_cells {AS_L6PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L6PHIAn1_STREAM_DELAY_START_BX_2 [get_cells {AS_L6PHIAn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L6PHIB_B_L5B_DELAY_MEM_1 [get_cells {AS_L6PHIB_B_L5B_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L6PHIB_B_L5B_DELAY_START_BX_1 [get_cells {AS_L6PHIB_B_L5B_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L6PHIB_B_L5B_DELAY_MEM_2 [get_cells {AS_L6PHIB_B_L5B_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -1401,6 +1581,10 @@ set_property USER_SLR_ASSIGNMENT AS_L6PHIBn1_DELAY_MEM_1 [get_cells {AS_L6PHIBn1 set_property USER_SLR_ASSIGNMENT AS_L6PHIBn1_DELAY_START_BX_1 [get_cells {AS_L6PHIBn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L6PHIBn1_DELAY_MEM_2 [get_cells {AS_L6PHIBn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L6PHIBn1_DELAY_START_BX_2 [get_cells {AS_L6PHIBn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L6PHIBn1_STREAM_DELAY_MEM_1 [get_cells {AS_L6PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L6PHIBn1_STREAM_DELAY_START_BX_1 [get_cells {AS_L6PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L6PHIBn1_STREAM_DELAY_MEM_2 [get_cells {AS_L6PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L6PHIBn1_STREAM_DELAY_START_BX_2 [get_cells {AS_L6PHIBn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L6PHIC_B_L5C_DELAY_MEM_1 [get_cells {AS_L6PHIC_B_L5C_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L6PHIC_B_L5C_DELAY_START_BX_1 [get_cells {AS_L6PHIC_B_L5C_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L6PHIC_B_L5C_DELAY_MEM_2 [get_cells {AS_L6PHIC_B_L5C_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -1409,6 +1593,10 @@ set_property USER_SLR_ASSIGNMENT AS_L6PHICn1_DELAY_MEM_1 [get_cells {AS_L6PHICn1 set_property USER_SLR_ASSIGNMENT AS_L6PHICn1_DELAY_START_BX_1 [get_cells {AS_L6PHICn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L6PHICn1_DELAY_MEM_2 [get_cells {AS_L6PHICn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L6PHICn1_DELAY_START_BX_2 [get_cells {AS_L6PHICn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L6PHICn1_STREAM_DELAY_MEM_1 [get_cells {AS_L6PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L6PHICn1_STREAM_DELAY_START_BX_1 [get_cells {AS_L6PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L6PHICn1_STREAM_DELAY_MEM_2 [get_cells {AS_L6PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L6PHICn1_STREAM_DELAY_START_BX_2 [get_cells {AS_L6PHICn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L6PHID_B_L5D_DELAY_MEM_1 [get_cells {AS_L6PHID_B_L5D_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L6PHID_B_L5D_DELAY_START_BX_1 [get_cells {AS_L6PHID_B_L5D_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L6PHID_B_L5D_DELAY_MEM_2 [get_cells {AS_L6PHID_B_L5D_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -1417,6 +1605,10 @@ set_property USER_SLR_ASSIGNMENT AS_L6PHIDn1_DELAY_MEM_1 [get_cells {AS_L6PHIDn1 set_property USER_SLR_ASSIGNMENT AS_L6PHIDn1_DELAY_START_BX_1 [get_cells {AS_L6PHIDn1_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT AS_L6PHIDn1_DELAY_MEM_2 [get_cells {AS_L6PHIDn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT AS_L6PHIDn1_DELAY_START_BX_2 [get_cells {AS_L6PHIDn1_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L6PHIDn1_STREAM_DELAY_MEM_1 [get_cells {AS_L6PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L6PHIDn1_STREAM_DELAY_START_BX_1 [get_cells {AS_L6PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT AS_L6PHIDn1_STREAM_DELAY_MEM_2 [get_cells {AS_L6PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT AS_L6PHIDn1_STREAM_DELAY_START_BX_2 [get_cells {AS_L6PHIDn1_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT IL_D1PHIA_2S_5_A_DELAY_MEM_1 [get_cells {IL_D1PHIA_2S_5_A_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT IL_D1PHIA_2S_5_A_DELAY_START_BX_1 [get_cells {IL_D1PHIA_2S_5_A_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT IL_D1PHIA_2S_5_A_DELAY_MEM_2 [get_cells {IL_D1PHIA_2S_5_A_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] @@ -3003,196 +3195,256 @@ set_property USER_SLR_ASSIGNMENT LATCH_TP_L5L6D_MEM_2 [get_cells {LATCH_TP_L5L6D set_property USER_SLR_ASSIGNMENT LATCH_TP_L5L6D_START_BX_2 [get_cells {LATCH_TP_L5L6D/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D1PHIA_MEM_1 [get_cells {LATCH_VMR_D1PHIA/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D1PHIA_START_BX_1 [get_cells {LATCH_VMR_D1PHIA/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D1PHIA_MEM_2 [get_cells {LATCH_VMR_D1PHIA/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D1PHIA_START_BX_2 [get_cells {LATCH_VMR_D1PHIA/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D1PHIA_0_MEM_1 [get_cells {LATCH_VMR_D1PHIA_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D1PHIA_0_START_BX_1 [get_cells {LATCH_VMR_D1PHIA_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D1PHIB_MEM_1 [get_cells {LATCH_VMR_D1PHIB/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D1PHIB_START_BX_1 [get_cells {LATCH_VMR_D1PHIB/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D1PHIB_MEM_2 [get_cells {LATCH_VMR_D1PHIB/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D1PHIB_START_BX_2 [get_cells {LATCH_VMR_D1PHIB/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D1PHIB_0_MEM_1 [get_cells {LATCH_VMR_D1PHIB_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D1PHIB_0_START_BX_1 [get_cells {LATCH_VMR_D1PHIB_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D1PHIC_MEM_1 [get_cells {LATCH_VMR_D1PHIC/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D1PHIC_START_BX_1 [get_cells {LATCH_VMR_D1PHIC/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D1PHIC_MEM_2 [get_cells {LATCH_VMR_D1PHIC/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D1PHIC_START_BX_2 [get_cells {LATCH_VMR_D1PHIC/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D1PHIC_0_MEM_1 [get_cells {LATCH_VMR_D1PHIC_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D1PHIC_0_START_BX_1 [get_cells {LATCH_VMR_D1PHIC_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D1PHID_MEM_1 [get_cells {LATCH_VMR_D1PHID/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D1PHID_START_BX_1 [get_cells {LATCH_VMR_D1PHID/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D1PHID_MEM_2 [get_cells {LATCH_VMR_D1PHID/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D1PHID_START_BX_2 [get_cells {LATCH_VMR_D1PHID/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D1PHID_0_MEM_1 [get_cells {LATCH_VMR_D1PHID_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D1PHID_0_START_BX_1 [get_cells {LATCH_VMR_D1PHID_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D2PHIA_MEM_1 [get_cells {LATCH_VMR_D2PHIA/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D2PHIA_START_BX_1 [get_cells {LATCH_VMR_D2PHIA/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D2PHIA_MEM_2 [get_cells {LATCH_VMR_D2PHIA/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D2PHIA_START_BX_2 [get_cells {LATCH_VMR_D2PHIA/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D2PHIA_0_MEM_1 [get_cells {LATCH_VMR_D2PHIA_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D2PHIA_0_START_BX_1 [get_cells {LATCH_VMR_D2PHIA_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D2PHIB_MEM_1 [get_cells {LATCH_VMR_D2PHIB/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D2PHIB_START_BX_1 [get_cells {LATCH_VMR_D2PHIB/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D2PHIB_MEM_2 [get_cells {LATCH_VMR_D2PHIB/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D2PHIB_START_BX_2 [get_cells {LATCH_VMR_D2PHIB/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D2PHIB_0_MEM_1 [get_cells {LATCH_VMR_D2PHIB_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D2PHIB_0_START_BX_1 [get_cells {LATCH_VMR_D2PHIB_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D2PHIC_MEM_1 [get_cells {LATCH_VMR_D2PHIC/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D2PHIC_START_BX_1 [get_cells {LATCH_VMR_D2PHIC/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D2PHIC_MEM_2 [get_cells {LATCH_VMR_D2PHIC/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D2PHIC_START_BX_2 [get_cells {LATCH_VMR_D2PHIC/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D2PHIC_0_MEM_1 [get_cells {LATCH_VMR_D2PHIC_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D2PHIC_0_START_BX_1 [get_cells {LATCH_VMR_D2PHIC_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D2PHID_MEM_1 [get_cells {LATCH_VMR_D2PHID/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D2PHID_START_BX_1 [get_cells {LATCH_VMR_D2PHID/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D2PHID_MEM_2 [get_cells {LATCH_VMR_D2PHID/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D2PHID_START_BX_2 [get_cells {LATCH_VMR_D2PHID/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D2PHID_0_MEM_1 [get_cells {LATCH_VMR_D2PHID_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D2PHID_0_START_BX_1 [get_cells {LATCH_VMR_D2PHID_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D3PHIA_MEM_1 [get_cells {LATCH_VMR_D3PHIA/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D3PHIA_START_BX_1 [get_cells {LATCH_VMR_D3PHIA/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D3PHIA_MEM_2 [get_cells {LATCH_VMR_D3PHIA/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D3PHIA_START_BX_2 [get_cells {LATCH_VMR_D3PHIA/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D3PHIA_0_MEM_1 [get_cells {LATCH_VMR_D3PHIA_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D3PHIA_0_START_BX_1 [get_cells {LATCH_VMR_D3PHIA_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D3PHIB_MEM_1 [get_cells {LATCH_VMR_D3PHIB/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D3PHIB_START_BX_1 [get_cells {LATCH_VMR_D3PHIB/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D3PHIB_MEM_2 [get_cells {LATCH_VMR_D3PHIB/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D3PHIB_START_BX_2 [get_cells {LATCH_VMR_D3PHIB/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D3PHIB_0_MEM_1 [get_cells {LATCH_VMR_D3PHIB_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D3PHIB_0_START_BX_1 [get_cells {LATCH_VMR_D3PHIB_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D3PHIC_MEM_1 [get_cells {LATCH_VMR_D3PHIC/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D3PHIC_START_BX_1 [get_cells {LATCH_VMR_D3PHIC/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D3PHIC_MEM_2 [get_cells {LATCH_VMR_D3PHIC/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D3PHIC_START_BX_2 [get_cells {LATCH_VMR_D3PHIC/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D3PHIC_0_MEM_1 [get_cells {LATCH_VMR_D3PHIC_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D3PHIC_0_START_BX_1 [get_cells {LATCH_VMR_D3PHIC_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D3PHID_MEM_1 [get_cells {LATCH_VMR_D3PHID/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D3PHID_START_BX_1 [get_cells {LATCH_VMR_D3PHID/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D3PHID_MEM_2 [get_cells {LATCH_VMR_D3PHID/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D3PHID_START_BX_2 [get_cells {LATCH_VMR_D3PHID/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D3PHID_0_MEM_1 [get_cells {LATCH_VMR_D3PHID_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D3PHID_0_START_BX_1 [get_cells {LATCH_VMR_D3PHID_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D4PHIA_MEM_1 [get_cells {LATCH_VMR_D4PHIA/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D4PHIA_START_BX_1 [get_cells {LATCH_VMR_D4PHIA/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D4PHIA_MEM_2 [get_cells {LATCH_VMR_D4PHIA/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D4PHIA_START_BX_2 [get_cells {LATCH_VMR_D4PHIA/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D4PHIA_0_MEM_1 [get_cells {LATCH_VMR_D4PHIA_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D4PHIA_0_START_BX_1 [get_cells {LATCH_VMR_D4PHIA_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D4PHIB_MEM_1 [get_cells {LATCH_VMR_D4PHIB/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D4PHIB_START_BX_1 [get_cells {LATCH_VMR_D4PHIB/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D4PHIB_MEM_2 [get_cells {LATCH_VMR_D4PHIB/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D4PHIB_START_BX_2 [get_cells {LATCH_VMR_D4PHIB/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D4PHIB_0_MEM_1 [get_cells {LATCH_VMR_D4PHIB_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D4PHIB_0_START_BX_1 [get_cells {LATCH_VMR_D4PHIB_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D4PHIC_MEM_1 [get_cells {LATCH_VMR_D4PHIC/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D4PHIC_START_BX_1 [get_cells {LATCH_VMR_D4PHIC/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D4PHIC_MEM_2 [get_cells {LATCH_VMR_D4PHIC/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D4PHIC_START_BX_2 [get_cells {LATCH_VMR_D4PHIC/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D4PHIC_0_MEM_1 [get_cells {LATCH_VMR_D4PHIC_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D4PHIC_0_START_BX_1 [get_cells {LATCH_VMR_D4PHIC_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D4PHID_MEM_1 [get_cells {LATCH_VMR_D4PHID/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D4PHID_START_BX_1 [get_cells {LATCH_VMR_D4PHID/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D4PHID_MEM_2 [get_cells {LATCH_VMR_D4PHID/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D4PHID_START_BX_2 [get_cells {LATCH_VMR_D4PHID/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D4PHID_0_MEM_1 [get_cells {LATCH_VMR_D4PHID_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D4PHID_0_START_BX_1 [get_cells {LATCH_VMR_D4PHID_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D5PHIA_MEM_1 [get_cells {LATCH_VMR_D5PHIA/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D5PHIA_START_BX_1 [get_cells {LATCH_VMR_D5PHIA/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D5PHIA_MEM_2 [get_cells {LATCH_VMR_D5PHIA/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D5PHIA_START_BX_2 [get_cells {LATCH_VMR_D5PHIA/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D5PHIA_0_MEM_1 [get_cells {LATCH_VMR_D5PHIA_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D5PHIA_0_START_BX_1 [get_cells {LATCH_VMR_D5PHIA_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D5PHIB_MEM_1 [get_cells {LATCH_VMR_D5PHIB/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D5PHIB_START_BX_1 [get_cells {LATCH_VMR_D5PHIB/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D5PHIB_MEM_2 [get_cells {LATCH_VMR_D5PHIB/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D5PHIB_START_BX_2 [get_cells {LATCH_VMR_D5PHIB/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D5PHIB_0_MEM_1 [get_cells {LATCH_VMR_D5PHIB_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D5PHIB_0_START_BX_1 [get_cells {LATCH_VMR_D5PHIB_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D5PHIC_MEM_1 [get_cells {LATCH_VMR_D5PHIC/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D5PHIC_START_BX_1 [get_cells {LATCH_VMR_D5PHIC/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D5PHIC_MEM_2 [get_cells {LATCH_VMR_D5PHIC/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D5PHIC_START_BX_2 [get_cells {LATCH_VMR_D5PHIC/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D5PHIC_0_MEM_1 [get_cells {LATCH_VMR_D5PHIC_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D5PHIC_0_START_BX_1 [get_cells {LATCH_VMR_D5PHIC_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D5PHID_MEM_1 [get_cells {LATCH_VMR_D5PHID/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_D5PHID_START_BX_1 [get_cells {LATCH_VMR_D5PHID/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D5PHID_MEM_2 [get_cells {LATCH_VMR_D5PHID/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_D5PHID_START_BX_2 [get_cells {LATCH_VMR_D5PHID/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D5PHID_0_MEM_1 [get_cells {LATCH_VMR_D5PHID_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_D5PHID_0_START_BX_1 [get_cells {LATCH_VMR_D5PHID_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIA_MEM_1 [get_cells {LATCH_VMR_L1PHIA/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIA_START_BX_1 [get_cells {LATCH_VMR_L1PHIA/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIA_MEM_2 [get_cells {LATCH_VMR_L1PHIA/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIA_START_BX_2 [get_cells {LATCH_VMR_L1PHIA/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIA_0_MEM_1 [get_cells {LATCH_VMR_L1PHIA_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIA_0_START_BX_1 [get_cells {LATCH_VMR_L1PHIA_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIB_MEM_1 [get_cells {LATCH_VMR_L1PHIB/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIB_START_BX_1 [get_cells {LATCH_VMR_L1PHIB/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIB_MEM_2 [get_cells {LATCH_VMR_L1PHIB/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIB_START_BX_2 [get_cells {LATCH_VMR_L1PHIB/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIB_0_MEM_1 [get_cells {LATCH_VMR_L1PHIB_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIB_0_START_BX_1 [get_cells {LATCH_VMR_L1PHIB_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIC_MEM_1 [get_cells {LATCH_VMR_L1PHIC/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIC_START_BX_1 [get_cells {LATCH_VMR_L1PHIC/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIC_MEM_2 [get_cells {LATCH_VMR_L1PHIC/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIC_START_BX_2 [get_cells {LATCH_VMR_L1PHIC/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIC_0_MEM_1 [get_cells {LATCH_VMR_L1PHIC_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIC_0_START_BX_1 [get_cells {LATCH_VMR_L1PHIC_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHID_MEM_1 [get_cells {LATCH_VMR_L1PHID/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHID_START_BX_1 [get_cells {LATCH_VMR_L1PHID/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHID_MEM_2 [get_cells {LATCH_VMR_L1PHID/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHID_START_BX_2 [get_cells {LATCH_VMR_L1PHID/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHID_0_MEM_1 [get_cells {LATCH_VMR_L1PHID_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHID_0_START_BX_1 [get_cells {LATCH_VMR_L1PHID_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIE_MEM_1 [get_cells {LATCH_VMR_L1PHIE/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIE_START_BX_1 [get_cells {LATCH_VMR_L1PHIE/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIE_MEM_2 [get_cells {LATCH_VMR_L1PHIE/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIE_START_BX_2 [get_cells {LATCH_VMR_L1PHIE/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIE_0_MEM_1 [get_cells {LATCH_VMR_L1PHIE_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIE_0_START_BX_1 [get_cells {LATCH_VMR_L1PHIE_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIF_MEM_1 [get_cells {LATCH_VMR_L1PHIF/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIF_START_BX_1 [get_cells {LATCH_VMR_L1PHIF/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIF_MEM_2 [get_cells {LATCH_VMR_L1PHIF/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIF_START_BX_2 [get_cells {LATCH_VMR_L1PHIF/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIF_0_MEM_1 [get_cells {LATCH_VMR_L1PHIF_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIF_0_START_BX_1 [get_cells {LATCH_VMR_L1PHIF_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIG_MEM_1 [get_cells {LATCH_VMR_L1PHIG/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIG_START_BX_1 [get_cells {LATCH_VMR_L1PHIG/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIG_MEM_2 [get_cells {LATCH_VMR_L1PHIG/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIG_START_BX_2 [get_cells {LATCH_VMR_L1PHIG/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIG_0_MEM_1 [get_cells {LATCH_VMR_L1PHIG_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIG_0_START_BX_1 [get_cells {LATCH_VMR_L1PHIG_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIH_MEM_1 [get_cells {LATCH_VMR_L1PHIH/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIH_START_BX_1 [get_cells {LATCH_VMR_L1PHIH/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIH_MEM_2 [get_cells {LATCH_VMR_L1PHIH/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIH_START_BX_2 [get_cells {LATCH_VMR_L1PHIH/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIH_0_MEM_1 [get_cells {LATCH_VMR_L1PHIH_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L1PHIH_0_START_BX_1 [get_cells {LATCH_VMR_L1PHIH_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L2PHIA_MEM_1 [get_cells {LATCH_VMR_L2PHIA/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L2PHIA_START_BX_1 [get_cells {LATCH_VMR_L2PHIA/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L2PHIA_MEM_2 [get_cells {LATCH_VMR_L2PHIA/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L2PHIA_START_BX_2 [get_cells {LATCH_VMR_L2PHIA/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L2PHIA_0_MEM_1 [get_cells {LATCH_VMR_L2PHIA_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L2PHIA_0_START_BX_1 [get_cells {LATCH_VMR_L2PHIA_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L2PHIB_MEM_1 [get_cells {LATCH_VMR_L2PHIB/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L2PHIB_START_BX_1 [get_cells {LATCH_VMR_L2PHIB/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L2PHIB_MEM_2 [get_cells {LATCH_VMR_L2PHIB/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L2PHIB_START_BX_2 [get_cells {LATCH_VMR_L2PHIB/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L2PHIB_0_MEM_1 [get_cells {LATCH_VMR_L2PHIB_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L2PHIB_0_START_BX_1 [get_cells {LATCH_VMR_L2PHIB_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L2PHIC_MEM_1 [get_cells {LATCH_VMR_L2PHIC/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L2PHIC_START_BX_1 [get_cells {LATCH_VMR_L2PHIC/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L2PHIC_MEM_2 [get_cells {LATCH_VMR_L2PHIC/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L2PHIC_START_BX_2 [get_cells {LATCH_VMR_L2PHIC/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L2PHIC_0_MEM_1 [get_cells {LATCH_VMR_L2PHIC_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L2PHIC_0_START_BX_1 [get_cells {LATCH_VMR_L2PHIC_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L2PHID_MEM_1 [get_cells {LATCH_VMR_L2PHID/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L2PHID_START_BX_1 [get_cells {LATCH_VMR_L2PHID/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L2PHID_MEM_2 [get_cells {LATCH_VMR_L2PHID/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L2PHID_START_BX_2 [get_cells {LATCH_VMR_L2PHID/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L2PHID_0_MEM_1 [get_cells {LATCH_VMR_L2PHID_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L2PHID_0_START_BX_1 [get_cells {LATCH_VMR_L2PHID_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L3PHIA_MEM_1 [get_cells {LATCH_VMR_L3PHIA/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L3PHIA_START_BX_1 [get_cells {LATCH_VMR_L3PHIA/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L3PHIA_MEM_2 [get_cells {LATCH_VMR_L3PHIA/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L3PHIA_START_BX_2 [get_cells {LATCH_VMR_L3PHIA/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L3PHIA_0_MEM_1 [get_cells {LATCH_VMR_L3PHIA_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L3PHIA_0_START_BX_1 [get_cells {LATCH_VMR_L3PHIA_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L3PHIB_MEM_1 [get_cells {LATCH_VMR_L3PHIB/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L3PHIB_START_BX_1 [get_cells {LATCH_VMR_L3PHIB/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L3PHIB_MEM_2 [get_cells {LATCH_VMR_L3PHIB/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L3PHIB_START_BX_2 [get_cells {LATCH_VMR_L3PHIB/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L3PHIB_0_MEM_1 [get_cells {LATCH_VMR_L3PHIB_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L3PHIB_0_START_BX_1 [get_cells {LATCH_VMR_L3PHIB_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L3PHIC_MEM_1 [get_cells {LATCH_VMR_L3PHIC/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L3PHIC_START_BX_1 [get_cells {LATCH_VMR_L3PHIC/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L3PHIC_MEM_2 [get_cells {LATCH_VMR_L3PHIC/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L3PHIC_START_BX_2 [get_cells {LATCH_VMR_L3PHIC/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L3PHIC_0_MEM_1 [get_cells {LATCH_VMR_L3PHIC_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L3PHIC_0_START_BX_1 [get_cells {LATCH_VMR_L3PHIC_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L3PHID_MEM_1 [get_cells {LATCH_VMR_L3PHID/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L3PHID_START_BX_1 [get_cells {LATCH_VMR_L3PHID/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L3PHID_MEM_2 [get_cells {LATCH_VMR_L3PHID/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L3PHID_START_BX_2 [get_cells {LATCH_VMR_L3PHID/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L3PHID_0_MEM_1 [get_cells {LATCH_VMR_L3PHID_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L3PHID_0_START_BX_1 [get_cells {LATCH_VMR_L3PHID_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L4PHIA_MEM_1 [get_cells {LATCH_VMR_L4PHIA/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L4PHIA_START_BX_1 [get_cells {LATCH_VMR_L4PHIA/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L4PHIA_MEM_2 [get_cells {LATCH_VMR_L4PHIA/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L4PHIA_START_BX_2 [get_cells {LATCH_VMR_L4PHIA/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L4PHIA_0_MEM_1 [get_cells {LATCH_VMR_L4PHIA_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L4PHIA_0_START_BX_1 [get_cells {LATCH_VMR_L4PHIA_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L4PHIB_MEM_1 [get_cells {LATCH_VMR_L4PHIB/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L4PHIB_START_BX_1 [get_cells {LATCH_VMR_L4PHIB/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L4PHIB_MEM_2 [get_cells {LATCH_VMR_L4PHIB/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L4PHIB_START_BX_2 [get_cells {LATCH_VMR_L4PHIB/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L4PHIB_0_MEM_1 [get_cells {LATCH_VMR_L4PHIB_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L4PHIB_0_START_BX_1 [get_cells {LATCH_VMR_L4PHIB_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L4PHIC_MEM_1 [get_cells {LATCH_VMR_L4PHIC/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L4PHIC_START_BX_1 [get_cells {LATCH_VMR_L4PHIC/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L4PHIC_MEM_2 [get_cells {LATCH_VMR_L4PHIC/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L4PHIC_START_BX_2 [get_cells {LATCH_VMR_L4PHIC/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L4PHIC_0_MEM_1 [get_cells {LATCH_VMR_L4PHIC_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L4PHIC_0_START_BX_1 [get_cells {LATCH_VMR_L4PHIC_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L4PHID_MEM_1 [get_cells {LATCH_VMR_L4PHID/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L4PHID_START_BX_1 [get_cells {LATCH_VMR_L4PHID/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L4PHID_MEM_2 [get_cells {LATCH_VMR_L4PHID/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L4PHID_START_BX_2 [get_cells {LATCH_VMR_L4PHID/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L4PHID_0_MEM_1 [get_cells {LATCH_VMR_L4PHID_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L4PHID_0_START_BX_1 [get_cells {LATCH_VMR_L4PHID_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L5PHIA_MEM_1 [get_cells {LATCH_VMR_L5PHIA/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L5PHIA_START_BX_1 [get_cells {LATCH_VMR_L5PHIA/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L5PHIA_MEM_2 [get_cells {LATCH_VMR_L5PHIA/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L5PHIA_START_BX_2 [get_cells {LATCH_VMR_L5PHIA/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L5PHIA_0_MEM_1 [get_cells {LATCH_VMR_L5PHIA_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L5PHIA_0_START_BX_1 [get_cells {LATCH_VMR_L5PHIA_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L5PHIB_MEM_1 [get_cells {LATCH_VMR_L5PHIB/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L5PHIB_START_BX_1 [get_cells {LATCH_VMR_L5PHIB/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L5PHIB_MEM_2 [get_cells {LATCH_VMR_L5PHIB/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L5PHIB_START_BX_2 [get_cells {LATCH_VMR_L5PHIB/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L5PHIB_0_MEM_1 [get_cells {LATCH_VMR_L5PHIB_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L5PHIB_0_START_BX_1 [get_cells {LATCH_VMR_L5PHIB_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L5PHIC_MEM_1 [get_cells {LATCH_VMR_L5PHIC/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L5PHIC_START_BX_1 [get_cells {LATCH_VMR_L5PHIC/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L5PHIC_MEM_2 [get_cells {LATCH_VMR_L5PHIC/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L5PHIC_START_BX_2 [get_cells {LATCH_VMR_L5PHIC/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L5PHIC_0_MEM_1 [get_cells {LATCH_VMR_L5PHIC_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L5PHIC_0_START_BX_1 [get_cells {LATCH_VMR_L5PHIC_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L5PHID_MEM_1 [get_cells {LATCH_VMR_L5PHID/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L5PHID_START_BX_1 [get_cells {LATCH_VMR_L5PHID/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L5PHID_MEM_2 [get_cells {LATCH_VMR_L5PHID/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L5PHID_START_BX_2 [get_cells {LATCH_VMR_L5PHID/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L5PHID_0_MEM_1 [get_cells {LATCH_VMR_L5PHID_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L5PHID_0_START_BX_1 [get_cells {LATCH_VMR_L5PHID_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L6PHIA_MEM_1 [get_cells {LATCH_VMR_L6PHIA/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L6PHIA_START_BX_1 [get_cells {LATCH_VMR_L6PHIA/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L6PHIA_MEM_2 [get_cells {LATCH_VMR_L6PHIA/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L6PHIA_START_BX_2 [get_cells {LATCH_VMR_L6PHIA/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L6PHIA_0_MEM_1 [get_cells {LATCH_VMR_L6PHIA_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L6PHIA_0_START_BX_1 [get_cells {LATCH_VMR_L6PHIA_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L6PHIB_MEM_1 [get_cells {LATCH_VMR_L6PHIB/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L6PHIB_START_BX_1 [get_cells {LATCH_VMR_L6PHIB/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L6PHIB_MEM_2 [get_cells {LATCH_VMR_L6PHIB/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L6PHIB_START_BX_2 [get_cells {LATCH_VMR_L6PHIB/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L6PHIB_0_MEM_1 [get_cells {LATCH_VMR_L6PHIB_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L6PHIB_0_START_BX_1 [get_cells {LATCH_VMR_L6PHIB_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L6PHIC_MEM_1 [get_cells {LATCH_VMR_L6PHIC/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L6PHIC_START_BX_1 [get_cells {LATCH_VMR_L6PHIC/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L6PHIC_MEM_2 [get_cells {LATCH_VMR_L6PHIC/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L6PHIC_START_BX_2 [get_cells {LATCH_VMR_L6PHIC/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L6PHIC_0_MEM_1 [get_cells {LATCH_VMR_L6PHIC_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L6PHIC_0_START_BX_1 [get_cells {LATCH_VMR_L6PHIC_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L6PHID_MEM_1 [get_cells {LATCH_VMR_L6PHID/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT LATCH_VMR_L6PHID_START_BX_1 [get_cells {LATCH_VMR_L6PHID/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L6PHID_MEM_2 [get_cells {LATCH_VMR_L6PHID/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] -set_property USER_SLR_ASSIGNMENT LATCH_VMR_L6PHID_START_BX_2 [get_cells {LATCH_VMR_L6PHID/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L6PHID_0_MEM_1 [get_cells {LATCH_VMR_L6PHID_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT LATCH_VMR_L6PHID_0_START_BX_1 [get_cells {LATCH_VMR_L6PHID_0/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT TPARD1D2ABCD_STREAM_DELAY_MEM_1 [get_cells {TPARD1D2ABCD_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT TPARD1D2ABCD_STREAM_DELAY_START_BX_1 [get_cells {TPARD1D2ABCD_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT TPARD1D2ABCD_STREAM_DELAY_MEM_2 [get_cells {TPARD1D2ABCD_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT TPARD1D2ABCD_STREAM_DELAY_START_BX_2 [get_cells {TPARD1D2ABCD_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT TPARD3D4ABCD_STREAM_DELAY_MEM_1 [get_cells {TPARD3D4ABCD_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT TPARD3D4ABCD_STREAM_DELAY_START_BX_1 [get_cells {TPARD3D4ABCD_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT TPARD3D4ABCD_STREAM_DELAY_MEM_2 [get_cells {TPARD3D4ABCD_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT TPARD3D4ABCD_STREAM_DELAY_START_BX_2 [get_cells {TPARD3D4ABCD_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT TPARL1D1ABCD_STREAM_DELAY_MEM_1 [get_cells {TPARL1D1ABCD_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT TPARL1D1ABCD_STREAM_DELAY_START_BX_1 [get_cells {TPARL1D1ABCD_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT TPARL1D1ABCD_STREAM_DELAY_MEM_2 [get_cells {TPARL1D1ABCD_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT TPARL1D1ABCD_STREAM_DELAY_START_BX_2 [get_cells {TPARL1D1ABCD_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT TPARL1D1EFGH_STREAM_DELAY_MEM_1 [get_cells {TPARL1D1EFGH_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT TPARL1D1EFGH_STREAM_DELAY_START_BX_1 [get_cells {TPARL1D1EFGH_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT TPARL1D1EFGH_STREAM_DELAY_MEM_2 [get_cells {TPARL1D1EFGH_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT TPARL1D1EFGH_STREAM_DELAY_START_BX_2 [get_cells {TPARL1D1EFGH_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT TPARL1L2ABC_STREAM_DELAY_MEM_1 [get_cells {TPARL1L2ABC_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT TPARL1L2ABC_STREAM_DELAY_START_BX_1 [get_cells {TPARL1L2ABC_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT TPARL1L2ABC_STREAM_DELAY_MEM_2 [get_cells {TPARL1L2ABC_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT TPARL1L2ABC_STREAM_DELAY_START_BX_2 [get_cells {TPARL1L2ABC_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT TPARL1L2DE_STREAM_DELAY_MEM_1 [get_cells {TPARL1L2DE_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT TPARL1L2DE_STREAM_DELAY_START_BX_1 [get_cells {TPARL1L2DE_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT TPARL1L2DE_STREAM_DELAY_MEM_2 [get_cells {TPARL1L2DE_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT TPARL1L2DE_STREAM_DELAY_START_BX_2 [get_cells {TPARL1L2DE_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT TPARL1L2F_STREAM_DELAY_MEM_1 [get_cells {TPARL1L2F_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT TPARL1L2F_STREAM_DELAY_START_BX_1 [get_cells {TPARL1L2F_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT TPARL1L2F_STREAM_DELAY_MEM_2 [get_cells {TPARL1L2F_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT TPARL1L2F_STREAM_DELAY_START_BX_2 [get_cells {TPARL1L2F_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT TPARL1L2G_STREAM_DELAY_MEM_1 [get_cells {TPARL1L2G_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT TPARL1L2G_STREAM_DELAY_START_BX_1 [get_cells {TPARL1L2G_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT TPARL1L2G_STREAM_DELAY_MEM_2 [get_cells {TPARL1L2G_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT TPARL1L2G_STREAM_DELAY_START_BX_2 [get_cells {TPARL1L2G_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT TPARL1L2HI_STREAM_DELAY_MEM_1 [get_cells {TPARL1L2HI_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT TPARL1L2HI_STREAM_DELAY_START_BX_1 [get_cells {TPARL1L2HI_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT TPARL1L2HI_STREAM_DELAY_MEM_2 [get_cells {TPARL1L2HI_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT TPARL1L2HI_STREAM_DELAY_START_BX_2 [get_cells {TPARL1L2HI_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT TPARL1L2JKL_STREAM_DELAY_MEM_1 [get_cells {TPARL1L2JKL_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT TPARL1L2JKL_STREAM_DELAY_START_BX_1 [get_cells {TPARL1L2JKL_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT TPARL1L2JKL_STREAM_DELAY_MEM_2 [get_cells {TPARL1L2JKL_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT TPARL1L2JKL_STREAM_DELAY_START_BX_2 [get_cells {TPARL1L2JKL_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT TPARL2D1ABCD_STREAM_DELAY_MEM_1 [get_cells {TPARL2D1ABCD_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT TPARL2D1ABCD_STREAM_DELAY_START_BX_1 [get_cells {TPARL2D1ABCD_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT TPARL2D1ABCD_STREAM_DELAY_MEM_2 [get_cells {TPARL2D1ABCD_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT TPARL2D1ABCD_STREAM_DELAY_START_BX_2 [get_cells {TPARL2D1ABCD_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT TPARL2L3ABCD_STREAM_DELAY_MEM_1 [get_cells {TPARL2L3ABCD_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT TPARL2L3ABCD_STREAM_DELAY_START_BX_1 [get_cells {TPARL2L3ABCD_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT TPARL2L3ABCD_STREAM_DELAY_MEM_2 [get_cells {TPARL2L3ABCD_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT TPARL2L3ABCD_STREAM_DELAY_START_BX_2 [get_cells {TPARL2L3ABCD_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT TPARL3L4AB_STREAM_DELAY_MEM_1 [get_cells {TPARL3L4AB_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT TPARL3L4AB_STREAM_DELAY_START_BX_1 [get_cells {TPARL3L4AB_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT TPARL3L4AB_STREAM_DELAY_MEM_2 [get_cells {TPARL3L4AB_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT TPARL3L4AB_STREAM_DELAY_START_BX_2 [get_cells {TPARL3L4AB_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT TPARL3L4CD_STREAM_DELAY_MEM_1 [get_cells {TPARL3L4CD_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT TPARL3L4CD_STREAM_DELAY_START_BX_1 [get_cells {TPARL3L4CD_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT TPARL3L4CD_STREAM_DELAY_MEM_2 [get_cells {TPARL3L4CD_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT TPARL3L4CD_STREAM_DELAY_START_BX_2 [get_cells {TPARL3L4CD_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT TPARL5L6ABCD_STREAM_DELAY_MEM_1 [get_cells {TPARL5L6ABCD_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT TPARL5L6ABCD_STREAM_DELAY_START_BX_1 [get_cells {TPARL5L6ABCD_STREAM_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] +set_property USER_SLR_ASSIGNMENT TPARL5L6ABCD_STREAM_DELAY_MEM_2 [get_cells {TPARL5L6ABCD_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] +set_property USER_SLR_ASSIGNMENT TPARL5L6ABCD_STREAM_DELAY_START_BX_2 [get_cells {TPARL5L6ABCD_STREAM_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT TPAR_D1D2A_DELAY_MEM_1 [get_cells {TPAR_D1D2A_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] set_property USER_SLR_ASSIGNMENT TPAR_D1D2A_DELAY_START_BX_1 [get_cells {TPAR_D1D2A_DELAY/PIPELINE_SLR_XING[1].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_START_BX}] set_property USER_SLR_ASSIGNMENT TPAR_D1D2A_DELAY_MEM_2 [get_cells {TPAR_D1D2A_DELAY/PIPELINE_SLR_XING[2].AUTO_PIPELINE_OFF.USE_SRL_OFF.PIPELINE_MEM}] From 4bc5e87f9f6e735b090544ce14aa1acf4f2e1bdb Mon Sep 17 00:00:00 2001 From: Andrew Hart Date: Mon, 2 Jun 2025 17:37:24 -0400 Subject: [PATCH 11/14] Keep hierarchy and all signals in pipelines during synthesis. --- IntegrationTests/common/hdl/pipelining.vhd | 28 +++++++++++++++++----- 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/IntegrationTests/common/hdl/pipelining.vhd b/IntegrationTests/common/hdl/pipelining.vhd index 9771687911d..ef528279b12 100644 --- a/IntegrationTests/common/hdl/pipelining.vhd +++ b/IntegrationTests/common/hdl/pipelining.vhd @@ -43,8 +43,8 @@ end tf_pipeline; architecture behavior of tf_pipeline is - attribute dont_touch : string; - attribute dont_touch of behavior : architecture is "yes"; + attribute keep_hierarchy : string; + attribute keep_hierarchy of behavior : architecture is "yes"; type t_wea_pipe is array (0 to DELAY - 1) of std_logic; type t_addra_pipe is array (0 to DELAY - 1) of std_logic_vector( clogb2(RAM_DEPTH) - 1 downto 0 ); @@ -65,6 +65,14 @@ architecture behavior of tf_pipeline is attribute shreg_extract of start_pipe : signal is USE_SRL; attribute shreg_extract of bx_pipe : signal is USE_SRL; + attribute keep : string; + attribute keep of wea_pipe : signal is "yes"; + attribute keep of addra_pipe : signal is "yes"; + attribute keep of dina_pipe : signal is "yes"; + attribute keep of start_pipe : signal is "yes"; + attribute keep of bx_pipe : signal is "yes"; + attribute keep of bx_vld_pipe : signal is "yes"; + begin wea_out <= wea_pipe(DELAY - 1); @@ -140,8 +148,8 @@ end tf_auto_pipeline; architecture behavior of tf_auto_pipeline is - attribute dont_touch : string; - attribute dont_touch of behavior : architecture is "yes"; + attribute keep_hierarchy : string; + attribute keep_hierarchy of behavior : architecture is "yes"; signal wea_reg : std_logic := '0'; signal addra_reg : std_logic_vector( clogb2(RAM_DEPTH) - 1 downto 0 ) := (others => '0'); @@ -149,6 +157,14 @@ architecture behavior of tf_auto_pipeline is signal start_reg : std_logic := '0'; signal bx_reg : std_logic_vector(2 downto 0) := (others => '0'); + attribute keep : string; + attribute keep of wea_reg : signal is "yes"; + attribute keep of addra_reg : signal is "yes"; + attribute keep of dina_reg : signal is "yes"; + attribute keep of start_reg : signal is "yes"; + attribute keep of bx_reg : signal is "yes"; + attribute keep of bx_vld_reg : signal is "yes"; + begin wea_out <= wea_reg; @@ -220,8 +236,8 @@ end tf_pipeline_slr_xing; architecture behavior of tf_pipeline_slr_xing is - attribute dont_touch : string; - attribute dont_touch of behavior : architecture is "yes"; + attribute keep_hierarchy : string; + attribute keep_hierarchy of behavior : architecture is "yes"; type t_wea_intra is array (0 to NUM_SLR) of std_logic; type t_addra_intra is array (0 to NUM_SLR) of std_logic_vector( clogb2(RAM_DEPTH) - 1 downto 0 ); From 16d85ebe42af0687b4c979d308e63792d5abcb03 Mon Sep 17 00:00:00 2001 From: Andrew Hart Date: Mon, 5 May 2025 11:40:42 -0400 Subject: [PATCH 12/14] Added a port for BX valid signals to pipeline modules. --- IntegrationTests/common/hdl/pipelining.vhd | 37 ++++++++++++++++++---- 1 file changed, 31 insertions(+), 6 deletions(-) diff --git a/IntegrationTests/common/hdl/pipelining.vhd b/IntegrationTests/common/hdl/pipelining.vhd index ef528279b12..54845692a9e 100644 --- a/IntegrationTests/common/hdl/pipelining.vhd +++ b/IntegrationTests/common/hdl/pipelining.vhd @@ -36,8 +36,10 @@ entity tf_pipeline is -- Start/BX signals done : in std_logic := '0'; bx_out : in std_logic_vector(2 downto 0) := (others => '0'); + bx_out_vld : in std_logic := '0'; start : out std_logic; - bx : out std_logic_vector(2 downto 0) + bx : out std_logic_vector(2 downto 0); + bx_vld : out std_logic ); end tf_pipeline; @@ -51,12 +53,14 @@ architecture behavior of tf_pipeline is type t_dina_pipe is array (0 to DELAY - 1) of std_logic_vector( RAM_WIDTH - 1 downto 0 ); type t_start_pipe is array(0 to DELAY - 1) of std_logic; type t_bx_pipe is array(0 to DELAY - 1) of std_logic_vector(2 downto 0); + type t_bx_vld_pipe is array(0 to DELAY - 1) of std_logic; signal wea_pipe : t_wea_pipe := (others => '0'); signal addra_pipe : t_addra_pipe := (others => (others => '0') ); signal dina_pipe : t_dina_pipe := (others => (others => '0') ); signal start_pipe : t_start_pipe := (others => '0'); signal bx_pipe : t_bx_pipe := (others => (others => '0') ); + signal bx_vld_pipe : t_bx_vld_pipe := (others => '0'); attribute shreg_extract : string; attribute shreg_extract of wea_pipe : signal is USE_SRL; @@ -64,6 +68,7 @@ architecture behavior of tf_pipeline is attribute shreg_extract of dina_pipe : signal is USE_SRL; attribute shreg_extract of start_pipe : signal is USE_SRL; attribute shreg_extract of bx_pipe : signal is USE_SRL; + attribute shreg_extract of bx_vld_pipe : signal is USE_SRL; attribute keep : string; attribute keep of wea_pipe : signal is "yes"; @@ -80,6 +85,7 @@ begin dina_out <= dina_pipe(DELAY - 1); start <= start_pipe(DELAY - 1); bx <= bx_pipe(DELAY - 1); + bx_vld <= bx_vld_pipe(DELAY - 1); PIPELINE : process (clk) is begin @@ -92,6 +98,7 @@ begin dina_pipe(ii) <= dina_pipe(ii - 1); start_pipe(ii) <= start_pipe(ii - 1); bx_pipe(ii) <= bx_pipe(ii - 1); + bx_vld_pipe(ii) <= bx_vld_pipe(ii - 1); end loop; wea_pipe(0) <= wea; @@ -103,6 +110,7 @@ begin start_pipe(0) <= done; end if; bx_pipe(0) <= bx_out; + bx_vld_pipe(0) <= bx_out_vld; end if; @@ -141,8 +149,10 @@ entity tf_auto_pipeline is -- Start/BX signals done : in std_logic := '0'; bx_out : in std_logic_vector(2 downto 0) := (others => '0'); + bx_out_vld : in std_logic := '0'; start : out std_logic; - bx : out std_logic_vector(2 downto 0) + bx : out std_logic_vector(2 downto 0); + bx_vld : out std_logic ); end tf_auto_pipeline; @@ -156,6 +166,7 @@ architecture behavior of tf_auto_pipeline is signal dina_reg : std_logic_vector( RAM_WIDTH - 1 downto 0 ) := (others => '0'); signal start_reg : std_logic := '0'; signal bx_reg : std_logic_vector(2 downto 0) := (others => '0'); + signal bx_vld_reg : std_logic := '0'; attribute keep : string; attribute keep of wea_reg : signal is "yes"; @@ -172,6 +183,7 @@ begin dina_out <= dina_reg; start <= start_reg; bx <= bx_reg; + bx_vld <= bx_vld_reg; AUTO_PIPELINE : process (clk) is begin @@ -187,6 +199,7 @@ begin start_reg <= done; end if; bx_reg <= bx_out; + bx_vld_reg <= bx_out_vld; end if; @@ -229,8 +242,10 @@ entity tf_pipeline_slr_xing is -- Start/BX signals done : in std_logic := '0'; bx_out : in std_logic_vector(2 downto 0) := (others => '0'); + bx_out_vld : in std_logic := '0'; start : out std_logic; - bx : out std_logic_vector(2 downto 0) + bx : out std_logic_vector(2 downto 0); + bx_vld : out std_logic ); end tf_pipeline_slr_xing; @@ -244,12 +259,14 @@ architecture behavior of tf_pipeline_slr_xing is type t_dina_intra is array (0 to NUM_SLR) of std_logic_vector( RAM_WIDTH - 1 downto 0 ); type t_start_intra is array(0 to NUM_SLR) of std_logic; type t_bx_intra is array(0 to NUM_SLR) of std_logic_vector(2 downto 0); + type t_bx_vld_intra is array(0 to NUM_SLR) of std_logic; signal wea_intra : t_wea_intra := (others => '0'); signal addra_intra : t_addra_intra := (others => (others => '0')); signal dina_intra : t_dina_intra := (others => (others => '0')); signal start_intra : t_start_intra := (others => '0'); signal bx_intra : t_bx_intra := (others => (others => '0')); + signal bx_vld_intra : t_bx_vld_intra := (others => '0'); begin @@ -258,6 +275,7 @@ begin dina_out <= dina_intra(NUM_SLR); start <= start_intra(NUM_SLR); bx <= bx_intra(NUM_SLR); + bx_vld <= bx_vld_intra(NUM_SLR); PIPELINE_SLR_XING : for ii in 1 to NUM_SLR generate @@ -287,8 +305,10 @@ begin reset => reset, done => start_intra(ii - 1), bx_out => bx_intra(ii - 1), + bx_out_vld => bx_vld_intra(ii - 1), start => start_intra(ii), - bx => bx_intra(ii) + bx => bx_intra(ii), + bx_vld => bx_vld_intra(ii) ); end generate AUTO_PIPELINE_ON; @@ -327,8 +347,10 @@ begin reset => reset, done => start_intra(ii - 1), bx_out => bx_intra(ii - 1), + bx_out_vld => bx_vld_intra(ii - 1), start => start_intra(ii), - bx => bx_intra(ii) + bx => bx_intra(ii), + bx_vld => bx_vld_intra(ii) ); end generate USE_SRL_ON; @@ -365,8 +387,10 @@ begin reset => reset, done => start_intra(ii - 1), bx_out => bx_intra(ii - 1), + bx_out_vld => bx_vld_intra(ii - 1), start => start_intra(ii), - bx => bx_intra(ii) + bx => bx_intra(ii), + bx_vld => bx_vld_intra(ii) ); end generate USE_SRL_OFF; @@ -380,5 +404,6 @@ begin dina_intra(0) <= dina; start_intra(0) <= done; bx_intra(0) <= bx_out; + bx_vld_intra(0) <= bx_out_vld; end behavior; From dd4fcc402294e627efb8786a823067913c8b4ee6 Mon Sep 17 00:00:00 2001 From: Andrew Hart Date: Fri, 18 Jul 2025 09:21:06 -0400 Subject: [PATCH 13/14] Only latch start signal at beginning of pipeline. --- IntegrationTests/common/hdl/pipelining.vhd | 76 ++++++++++++++++++---- 1 file changed, 63 insertions(+), 13 deletions(-) diff --git a/IntegrationTests/common/hdl/pipelining.vhd b/IntegrationTests/common/hdl/pipelining.vhd index 54845692a9e..eace2e9497c 100644 --- a/IntegrationTests/common/hdl/pipelining.vhd +++ b/IntegrationTests/common/hdl/pipelining.vhd @@ -16,6 +16,7 @@ entity tf_pipeline is generic ( DELAY : natural := 2; USE_SRL : string := "no"; + LATCH_START : boolean := false; RAM_WIDTH : natural := 14; NUM_PAGES : natural := 2; PAGE_LENGTH : natural := PAGE_LENGTH; @@ -96,7 +97,6 @@ begin wea_pipe(ii) <= wea_pipe(ii - 1); addra_pipe(ii) <= addra_pipe(ii - 1); dina_pipe(ii) <= dina_pipe(ii - 1); - start_pipe(ii) <= start_pipe(ii - 1); bx_pipe(ii) <= bx_pipe(ii - 1); bx_vld_pipe(ii) <= bx_vld_pipe(ii - 1); end loop; @@ -104,11 +104,6 @@ begin wea_pipe(0) <= wea; addra_pipe(0) <= addra; dina_pipe(0) <= dina; - if reset = '1' then - start_pipe(0) <= '0'; - elsif done = '1' then - start_pipe(0) <= done; - end if; bx_pipe(0) <= bx_out; bx_vld_pipe(0) <= bx_out_vld; @@ -116,6 +111,34 @@ begin end process; + START_LATCH : if LATCH_START generate + START_LATCH_PIPELINE : process (clk) is + begin + if rising_edge(clk) then + for ii in 1 to DELAY - 1 loop + start_pipe(ii) <= start_pipe(ii - 1); + end loop; + if reset = '1' then + start_pipe(0) <= '0'; + elsif done = '1' then + start_pipe(0) <= '1'; + end if; + end if; + end process; + end generate START_LATCH; + + NO_START_LATCH : if not LATCH_START generate + START_PIPELINE : process (clk) is + begin + if rising_edge(clk) then + for ii in 1 to DELAY - 1 loop + start_pipe(ii) <= start_pipe(ii - 1); + end loop; + start_pipe(0) <= done; + end if; + end process; + end generate NO_START_LATCH; + end behavior; --! Using the IEEE Library @@ -129,6 +152,7 @@ use work.tf_pkg.all; entity tf_auto_pipeline is generic ( + LATCH_START : boolean := false; RAM_WIDTH : natural := 14; NUM_PAGES : natural := 2; PAGE_LENGTH : natural := PAGE_LENGTH; @@ -193,11 +217,6 @@ begin wea_reg <= wea; addra_reg <= addra; dina_reg <= dina; - if reset = '1' then - start_reg <= '0'; - elsif done = '1' then - start_reg <= done; - end if; bx_reg <= bx_out; bx_vld_reg <= bx_out_vld; @@ -205,6 +224,28 @@ begin end process; + START_LATCH : if LATCH_START generate + START_LATCH_PIPELINE : process (clk) is + begin + if rising_edge(clk) then + if reset = '1' then + start_reg <= '0'; + elsif done = '1' then + start_reg <= '1'; + end if; + end if; + end process; + end generate START_LATCH; + + NO_START_LATCH : if not LATCH_START generate + START_PIPELINE : process (clk) is + begin + if rising_edge(clk) then + start_reg <= done; + end if; + end process; + end generate NO_START_LATCH; + end behavior; --! Using the IEEE Library @@ -222,6 +263,7 @@ entity tf_pipeline_slr_xing is NUM_SLR : natural := 2; DELAY : t_arr_1d_nat(0 to NUM_SLR - 1) := (others => 2); USE_SRL : t_arr_1d_bol(0 to NUM_SLR - 1) := (others => false); + LATCH_START : boolean := true; RAM_WIDTH : natural := 14; NUM_PAGES : natural := 2; PAGE_LENGTH : natural := PAGE_LENGTH; @@ -254,6 +296,9 @@ architecture behavior of tf_pipeline_slr_xing is attribute keep_hierarchy : string; attribute keep_hierarchy of behavior : architecture is "yes"; + type t_latch_start_map is array (1 to NUM_SLR) of boolean; + constant latch_start_map : t_latch_start_map := (1 => LATCH_START, others => false); + type t_wea_intra is array (0 to NUM_SLR) of std_logic; type t_addra_intra is array (0 to NUM_SLR) of std_logic_vector( clogb2(RAM_DEPTH) - 1 downto 0 ); type t_dina_intra is array (0 to NUM_SLR) of std_logic_vector( RAM_WIDTH - 1 downto 0 ); @@ -300,6 +345,9 @@ begin ); AUTO_PIPELINE_START_BX : entity work.tf_auto_pipeline + generic map ( + LATCH_START => latch_start_map(ii) + ) port map ( clk => clk, reset => reset, @@ -340,7 +388,8 @@ begin PIPELINE_START_BX : entity work.tf_pipeline generic map ( DELAY => DELAY(ii - 1), - USE_SRL => "yes" + USE_SRL => "yes", + LATCH_START => latch_start_map(ii) ) port map ( clk => clk, @@ -380,7 +429,8 @@ begin PIPELINE_START_BX : entity work.tf_pipeline generic map ( DELAY => DELAY(ii - 1), - USE_SRL => "no" + USE_SRL => "no", + LATCH_START => latch_start_map(ii) ) port map ( clk => clk, From a76da57a08de0934a54f5867efc15438ac447088 Mon Sep 17 00:00:00 2001 From: Andrew Hart Date: Fri, 18 Jul 2025 09:05:33 -0400 Subject: [PATCH 14/14] Removed regceb ports from memory modules. --- IntegrationTests/common/hdl/tf_mem.vhd | 1 - IntegrationTests/common/hdl/tf_mem_bin.vhd | 3 --- IntegrationTests/common/hdl/tf_mem_tpar.vhd | 1 - IntegrationTests/common/hdl/tf_mem_tproj.vhd | 1 - 4 files changed, 6 deletions(-) diff --git a/IntegrationTests/common/hdl/tf_mem.vhd b/IntegrationTests/common/hdl/tf_mem.vhd index d56609db655..f4314c3fc80 100644 --- a/IntegrationTests/common/hdl/tf_mem.vhd +++ b/IntegrationTests/common/hdl/tf_mem.vhd @@ -50,7 +50,6 @@ entity tf_mem is enb : in std_logic; --! Read Enable, for additional power savings, disable when not in use rsta : in std_logic; --! Input reset rstb : in std_logic; --! Output reset (does not affect memory contents) - regceb : in std_logic; --! Output register enable addra : in std_logic_vector(clogb2(RAM_DEPTH)-1 downto 0); --! Write address bus, width determined from RAM_DEPTH dina : in std_logic_vector(RAM_WIDTH-1 downto 0); --! RAM input data addrb : in std_logic_vector(clogb2(RAM_DEPTH)-1 downto 0); --! Read address bus, width determined from RAM_DEPTH diff --git a/IntegrationTests/common/hdl/tf_mem_bin.vhd b/IntegrationTests/common/hdl/tf_mem_bin.vhd index 8a90b86b71c..9ec055dc169 100644 --- a/IntegrationTests/common/hdl/tf_mem_bin.vhd +++ b/IntegrationTests/common/hdl/tf_mem_bin.vhd @@ -115,9 +115,6 @@ entity tf_mem_bin is --! Output reset (does not affect memory contents) rstb : in std_logic; - --! Output register enable - regceb : in std_logic; - --! Read address bus, width determined from RAM_DEPTH and NCOPY addrb : in std_logic_vector(NUM_COPY*RAM_DEPTH_BITS-1 downto 0); diff --git a/IntegrationTests/common/hdl/tf_mem_tpar.vhd b/IntegrationTests/common/hdl/tf_mem_tpar.vhd index 67c1b9da6a9..fde397daa3e 100644 --- a/IntegrationTests/common/hdl/tf_mem_tpar.vhd +++ b/IntegrationTests/common/hdl/tf_mem_tpar.vhd @@ -50,7 +50,6 @@ entity tf_mem_tpar is enb : in std_logic; --! Read Enable, for additional power savings, disable when not in use rsta : in std_logic; --! Input reset rstb : in std_logic; --! Output reset (does not affect memory contents) - regceb : in std_logic; --! Output register enable addra : in std_logic_vector(clogb2(RAM_DEPTH)-1 downto 0); --! Write address bus, width determined from RAM_DEPTH dina : in std_logic_vector(RAM_WIDTH-1 downto 0); --! RAM input data addrb : in std_logic_vector(clogb2(RAM_DEPTH)-1 downto 0); --! Read address bus, width determined from RAM_DEPTH diff --git a/IntegrationTests/common/hdl/tf_mem_tproj.vhd b/IntegrationTests/common/hdl/tf_mem_tproj.vhd index a5e838245e1..c975bb336e8 100644 --- a/IntegrationTests/common/hdl/tf_mem_tproj.vhd +++ b/IntegrationTests/common/hdl/tf_mem_tproj.vhd @@ -50,7 +50,6 @@ entity tf_mem_tproj is enb : in std_logic; --! Read Enable, for additional power savings, disable when not in use rsta : in std_logic; --! Input reset rstb : in std_logic; --! Output reset (does not affect memory contents) - regceb : in std_logic; --! Output register enable addra : in std_logic_vector(clogb2(RAM_DEPTH)-1 downto 0); --! Write address bus, width determined from RAM_DEPTH dina : in std_logic_vector(RAM_WIDTH-1 downto 0); --! RAM input data addrb : in std_logic_vector(clogb2(RAM_DEPTH)-1 downto 0); --! Read address bus, width determined from RAM_DEPTH