diff --git a/IntegrationTests/common/hdl/mem_reader.vhd b/IntegrationTests/common/hdl/mem_reader.vhd index 4e4e5a5914b..cdecfd6d134 100644 --- a/IntegrationTests/common/hdl/mem_reader.vhd +++ b/IntegrationTests/common/hdl/mem_reader.vhd @@ -190,9 +190,11 @@ begin dout <= din; - --if (valid3='1') then - -- report "mem_reader: "&time'image(now)&" "&NAME&" addr="&to_bstring(addr_counter2)&" din="&to_bstring(din)&" valid="&to_bstring(valid3); - --end if; + if (DEBUG) then + if (valid3='1') then + report "mem_reader: "&time'image(now)&" "&NAME&" addr="&to_hstring(addr_counter2)&" din="&to_hstring(din)&" valid="&to_bstring(valid3); + end if; + end if; end if; diff --git a/IntegrationTests/common/hdl/tf_mem.vhd b/IntegrationTests/common/hdl/tf_mem.vhd index 49fff07e510..b1a58861770 100644 --- a/IntegrationTests/common/hdl/tf_mem.vhd +++ b/IntegrationTests/common/hdl/tf_mem.vhd @@ -37,7 +37,9 @@ entity tf_mem is RAM_PERFORMANCE : string := "HIGH_PERFORMANCE";--! Select "HIGH_PERFORMANCE" (2 clk latency) or "LOW_LATENCY" (1 clk latency) NAME : string := "MEMNAME"; --! Name of mem for printout DEBUG : boolean := false; --! If true prints debug info - MEM_TYPE : string := "block" --! specifies RAM type (block/ultra) + MEM_TYPE : string := "block"; --! specifies RAM type (block/ultra) + FILE_WRITE : boolean := true --! If set to true will + --write debug output for memory ); port ( clka : in std_logic; --! Write clock @@ -112,15 +114,18 @@ begin assert (RAM_DEPTH = NUM_PAGES*PAGE_LENGTH) report "User changed RAM_DEPTH" severity FAILURE; process(clka) + + variable initialized : boolean := false; variable init : std_logic := '1'; --FIXME hardcoded number variable slv_clk_cnt : std_logic_vector(6 downto 0) := (others => '0'); -- Clock counter + variable slv_clk_cnt_save : std_logic_vector(6 downto 0) := (others => '0'); -- Clock counter variable slv_page_cnt_save : std_logic_vector(clogb2(NUM_PAGES)-1 downto 0) := (others => '0'); -- Page counter save variable slv_page_cnt : std_logic_vector(clogb2(NUM_PAGES)-1 downto 0) := (others => '0'); - variable page : integer := 0; - variable addr_in_page : integer := 0; - variable address : std_logic_vector(clogb2(RAM_DEPTH)-1 downto 0); - variable overwrite : std_logic := '1'; + variable bx : integer := 0; + variable bx_save : integer := 0; + variable address : std_logic_vector(clogb2(RAM_DEPTH)-1 downto 0); + variable overwrite : std_logic := '1'; begin if rising_edge(clka) then -- ######################################### Start counter initially if DEBUG then @@ -132,15 +137,18 @@ begin end if; end if; slv_page_cnt_save := slv_page_cnt; + slv_clk_cnt_save := slv_clk_cnt; + bx_save := bx; if (init = '0' and to_integer(unsigned(slv_clk_cnt)) < MAX_ENTRIES-1) then -- ####### Counter nent slv_clk_cnt := std_logic_vector(unsigned(slv_clk_cnt)+1); --report time'image(now)&" tf_mem "&NAME&" increment vi_clk_cnt:"&integer'image(vi_clk_cnt); elsif (to_integer(unsigned(slv_clk_cnt)) >= MAX_ENTRIES-1) then -- -1 not included --report time'image(now)&" tf_mem "&NAME&" goto next page"; slv_clk_cnt := (others => '0'); + bx := bx + 1; --assert (vi_page_cnt < NUM_PAGES) report "vi_page_cnt out of range" severity error; - if (to_integer(unsigned(slv_page_cnt)) < NUM_PAGES-1) then -- Assuming linear continuous page access - slv_page_cnt := std_logic_vector(unsigned(slv_page_cnt)+1); + if (to_integer(unsigned(slv_page_cnt)) < NUM_PAGES - 1) then -- Assuming linear continuous page access + slv_page_cnt := std_logic_vector(unsigned(slv_page_cnt) + 1); --report time'image(now)&" tf_mem "&NAME&" increment vi_page_cnt:"&integer'image(vi_page_cnt); else --report time'image(now)&" tf_mem "&NAME&" resetting vi_page_cnt"; @@ -156,6 +164,7 @@ begin --use sync_nent transition to synchronize at BX (page) 1 --report time'image(now)&" tf_mem "&NAME&" sync_nent"; init := '0'; + bx := 1; slv_clk_cnt := (others => '0'); slv_page_cnt := (0 => '1', others => '0'); end if; @@ -169,6 +178,11 @@ begin end if; --report "tf_mem "&time'image(now)&" "&NAME&" page writeaddr "&" "&to_bstring(slv_page_cnt_save)&" "&to_bstring(address)&" "&to_bstring(overwrite)&" "&to_bstring(dina)&" addra "&to_bstring(addra); sa_RAM_data(to_integer(unsigned(address))) <= dina; -- Write data + if FILE_WRITE then + write_data(initialized, "../../../../../dataOut/"&NAME&".dat",time'image(now), integer'image(bx_save), to_hstring(slv_clk_cnt_save), to_hstring(address(clogb2(RAM_DEPTH)-clogb2(NUM_PAGES)-1 downto 0)), to_hstring(dina) ); + end if; + initialized := true; + if (overwrite = '0') then nent_o(to_integer(unsigned(slv_page_cnt_save))) <= std_logic_vector(to_unsigned(to_integer(unsigned(nent_o(to_integer(unsigned(slv_page_cnt_save))))) + 1, nent_o(to_integer(unsigned(slv_page_cnt_save)))'length)); -- + 1 (slv) end if; diff --git a/IntegrationTests/common/hdl/tf_mem_bin.vhd b/IntegrationTests/common/hdl/tf_mem_bin.vhd index a3b8c38482d..8a90b86b71c 100644 --- a/IntegrationTests/common/hdl/tf_mem_bin.vhd +++ b/IntegrationTests/common/hdl/tf_mem_bin.vhd @@ -85,8 +85,13 @@ entity tf_mem_bin is --! (1 clk latency) RAM_PERFORMANCE : string := "HIGH_PERFORMANCE"; + DEBUG : boolean := false; --! Debug printout + --! Memory name - used for debugging - NAME : string := "MEMNAME" + NAME : string := "MEMNAME"; + FILE_WRITE : boolean := true --! If set to true will + --write debug output for memory + ); port ( @@ -289,12 +294,18 @@ begin assert (RAM_DEPTH = NUM_PAGES*PAGE_LENGTH) report "User changed RAM_DEPTH" severity FAILURE; process(clka) + + variable initialized : boolean := false; + variable init : std_logic := '1'; variable new_bx : boolean := false; --FIXME hardcoded number variable slv_clk_cnt : std_logic_vector(6 downto 0) := (others => '0'); -- Clock counter + variable slv_clk_cnt_save : std_logic_vector(6 downto 0) := (others => '0'); -- Clock counter variable slv_page_cnt : std_logic_vector(NUM_PAGES_BITS-1 downto 0) := (others => '0'); -- Page counter variable slv_page_cnt_save : std_logic_vector(NUM_PAGES_BITS-1 downto 0) := (others => '0'); -- Page counter + variable bx : integer := 0; + variable bx_save : integer := 0; --! Extract phi and rz bin address alias vi_nent_idx : std_logic_vector(NUM_PHI_BITS+NUM_RZ_BITS-1 downto 0) is addra(NUM_PHI_BITS + NUM_RZ_BITS - 1 downto 0); @@ -320,10 +331,13 @@ begin if rising_edge(clka) then new_bx := false; slv_page_cnt_save := slv_page_cnt; + slv_clk_cnt_save := slv_clk_cnt; + bx_save := bx; if (init = '0' and to_integer(unsigned(slv_clk_cnt)) < MAX_ENTRIES-1) then -- ####### Counter nent slv_clk_cnt := std_logic_vector(unsigned(slv_clk_cnt)+1); elsif (to_integer(unsigned(slv_clk_cnt)) >= MAX_ENTRIES-1) then -- -1 not included slv_clk_cnt := (others => '0'); + bx := bx + 1; new_bx := true; validbinmasktmp <= (others => '0'); nentry_mask_tmp <= (others => '0'); -- Do we need this??? FIXME @@ -343,6 +357,7 @@ begin --use sync_nent transition to synchronize at BX (page) 1 --report time'image(now)&" tf_mem_bin "&NAME&" sync_nent"; init := '0'; + bx := 1; slv_clk_cnt := (others => '0'); slv_page_cnt := (0 => '1', others => '0'); validbinmasktmp <= (others => '0'); @@ -369,24 +384,27 @@ begin -- Protect against over writing nentry_tmp and nentry_mask_tmp if reset -- earlier due to going to new BX. Can this be done more cleanly? - if (new_bx = false) then - nentry_tmp(to_integer(unsigned(vi_nent_idx))) <= std_logic_vector(nentry); - nentry_mask_tmp(to_integer(unsigned(vi_nent_idx))) <= '1'; - end if; - phimask := ( 0 => '1', others => '0'); phimask := std_logic_vector(shift_left(unsigned(phimask), to_integer(unsigned(phibits)))); binmaskvalue := (binmasktmp(to_integer(unsigned(rzbits))) and validbinmasktmp(to_integer(unsigned(rzbits)))) or phimask; - binmasktmp(to_integer(unsigned(rzbits))) <= binmaskvalue; + if (DEBUG) then + report time'image(now)&" tf_mem_bin: " & NAME & " rzbits=" & to_hstring(rzbits) & " phibits=" & to_hstring(phibits) & " phimask=" & to_bstring(phimask) & " binmasktmp=" & to_bstring(binmasktmp(to_integer(unsigned(rzbits)))) & " validbinmasktmp=" & to_bstring(validbinmasktmp(to_integer(unsigned(rzbits)))) & " " & to_bstring(validbinmasktmp) & " binmaskvalue=" & to_bstring(binmaskvalue); + end if; + + if (new_bx = false) then + nentry_tmp(to_integer(unsigned(vi_nent_idx))) <= std_logic_vector(nentry); + nentry_mask_tmp(to_integer(unsigned(vi_nent_idx))) <= '1'; + binmasktmp(to_integer(unsigned(rzbits))) <= binmaskvalue; + validbinmasktmp(to_integer(unsigned(rzbits))) <= '1'; + end if; page_rzbits := slv_page_cnt_save & rzbits; binmaskA(to_integer(unsigned(page_rzbits))) <= binmaskvalue; binmaskB(to_integer(unsigned(page_rzbits))) <= binmaskvalue; - validbinmasktmp(to_integer(unsigned(rzbits))) <= '1'; validbinmask(to_integer(unsigned(page_rzbits))) <= '1'; @@ -395,7 +413,11 @@ begin for icopy in 0 to NUM_COPY-1 loop sa_RAM_data(icopy)(to_integer(unsigned(writeaddr))) <= dina; end loop; - + if FILE_WRITE then + write_data(initialized, "../../../../../dataOut/"&NAME&".dat",time'image(now), integer'image(bx_save), to_hstring(slv_clk_cnt_save), to_hstring(vi_nent_idx), to_hstring(dina) ); + end if; + initialized := true; + --report "tf_mem_bin write nent :"&time'image(now)&" "&NAME&" phi:"&to_bstring(phibits)&" rz:"&to_bstring(rzbits)&" "&to_bstring(nentry)&" "&to_bstring(writeaddr); if (to_integer(unsigned(phibits)) = 0) then @@ -483,7 +505,9 @@ begin for i in 0 to NUM_COPY-1 loop if (enb(i)='1') then - -- report "tf_mem_bin read addrb "&NAME&" "&integer'image(i)&" "&time'image(now)&" "& NAME & " " & to_hstring(addrb((i+1)*RAM_DEPTH_BITS-1 downto i*RAM_DEPTH_BITS))&" "&to_hstring(sa_RAM_data(i)(to_integer(unsigned(addrb((i+1)*RAM_DEPTH_BITS-1 downto i*RAM_DEPTH_BITS)))))&" "&to_bstring(validbinmask(to_integer(unsigned(addrb((i+1)*RAM_DEPTH_BITS-1 downto i*RAM_DEPTH_BITS+7)))))&" "&to_bstring(binmaskA(to_integer(unsigned(addrb((i+1)*RAM_DEPTH_BITS-1 downto i*RAM_DEPTH_BITS+7))))(to_integer(unsigned(addrb((i+1)*RAM_DEPTH_BITS-5 downto i*RAM_DEPTH_BITS+4))))); + if (DEBUG) then + report "tf_mem_bin read addrb "&NAME&" "&integer'image(i)&" "&time'image(now)&" "& NAME & " " & to_hstring(addrb((i+1)*RAM_DEPTH_BITS-1 downto i*RAM_DEPTH_BITS))&" "&to_hstring(sa_RAM_data(i)(to_integer(unsigned(addrb((i+1)*RAM_DEPTH_BITS-1 downto i*RAM_DEPTH_BITS)))))&" "&to_bstring(validbinmask(to_integer(unsigned(addrb((i+1)*RAM_DEPTH_BITS-1 downto i*RAM_DEPTH_BITS+7)))))&" "&to_bstring(binmaskA(to_integer(unsigned(addrb((i+1)*RAM_DEPTH_BITS-1 downto i*RAM_DEPTH_BITS+7))))(to_integer(unsigned(addrb((i+1)*RAM_DEPTH_BITS-5 downto i*RAM_DEPTH_BITS+4)))))&" "&to_bstring(binmaskA(to_integer(unsigned(addrb((i+1)*RAM_DEPTH_BITS-1 downto i*RAM_DEPTH_BITS+7))))); + end if; sv_RAM_row(i) <= sa_RAM_data(i)(to_integer(unsigned(addrb((i+1)*RAM_DEPTH_BITS-1 downto i*RAM_DEPTH_BITS)))); end if; end loop; diff --git a/IntegrationTests/common/hdl/tf_mem_tpar.vhd b/IntegrationTests/common/hdl/tf_mem_tpar.vhd index f5226daa678..67c1b9da6a9 100644 --- a/IntegrationTests/common/hdl/tf_mem_tpar.vhd +++ b/IntegrationTests/common/hdl/tf_mem_tpar.vhd @@ -38,7 +38,10 @@ entity tf_mem_tpar is INIT_HEX : boolean := true; --! Read init file in hex (default) or bin RAM_PERFORMANCE : string := "HIGH_PERFORMANCE";--! Select "HIGH_PERFORMANCE" (2 clk latency) or "LOW_LATENCY" (1 clk latency) NAME : string := "MEMNAME"; --! Name of mem for printout - DEBUG : boolean := false --! If true prints debug info + DEBUG : boolean := false; --! If true prints debug info + FILE_WRITE : boolean := true --! If set to true will + --write debug output for memory + ); port ( clka : in std_logic; --! Write clock @@ -116,13 +119,18 @@ assert (PAGE_LENGTH = 128) report "PAGE_LENGTH in tf_mem_tpar has to be 128" sev process(clka) + + variable initialized : boolean := false; variable init : std_logic := '1'; variable slv_clk_cnt : std_logic_vector(clogb2(PAGE_LENGTH)-1 downto 0) := (others => '0'); -- Clock counter + variable slv_clk_cnt_save : std_logic_vector(clogb2(PAGE_LENGTH)-1 downto 0) := (others => '0'); -- Clock counter variable slv_page_cnt_save : std_logic_vector(clogb2(NUM_PAGES)-1 downto 0) := (others => '0'); -- Page counter save variable slv_page_cnt : std_logic_vector(clogb2(NUM_PAGES)-1 downto 0) := (others => '0'); variable tpage : std_logic_vector(clogb2(NUM_TPAGES)-1 downto 0) := (others => '0'); variable nentaddress : std_logic_vector(clogb2(NUM_TPAGES*NUM_PAGES)-1 downto 0) := (others => '0'); variable address : std_logic_vector(clogb2(RAM_DEPTH)-1 downto 0); + variable bx : integer := 0; + variable bx_save : integer := 0; begin if rising_edge(clka) then -- ######################################### Start counter initially @@ -145,10 +153,13 @@ begin --end if; slv_page_cnt_save := slv_page_cnt; + slv_clk_cnt_save := slv_clk_cnt; + bx_save := bx; if (init = '0' and to_integer(unsigned(slv_clk_cnt)) < MAX_ENTRIES-1) then slv_clk_cnt := std_logic_vector(unsigned(slv_clk_cnt)+1); elsif (to_integer(unsigned(slv_clk_cnt)) >= MAX_ENTRIES-1) then slv_clk_cnt := (others => '0'); + bx := bx + 1; if (to_integer(unsigned(slv_page_cnt)) < NUM_PAGES-1) then slv_page_cnt := std_logic_vector(unsigned(slv_page_cnt)+1); else @@ -165,6 +176,7 @@ begin --use sync_nent transition to synchronize at BX (page) 1 --report time'image(now)&" tf_mem "&NAME&" sync_nent"; init := '0'; + bx := 1; slv_clk_cnt := (others => '0'); slv_page_cnt := (0 => '1', others => '0'); end if; @@ -181,6 +193,10 @@ begin end if; --report time'image(now)&" tf_mem_tpar "&NAME&" tpage:"&to_bstring(tpage)&" writeaddr "&to_bstring(slv_page_cnt_save)&" "&to_bstring(address)&" nentaddress nent:"&to_bstring(nentaddress)&" "&to_bstring(nent_o(to_integer(unsigned(nentaddress))))&" "&to_bstring(dina); sa_RAM_data(to_integer(unsigned(address))) <= dina; -- Write data + if FILE_WRITE then + write_data(initialized, "../../../../../dataOut/"&NAME&".dat",time'image(now), integer'image(bx_save), to_hstring(slv_clk_cnt_save), to_hstring(address(clogb2(NUM_TPAGES)+ 7 - 1 downto 0)), to_hstring(dina) ); + end if; + initialized := true; mask_o(to_integer(unsigned(slv_page_cnt_save)))(to_integer(unsigned(tpage))) <= '1'; end if; end if; diff --git a/IntegrationTests/common/hdl/tf_mem_tproj.vhd b/IntegrationTests/common/hdl/tf_mem_tproj.vhd index 6e673af4d56..a5e838245e1 100644 --- a/IntegrationTests/common/hdl/tf_mem_tproj.vhd +++ b/IntegrationTests/common/hdl/tf_mem_tproj.vhd @@ -38,7 +38,10 @@ entity tf_mem_tproj is INIT_HEX : boolean := true; --! Read init file in hex (default) or bin RAM_PERFORMANCE : string := "HIGH_PERFORMANCE";--! Select "HIGH_PERFORMANCE" (2 clk latency) or "LOW_LATENCY" (1 clk latency) NAME : string := "MEMNAME"; --! Name of mem for printout - DEBUG : boolean := false --! If true prints debug info + DEBUG : boolean := false; --! If true prints debug info + FILE_WRITE : boolean := true --! If set to true will + --write debug output for memory + ); port ( clka : in std_logic; --! Write clock @@ -115,13 +118,19 @@ assert (RAM_DEPTH = NUM_TPAGES*NUM_PAGES*PAGE_LENGTH) report "User changed RAM_ assert (PAGE_LENGTH = 64) report "PAGE_LENGTH in tf_mem_tproj has to be 64" severity FAILURE; process(clka) + + variable initialized : boolean := false; variable init : std_logic := '1'; variable slv_clk_cnt : std_logic_vector(clogb2(PAGE_LENGTH*2)-1 downto 0) := (others => '0'); -- Hack... + variable slv_clk_cnt_save : std_logic_vector(clogb2(PAGE_LENGTH*2)-1 downto 0) := (others => '0'); -- Hack... variable slv_page_cnt_save : std_logic_vector(clogb2(NUM_PAGES)-1 downto 0) := (others => '0'); variable slv_page_cnt : std_logic_vector(clogb2(NUM_PAGES)-1 downto 0) := (others => '0'); variable tpage : std_logic_vector(clogb2(NUM_TPAGES)-1 downto 0) := (others => '0'); variable nentaddress : std_logic_vector(clogb2(NUM_TPAGES*NUM_PAGES)-1 downto 0) := (others => '0'); variable address : std_logic_vector(clogb2(RAM_DEPTH)-1 downto 0); + variable bx : integer := 0; + variable bx_save : integer := 0; + begin if rising_edge(clka) then -- ######################################### Start counter initially --if DEBUG then @@ -142,10 +151,13 @@ begin --end if; --end if; slv_page_cnt_save := slv_page_cnt; + slv_clk_cnt_save := slv_clk_cnt; + bx_save := bx; if (init = '0' and to_integer(unsigned(slv_clk_cnt)) < MAX_ENTRIES-1) then slv_clk_cnt := std_logic_vector(unsigned(slv_clk_cnt)+1); elsif (to_integer(unsigned(slv_clk_cnt)) >= MAX_ENTRIES-1) then slv_clk_cnt := (others => '0'); + bx := bx + 1; if (to_integer(unsigned(slv_page_cnt)) < NUM_PAGES-1) then slv_page_cnt := std_logic_vector(unsigned(slv_page_cnt)+1); else @@ -162,6 +174,7 @@ begin --use sync_nent transition to synchronize at BX (page) 1 --report time'image(now)&" tf_mem "&NAME&" sync_nent"; init := '0'; + bx := 1; slv_clk_cnt := (others => '0'); slv_page_cnt := (0 => '1', others => '0'); end if; @@ -178,10 +191,16 @@ begin address := nentaddress&std_logic_vector(to_unsigned(0, nent_o(to_integer(unsigned(nentaddress)))'length)); nent_o(to_integer(unsigned(nentaddress))) <= std_logic_vector(to_unsigned(1, nent_o(to_integer(unsigned(nentaddress)))'length)); end if; - --report time'image(now)&" tf_mem_tproj "&NAME&" addra:"&to_bstring(addra)&" tpage:"&to_bstring(tpage)&" writeaddr "&to_bstring(slv_page_cnt_save)&" "&to_bstring(address)&" nentaddress nent:"&to_bstring(nentaddress)&" "&to_bstring(nent_o(to_integer(unsigned(nentaddress))))&" "&to_bstring(dina); - if (to_integer(unsigned(nent_o(to_integer(unsigned(nentaddress))))) /= 63) then + if DEBUG then + report time'image(now)&" tf_mem_tproj "&NAME&" addra:"&to_hstring(addra)&" tpage:"&to_hstring(tpage)&" writeaddr "&to_hstring(slv_page_cnt_save)&" "&to_hstring(address)&" nentaddress nent:"&to_hstring(nentaddress)&" "&to_hstring(nent_o(to_integer(unsigned(nentaddress))))&" "&to_hstring(dina); + end if; + if (to_integer(unsigned(nent_o(to_integer(unsigned(nentaddress))))) /= 63 or mask_o(to_integer(unsigned(slv_page_cnt_save)))(to_integer(unsigned(tpage))) /= '1') then sa_RAM_data(to_integer(unsigned(address))) <= dina; -- Write data mask_o(to_integer(unsigned(slv_page_cnt_save)))(to_integer(unsigned(tpage))) <= '1'; + if FILE_WRITE then + write_data(initialized, "../../../../../dataOut/"&NAME&".dat",time'image(now), integer'image(bx_save), to_hstring(slv_clk_cnt_save), to_hstring(address(clogb2(NUM_TPAGES)+ 6 - 1 downto 0)), to_hstring(dina) ); + end if; + initialized := true; end if; end if; end if; diff --git a/IntegrationTests/common/hdl/tf_merge_streamer.vhd b/IntegrationTests/common/hdl/tf_merge_streamer.vhd index 8e791de80db..30cf0971374 100644 --- a/IntegrationTests/common/hdl/tf_merge_streamer.vhd +++ b/IntegrationTests/common/hdl/tf_merge_streamer.vhd @@ -26,13 +26,14 @@ use work.tf_pkg.all; entity tf_merge_streamer is generic ( - NAME : string := "MERGERNAME"; --! Name of mem for printout - RAM_WIDTH: natural := 72; - NUM_PAGES : natural := 8; - RAM_DEPTH : natural := NUM_PAGES * PAGE_LENGTH; - NUM_INPUTS : natural := 4; - NUM_EXTRA_BITS: natural := 2; - ADDR_WIDTH : natural := 7 + NAME : string := "MERGERNAME"; --! Name of mem for printout + RAM_WIDTH : natural := 72; + NUM_PAGES : natural := 8; + RAM_DEPTH : natural := NUM_PAGES * PAGE_LENGTH; + NUM_INPUTS : natural := 4; + NUM_EXTRA_BITS : natural := 2; + FILE_WRITE : boolean := false --! If set to true will + --write debug output for memory ); port ( bx_in : in std_logic_vector(2 downto 0 ); @@ -66,6 +67,7 @@ architecture RTL of tf_merge_streamer is type mem_count_arr is array(MAX_INPUTS-1 downto 0) of integer; type toread_arr is array(pipe_stages-1 downto 0) of integer range 0 to 3; + type bx_array is array(pipe_stages-1 downto 0) of integer; type bx_arr is array(pipe_stages downto 0) of std_logic_vector(2 downto 0); type addr_arr_arr is array(MAX_INPUTS-1 downto 0) of std_logic_vector(LOG2_RAM_DEPTH-1 downto 0); @@ -76,6 +78,7 @@ architecture RTL of tf_merge_streamer is signal valid : std_logic_vector(pipe_stages-1 downto 0) := (others => '0'); signal bx_pipe : bx_arr := (others => (others => '0')); + signal bx_save : bx_array; signal addr_arr_int : addr_arr_arr := (others => (others => '0')); signal bx_last : std_logic_vector(2 downto 0) := "111"; signal bx_in_latch : std_logic_vector(2 downto 0) := "111"; --since output triggered by BX change, initializing bx_in_latch to 7 will start write on first valid bx (0) @@ -85,6 +88,8 @@ architecture RTL of tf_merge_streamer is begin process(clk) + variable initialized : boolean := false; + variable bx : integer := -1; variable nent_arr: nent_array; variable din_arr: din_array; variable bx_change : boolean := false; -- indicates to the module whether or not the bx has changed compared to the previous clock @@ -100,7 +105,7 @@ begin begin if rising_edge(clk) then - + bx_save(0) <= bx; bx_in_vld_3 := bx_in_vld_2; bx_in_vld_2 := bx_in_vld_1; bx_in_vld_1 := bx_in_vld; @@ -108,6 +113,7 @@ begin current_page_save := current_page; if (bx_in_vld_3 = '1') then + bx := bx + 1; bx_in_latch := bx_in; current_page := to_integer(unsigned(bx_in)) mod NUM_PAGES; end if; @@ -130,9 +136,9 @@ begin --report "tf_merge_streamer "&time'image(now)&" "&NAME&" readmask="&to_bstring(readmask)&" nextread="&integer'image(nextread)&" mem_count(nextread)="&integer'image(mem_count(nextread)); valid(0) <= '1'; --loop through starting with the next input in front of the current to-read (round-robin) - for i in 0 to 3 loop - if (readmask((toread(0) - i) mod 4) = '1') then - nextread := (toread(0) - i) mod 4; + for i in 3 downto 0 loop + if (readmask(i) = '1') then + nextread := i; end if; end loop; addr_arr_int(nextread) <= std_logic_vector(to_unsigned(current_page_save*page_length + mem_count(nextread), LOG2_RAM_DEPTH)); @@ -171,8 +177,16 @@ begin if valid(pipe_stages-1) ='1' then if (NUM_EXTRA_BITS > 0) then merged_dout <= '1' & std_logic_vector(to_unsigned(toread(pipe_stages-1),NUM_EXTRA_BITS)) & din_arr(toread(pipe_stages-1)); + if FILE_WRITE then + write_data(initialized, "../../../../../dataOut/"&NAME&".dat",time'image(now), integer'image(bx_save(pipe_stages-1)), " ", " ", to_hstring('1' & std_logic_vector(to_unsigned(toread(pipe_stages-1),NUM_EXTRA_BITS)) & din_arr(toread(pipe_stages-1)))); + end if; + initialized := true; else merged_dout <= '1' & din_arr(toread(pipe_stages-1)); + if FILE_WRITE then + write_data(initialized, "../../../../../dataOut/"&NAME&".dat",time'image(now), integer'image(bx_save(pipe_stages-1)), " ", " ", to_hstring(din_arr(toread(pipe_stages-1)))); + end if; + initialized := true; end if ; else merged_dout <= (others => '0'); @@ -182,6 +196,7 @@ begin bx_pipe(0) <= bx_in_latch; bx_out <= bx_pipe(pipe_stages); for j in pipe_stages-2 downto 0 loop + bx_save(j+1) <= bx_save(j); valid(j+1) <= valid(j); toread(j+1) <= toread(j); end loop; diff --git a/IntegrationTests/common/hdl/tf_pkg.vhd b/IntegrationTests/common/hdl/tf_pkg.vhd index ba759a161bf..157e8240660 100644 --- a/IntegrationTests/common/hdl/tf_pkg.vhd +++ b/IntegrationTests/common/hdl/tf_pkg.vhd @@ -193,6 +193,15 @@ package tf_pkg is n_entries_p2 : in t_arr8_8b; --! Number of entries per page n_entries_p2_we : in t_arr8_1b --! Number of entries per page write enable ); + procedure write_data( + INITIALIZED : in boolean; + file_path : in string; + tm : in string; + bx : in string; + clk : in string; + addr : in string; + data : in string + ); end package tf_pkg; @@ -514,4 +523,34 @@ package body tf_pkg is file_close(file_out); end write_emData_line_8p; + procedure write_data( + INITIALIZED : boolean; + file_path : string; + tm : string; + bx : string; + clk : string; + addr : string; + data : string) is + file file_out : text ; + variable line_out : line; + variable FILE_STATUS : file_open_status; + begin + if (not INITIALIZED) then + file_open(FILE_STATUS, file_out, file_path, WRITE_MODE); + assert (FILE_STATUS = open_ok) report "Failed to open file "&file_path severity FAILURE; + write(line_out, string'(" TIME (ns) BX CLK ADDR DATA")); + writeline(file_out, line_out); + else + file_open(FILE_STATUS, file_out, file_path, APPEND_MODE); + assert (FILE_STATUS = open_ok) report "Failed to open file "&file_path severity FAILURE; + end if; + write(line_out, NOW, right, 10); + write(line_out, bx, right, 8); + write(line_out, string'("0x")&clk, right, 8); + write(line_out, string'("0x")&addr, right, 8); + write(line_out, string'("0x")&data, right, 25); + writeline(file_out, line_out); + file_close(file_out); + end write_data; + end package body tf_pkg; diff --git a/IntegrationTests/common/script/CompareMemPrintsFW.py b/IntegrationTests/common/script/CompareMemPrintsFW.py index 67404e0d065..76707a12271 100644 --- a/IntegrationTests/common/script/CompareMemPrintsFW.py +++ b/IntegrationTests/common/script/CompareMemPrintsFW.py @@ -135,7 +135,7 @@ def compare(comparison_filename="", fail_on_error=False, file_location='./', pre print("Comparing TB results "+str(comparison_filename)+" to ref. file "+str(reference_filename)+" ... ") # Read column names from comparison file - column_names = list(pd.read_csv(file_location+"/"+comparison_filename,sep='\s+',nrows=1)) + column_names = list(pd.read_csv(file_location+"/"+comparison_filename,sep='\\s+',nrows=1)) if verbose: print(column_names) # Check if binned memory @@ -144,49 +144,27 @@ def compare(comparison_filename="", fail_on_error=False, file_location='./', pre else: is_binned = False - column_selections = ['TIME', 'BX', 'ADDR', 'DATA'] + column_selections = ['TIME', '(ns)', 'BX', 'CLK', 'ADDR', 'DATA'] # Open the comparison (= VHDL test-bench output) data - data = pd.read_csv(file_location+"/"+comparison_filename,sep='\s+',header=0,names=column_names,usecols=[i for i in column_names if any(select in i for select in column_selections)]) + data = pd.read_csv(file_location+"/"+comparison_filename,sep='\\s+',header=0,names=column_names,usecols=[i for i in column_names if any(select in i for select in column_selections)]) if verbose: print(data) # Can also just do data.head() - #Need to figure out how to handle the memory "overwrite" - this is a bit of a hack... - if (not is_binned) and ("TF_" not in comparison_filename) and ("AS_" not in comparison_filename) and ("MPAR_" not in comparison_filename): + #Remove duplicate addresses - this means we overwrote data, e.g. in the FM + if "FM_" in comparison_filename: + addresses = {} rows = [] + bx_old = -1; for index, row in data.iterrows(): - if row['ADDR'] == "0x01": - rows.append(index-1) # -1 to remove previos entry - data=data.drop(rows) - - #This is a hack to work around over flows in VMStub memories - if is_binned: - rows = [] - count = {} - for index, row in data.iterrows(): - entry = str(row['BX'])+row['ADDR'] - if entry not in count: - count[entry]=1 - else: - count[entry]+=1 - if count[entry]>15: - rows.append(index) - data=data.drop(rows) - - #This is a hack to work around over flows in MPROJ memories - if "MPROJ_" in comparison_filename: - rows = [] - count = {} - for index, row in data.iterrows(): - entry = str(row['BX'])+row['ADDR'] - if entry not in count: - count[entry]=1 - else: - count[entry]+=1 - if count[entry]>63: - rows.append(index) - data=data.drop(rows) - - # Hack to remove bin address + if row['BX'] != bx_old : + bx_old = row['BX'] + addresses = {} + if row['ADDR'] in addresses: + rows.append(addresses[row['ADDR']]) + addresses[row['ADDR']] = index + data = data.drop(rows) + + # Hack to remove bin address fix in emulation code printout? if "MPAR_" in comparison_filename: for index, row in data.iterrows(): adata = row['DATA'] @@ -221,10 +199,6 @@ def compare(comparison_filename="", fail_on_error=False, file_location='./', pre # Select the correct event from the comparison data selected_rows = selected_columns.loc[selected_columns['BX'] == ievent] - # Hack for FPGA1 Project as BX off by 0ne - if ("AS_" in comparison_filename and "n1" in comparison_filename) or "MPAR_" in comparison_filename: - selected_rows = selected_columns.loc[selected_columns['BX']-1 == ievent] - if len(selected_rows) == 0 and len(event) != 0: good = False number_of_missing_events += 1 @@ -232,9 +206,6 @@ def compare(comparison_filename="", fail_on_error=False, file_location='./', pre if fail_on_error: raise Exception(message) else: print("\t"+message) - # Select only the comparison data where the valid bit is set - #selected_rows = selected_rows.loc[selected_rows[selected_rows.columns[1]] == '0b1'] - # Check the length of the two sets # Raise an exception if the are fewer entries for a given event in the comparison data than in the reference data if len(selected_rows) != len(event): @@ -260,16 +231,13 @@ def compare(comparison_filename="", fail_on_error=False, file_location='./', pre if is_binned: bin, data = val - bin = bin.replace("0x","") + #bin = bin.replace("0x","") else: data = val # Raise exception if the values for a given entry don't match adata = selected_rows['DATA'][offset+ival] - if ("AS_" in comparison_filename) and ("n1" in comparison_filename): - adata=adata.replace("0x1","0x") - if adata != data: good = False number_of_value_mismatches += 1 @@ -280,13 +248,13 @@ def compare(comparison_filename="", fail_on_error=False, file_location='./', pre # Raise exception if the bin number of a given entry don't match elif is_binned: - ref_add = selected_rows['ADDR'][offset+ival][3:] - data_add = bin.upper() + ref_add = selected_rows['ADDR'][offset+ival] + data_add = bin.upper().replace('0X','0x') if ref_add != data_add: good = False number_of_value_mismatches += 1 message = "The bin for event "+str(ievent)+" stub "+str(selected_rows['DATA'][offset+ival])+" do not match!"\ - "\n\treference="+bin+" comparison="+str(selected_rows['ADDR'][offset+ival]) + "\n\treference="+str(ref_add)+" comparison="+str(data_add) if fail_on_error: raise Exception(message) else: print("\t\t"+message.replace("\n","\n\t\t")) @@ -318,7 +286,7 @@ def comparePredefined(args): raise FileNotFoundError(comparison_dir + " is empty. No files to compare.") # Find the lists of filenames - comparison_filename_list = [f for f in glob.glob(comparison_dir+"*.txt") if "debug" not in f and "cmp" not in f and "TW" not in f and "BW" not in f and "DW" not in f] # Remove debug and comparison files from file list, also also TW/BW output from TB (since TF output used instead). + comparison_filename_list = [f for f in glob.glob(comparison_dir+"*.dat") if "debug" not in f and "cmp" not in f and "TW" not in f and "BW" not in f and "DW" not in f] # Remove debug and comparison files from file list, also also TW/BW output from TB (since TF output used instead). comparison_filename_list.sort() reference_filename_list = [f.split('/')[-1].split('.')[0].replace("TEO", "TE").replace("TEI", "TE") for f in comparison_filename_list] # Remove file extension from comparison_filename_list and replace TEO/TEI with TE try: @@ -335,7 +303,7 @@ def comparePredefined(args): print("Summary of memories with errors") print("=================================") sys.stdout.flush() - os.system('grep "Bad events: [1-9]" dataOut/*cmp.txt') + os.system('grep "Bad events: [1-9]" dataOut/*cmp.dat') print("\n Accumulated number of errors =",ret_sum) diff --git a/emData/download.sh b/emData/download.sh index 3640e35ded9..ed049e9c940 100755 --- a/emData/download.sh +++ b/emData/download.sh @@ -1,27 +1,15 @@ #!/usr/bin/env bash set -e -### Test vectors correspond to fw_synch_250903 tag in cms-L1TK/cmssw repo ### - -## D98 detector geometry - -# Split modules - i.e. with PC and VMSMER -#memprints_url_split="https://cernbox.cern.ch/remote.php/dav/public-files/cAUD1B6sVbouL1P/MemPrints.tar.gz" -#luts_url_split="https://cernbox.cern.ch/remote.php/dav/public-files/O4binjyc9tEFGFH/LUTs.tar.gz" - -# Reduced Combined modules -#memprints_url_reducedcm="https://cernbox.cern.ch/remote.php/dav/public-files/ECMF704hrDY8sjO/MemPrints.tar.gz" -#luts_url_reducedcm="https://cernbox.cern.ch/remote.php/dav/public-files/UAMg2u9EWz9iI3Z/LUTs.tar.gz" - -## D110 detector geometry (C-simulation for PC_L2L3ABCD currently fails) +### Test vectors updated to fix configuration for missing allstub inner memoriesusing D110 geometry ### # Split modules - i.e. with PC and VMSMER -memprints_url_split="https://cernbox.cern.ch/remote.php/dav/public-files/rTMtu6T9vKXBmou/MemPrints.tar.gz" -luts_url_split="https://cernbox.cern.ch/remote.php/dav/public-files/RsXG1BOwjb4cAQN/LUTs.tar.gz" +luts_url_split="https://cernbox.cern.ch/remote.php/dav/public-files/bqqT3NRWwD25QI8/LUTs_250918.tgz" +memprints_url_split="https://cernbox.cern.ch/remote.php/dav/public-files/FoYh3CsYHKUlGNc/MemPrints_250918.tgz" # Reduced Combined modules -memprints_url_reducedcm="https://cernbox.cern.ch/remote.php/dav/public-files/HyFZX9shXIhA8ix/MemPrints.tar.gz" -luts_url_reducedcm="https://cernbox.cern.ch/remote.php/dav/public-files/MSJUMj9fYVm00Bx/LUTs.tar.gz" +memprints_url_reducedcm="https://cernbox.cern.ch/remote.php/dav/public-files/C8cmkVcIX67sGgP/MemPrints_Reduced_250918.tgz" +luts_url_reducedcm="https://cernbox.cern.ch/remote.php/dav/public-files/T4mnc4UXYXdKqxy/LUTs_Reduced_250918.tgz" # Function that prints information regarding the usage of this command function usage() { diff --git a/emData/project_generation_scripts b/emData/project_generation_scripts index 9a1943aeef5..19207361591 160000 --- a/emData/project_generation_scripts +++ b/emData/project_generation_scripts @@ -1 +1 @@ -Subproject commit 9a1943aeef5e0b141bc41cea44847746cc6bac10 +Subproject commit 19207361591d7062bf42d076bf93323b58005ed3