diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index a721e7ce78a..84d1b3aa907 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -231,7 +231,52 @@ TM-vivado-hls-build: VIVADO_VERSION: "2019.2" PROJ_NAME: "TM" # FW simulation --------------- -topReducedCombined-sim: +topReducedCombinedFPGA1-sim: + <<: *template_topTF-sim + allow_failure: true + variables: + VIVADO_VERSION: "2019.2" + PROJ_NAME: "ReducedCombinedConfig_FPGA1" + needs: + - job: download + - job: IR-vivado-hls-build + artifacts: false + - job: VMRCM-vivado-hls-build + artifacts: false + - job: VMSMER-vivado-hls-build + artifacts: false + - job: TP-vivado-hls-build + artifacts: false + - job: PC-vivado-hls-build + artifacts: false + - job: MP-vivado-hls-build + artifacts: false + - job: TB-vivado-hls-build + artifacts: false +# Check FW results --------------- +topReducedCombinedFPGA1-check-results: + <<: *template_check-results + allow_failure: true # FIXME: remove after all errors are fixed + variables: + VIVADO_VERSION: "2019.2" # Vivado not needed but it is part of the path that is called + PROJ_NAME: "ReducedCombinedConfig_FPGA1" + needs: + - download + - topReducedCombinedFPGA1-sim +# FW synthesis --------------- +topReducedCombinedFPGA1-synth: + <<: *template_topTF-synth + allow_failure: true + variables: + VIVADO_VERSION: "2019.2" + PROJ_NAME: "ReducedCombinedConfig_FPGA1" + needs: + - job: download + - job: topReducedCombinedFPGA1-sim + - job: topReducedCombinedFPGA1-check-results + artifacts: false +# FW simulation --------------- +topReducedCombinedFPGA2-sim: <<: *template_topTF-sim allow_failure: true variables: @@ -254,7 +299,7 @@ topReducedCombined-sim: - job: TB-vivado-hls-build artifacts: false # Check FW results --------------- -topReducedCombined-check-results: +topReducedCombinedFPGA2-check-results: <<: *template_check-results allow_failure: true # FIXME: remove after all errors are fixed variables: @@ -262,9 +307,9 @@ topReducedCombined-check-results: PROJ_NAME: "ReducedCombinedConfig_FPGA2" needs: - download - - topReducedCombined-sim + - topReducedCombinedFPGA2-sim # FW synthesis --------------- -topReducedCombined-synth: +topReducedCombinedFPGA2-synth: <<: *template_topTF-synth allow_failure: true variables: @@ -272,6 +317,6 @@ topReducedCombined-synth: PROJ_NAME: "ReducedCombinedConfig_FPGA2" needs: - job: download - - job: topReducedCombined-sim - - job: topReducedCombined-check-results + - job: topReducedCombinedFPGA2-sim + - job: topReducedCombinedFPGA2-check-results artifacts: false diff --git a/IntegrationTests/ReducedCombinedConfig_FPGA1/script/Makefile b/IntegrationTests/ReducedCombinedConfig_FPGA1/script/Makefile new file mode 100644 index 00000000000..7174b22feae --- /dev/null +++ b/IntegrationTests/ReducedCombinedConfig_FPGA1/script/Makefile @@ -0,0 +1,8 @@ +# Define base directory of firmware-hls clone. +FIRMWARE=$(shell git rev-parse --show-toplevel) +# MODIFY THESE LINES WHEN COPYING AND PASTING THIS MAKEFILE +TOP_FUNCS=$(FIRMWARE)/TopFunctions/ReducedCombinedConfig +MODULES=InputRouterTop_IR_DTC_PS10G_1_A InputRouterTop_IR_DTC_PS10G_1_B InputRouterTop_IR_DTC_PS10G_2_A InputRouterTop_IR_DTC_PS10G_2_B InputRouterTop_IR_DTC_PS10G_3_A InputRouterTop_IR_DTC_PS10G_3_B InputRouterTop_IR_DTC_PS_1_A InputRouterTop_IR_DTC_PS_1_B InputRouterTop_IR_DTC_PS_2_A InputRouterTop_IR_DTC_PS_2_B InputRouterTop_IR_DTC_negPS10G_1_A InputRouterTop_IR_DTC_negPS10G_1_B InputRouterTop_IR_DTC_negPS10G_2_A InputRouterTop_IR_DTC_negPS10G_2_B InputRouterTop_IR_DTC_negPS10G_3_A InputRouterTop_IR_DTC_negPS10G_3_B InputRouterTop_IR_DTC_negPS_1_A InputRouterTop_IR_DTC_negPS_1_B InputRouterTop_IR_DTC_negPS_2_A InputRouterTop_IR_DTC_negPS_2_B InputRouterTop_IR_DTC_2S_1_A InputRouterTop_IR_DTC_2S_1_B InputRouterTop_IR_DTC_2S_2_A InputRouterTop_IR_DTC_2S_2_B InputRouterTop_IR_DTC_2S_3_A InputRouterTop_IR_DTC_2S_3_B InputRouterTop_IR_DTC_2S_4_A InputRouterTop_IR_DTC_2S_4_B InputRouterTop_IR_DTC_neg2S_1_A InputRouterTop_IR_DTC_neg2S_1_B InputRouterTop_IR_DTC_neg2S_2_A InputRouterTop_IR_DTC_neg2S_2_B InputRouterTop_IR_DTC_neg2S_3_A InputRouterTop_IR_DTC_neg2S_3_B InputRouterTop_IR_DTC_neg2S_4_A InputRouterTop_IR_DTC_neg2S_4_B VMRouterCMTop_L1PHIA VMRouterCMTop_L1PHIB VMRouterCMTop_L1PHIC VMRouterCMTop_L1PHID VMRouterCMTop_L1PHIE VMRouterCMTop_L1PHIF VMRouterCMTop_L1PHIG VMRouterCMTop_L1PHIH VMRouterCMTop_L2PHIA VMRouterCMTop_L2PHIB VMRouterCMTop_L2PHIC VMRouterCMTop_L2PHID VMRouterCMTop_L3PHIA VMRouterCMTop_L3PHIB VMRouterCMTop_L3PHIC VMRouterCMTop_L3PHID VMRouterCMTop_L4PHIA VMRouterCMTop_L4PHIB VMRouterCMTop_L4PHIC VMRouterCMTop_L4PHID VMRouterCMTop_L5PHIA VMRouterCMTop_L5PHIB VMRouterCMTop_L5PHIC VMRouterCMTop_L5PHID VMRouterCMTop_L6PHIA VMRouterCMTop_L6PHIB VMRouterCMTop_L6PHIC VMRouterCMTop_L6PHID TrackletProcessor_L5L6A TrackletProcessor_L5L6B TrackletProcessor_L5L6C TrackletProcessor_L5L6D + +# Include rules for making the project. +include $(FIRMWARE)/IntegrationTests/common/script/Makefile.mk diff --git a/IntegrationTests/ReducedCombinedConfig_FPGA1/script/makeProject.tcl b/IntegrationTests/ReducedCombinedConfig_FPGA1/script/makeProject.tcl new file mode 100644 index 00000000000..74b350c3de0 --- /dev/null +++ b/IntegrationTests/ReducedCombinedConfig_FPGA1/script/makeProject.tcl @@ -0,0 +1,113 @@ +# Create Vivado project, with user HDL files & IP. +# Run this in IntegrationTests/xyz/script/ + +# Create project +set projName "Work" +set FPGA "xcvu13p-flga2577-2-e" +create_project -force ${projName} ./${projName} -part $FPGA +set_property target_language VHDL [current_project] + +# Rebuild user HLS IP repos index before adding any source files +set_property ip_repo_paths "./" [get_filesets sources_1] +update_ip_catalog -rebuild + +create_ip -name InputRouterTop_IR_DTC_PS10G_1_A -module_name IR_PS10G_1_A -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_PS10G_1_B -module_name IR_PS10G_1_B -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_PS10G_2_A -module_name IR_PS10G_2_A -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_PS10G_2_B -module_name IR_PS10G_2_B -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_PS10G_3_A -module_name IR_PS10G_3_A -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_PS10G_3_B -module_name IR_PS10G_3_B -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_PS_1_A -module_name IR_PS_1_A -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_PS_1_B -module_name IR_PS_1_B -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_PS_2_A -module_name IR_PS_2_A -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_PS_2_B -module_name IR_PS_2_B -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_negPS10G_1_A -module_name IR_negPS10G_1_A -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_negPS10G_1_B -module_name IR_negPS10G_1_B -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_negPS10G_2_A -module_name IR_negPS10G_2_A -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_negPS10G_2_B -module_name IR_negPS10G_2_B -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_negPS10G_3_A -module_name IR_negPS10G_3_A -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_negPS10G_3_B -module_name IR_negPS10G_3_B -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_negPS_1_A -module_name IR_negPS_1_A -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_negPS_1_B -module_name IR_negPS_1_B -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_negPS_2_A -module_name IR_negPS_2_A -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_negPS_2_B -module_name IR_negPS_2_B -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_2S_1_A -module_name IR_2S_1_A -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_2S_1_B -module_name IR_2S_1_B -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_2S_2_A -module_name IR_2S_2_A -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_2S_2_B -module_name IR_2S_2_B -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_2S_3_A -module_name IR_2S_3_A -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_2S_3_B -module_name IR_2S_3_B -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_2S_4_A -module_name IR_2S_4_A -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_2S_4_B -module_name IR_2S_4_B -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_neg2S_1_A -module_name IR_neg2S_1_A -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_neg2S_1_B -module_name IR_neg2S_1_B -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_neg2S_2_A -module_name IR_neg2S_2_A -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_neg2S_2_B -module_name IR_neg2S_2_B -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_neg2S_3_A -module_name IR_neg2S_3_A -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_neg2S_3_B -module_name IR_neg2S_3_B -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_neg2S_4_A -module_name IR_neg2S_4_A -vendor xilinx.com -library hls -version 1.0 +create_ip -name InputRouterTop_IR_DTC_neg2S_4_B -module_name IR_neg2S_4_B -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMRouterCMTop_L1PHIA -module_name VMR_L1PHIA -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMRouterCMTop_L1PHIB -module_name VMR_L1PHIB -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMRouterCMTop_L1PHIC -module_name VMR_L1PHIC -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMRouterCMTop_L1PHID -module_name VMR_L1PHID -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMRouterCMTop_L1PHIE -module_name VMR_L1PHIE -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMRouterCMTop_L1PHIF -module_name VMR_L1PHIF -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMRouterCMTop_L1PHIG -module_name VMR_L1PHIG -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMRouterCMTop_L1PHIH -module_name VMR_L1PHIH -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMRouterCMTop_L2PHIA -module_name VMR_L2PHIA -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMRouterCMTop_L2PHIB -module_name VMR_L2PHIB -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMRouterCMTop_L2PHIC -module_name VMR_L2PHIC -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMRouterCMTop_L2PHID -module_name VMR_L2PHID -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMRouterCMTop_L3PHIA -module_name VMR_L3PHIA -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMRouterCMTop_L3PHIB -module_name VMR_L3PHIB -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMRouterCMTop_L3PHIC -module_name VMR_L3PHIC -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMRouterCMTop_L3PHID -module_name VMR_L3PHID -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMRouterCMTop_L4PHIA -module_name VMR_L4PHIA -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMRouterCMTop_L4PHIB -module_name VMR_L4PHIB -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMRouterCMTop_L4PHIC -module_name VMR_L4PHIC -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMRouterCMTop_L4PHID -module_name VMR_L4PHID -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMRouterCMTop_L5PHIA -module_name VMR_L5PHIA -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMRouterCMTop_L5PHIB -module_name VMR_L5PHIB -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMRouterCMTop_L5PHIC -module_name VMR_L5PHIC -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMRouterCMTop_L5PHID -module_name VMR_L5PHID -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMRouterCMTop_L6PHIA -module_name VMR_L6PHIA -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMRouterCMTop_L6PHIB -module_name VMR_L6PHIB -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMRouterCMTop_L6PHIC -module_name VMR_L6PHIC -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMRouterCMTop_L6PHID -module_name VMR_L6PHID -vendor xilinx.com -library hls -version 1.0 +create_ip -name TrackletProcessor_L5L6A -module_name TP_L5L6A -vendor xilinx.com -library hls -version 1.0 +create_ip -name TrackletProcessor_L5L6B -module_name TP_L5L6B -vendor xilinx.com -library hls -version 1.0 +create_ip -name TrackletProcessor_L5L6C -module_name TP_L5L6C -vendor xilinx.com -library hls -version 1.0 +create_ip -name TrackletProcessor_L5L6D -module_name TP_L5L6D -vendor xilinx.com -library hls -version 1.0 + +# Provide name of top-level HDL (without .vhd extension). +#set topLevelHDL "SectorProcessor" +set topLevelHDL "SectorProcessorFull" + +# Add HDL for algo +add_files -fileset sources_1 [glob ../hdl/SectorProcessor.vhd] +add_files -fileset sources_1 [glob ../hdl/SectorProcessorFull.vhd] +add_files -fileset sources_1 [glob ../hdl/memUtil_pkg.vhd] +add_files -fileset sources_1 [glob common/hdl/*.vhd] +remove_files -fileset sources_1 [glob common/hdl/latency_monitor.vhd] +remove_files -fileset sources_1 [glob common/hdl/tf_mem_new.vhd] + + +# Add HDL for TB +add_files -fileset sim_1 [glob ../tb/tb_tf_top.vhd] + +# Add constraints (clock etc.) +add_files -fileset constrs_1 [glob common/hdl/constraints.xdc] + +# Set 'sim_1' fileset properties +set_property file_type {VHDL 2008} [get_files -filter {FILE_TYPE == VHDL}] +set_property top -value ${topLevelHDL} -objects [get_filesets sim_1] +set_property top -value "tb_tf_top" -objects [get_filesets sim_1] +set_property xsim.simulate.runtime -value "0us" -objects [get_filesets sim_1] + +update_compile_order -fileset sources_1 + +puts "INFO: Project created: ${projName}" + +exit + diff --git a/IntegrationTests/ReducedCombinedConfig_FPGA1/script/runSim.tcl b/IntegrationTests/ReducedCombinedConfig_FPGA1/script/runSim.tcl new file mode 100644 index 00000000000..d63c52f28ff --- /dev/null +++ b/IntegrationTests/ReducedCombinedConfig_FPGA1/script/runSim.tcl @@ -0,0 +1,19 @@ +# Open project +set projName "Work" +open_project $projName/$projName.xpr + +reset_simulation sim_1 + +# Create directory for output .txt file +file delete -force dataOut/ +file mkdir dataOut/ + +# Launch Simulation +launch_simulation + +# Set default wave viewer cfg +open_wave_config {../tb/start_bx.wcfg} + +restart +# Need 4us + 0.45us per event (50us for 100 events, but 10us for quick test). +run 50 us diff --git a/IntegrationTests/ReducedCombinedConfig_FPGA1/tb/start_bx.wcfg b/IntegrationTests/ReducedCombinedConfig_FPGA1/tb/start_bx.wcfg new file mode 100644 index 00000000000..2d693edb473 --- /dev/null +++ b/IntegrationTests/ReducedCombinedConfig_FPGA1/tb/start_bx.wcfg @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + clk + clk + + + MP_done + MP_done + + + ap_start + ap_start + + + ap_done + ap_done + + + instubdata_dataarray_0_data_V_address0[10:0] + instubdata_dataarray_0_data_V_address0[10:0] + + + projin_0_dataarray_data_V_address0[9:0] + projin_0_dataarray_data_V_address0[9:0] + + + ap_start + ap_start + + + ap_start + ap_start + + + PC_start + PC_start + + + MP_start + MP_start + + + PC_bx_out[2:0] + PC_bx_out[2:0] + + + bx_V[2:0] + bx_V[2:0] + + diff --git a/IntegrationTests/common/script/CompareMemPrintsFW.py b/IntegrationTests/common/script/CompareMemPrintsFW.py index 5d33dbc157e..06f2fa26adf 100644 --- a/IntegrationTests/common/script/CompareMemPrintsFW.py +++ b/IntegrationTests/common/script/CompareMemPrintsFW.py @@ -53,6 +53,7 @@ class ReferenceType(Enum): AS = 'AllStubs' SP = 'StubPairs' TPAR = 'TrackletParameters' + MPAR = 'TrackletParameters' MPROJ = 'TrackletProjections' TPROJ = 'TrackletProjections' VMPROJ = 'VMProjections' @@ -150,7 +151,7 @@ def compare(comparison_filename="", fail_on_error=False, file_location='./', pre if verbose: print(data) # Can also just do data.head() #Need to figure out how to handle the memory "overwrite" - this is a bit of a hack... - if (not is_binned) and ("TF_" not in comparison_filename): + if (not is_binned) and ("TF_" not in comparison_filename) and ("AS_" not in comparison_filename): rows = [] for index, row in data.iterrows(): if row['ADDR'] == "0x01": @@ -205,6 +206,11 @@ def compare(comparison_filename="", fail_on_error=False, file_location='./', pre # Select the correct event from the comparison data selected_rows = selected_columns.loc[selected_columns['BX'] == ievent] + + # Hack for FPGA1 Project as BX off by 0ne + if "AS_" in comparison_filename and "n1" in comparison_filename: + selected_rows = selected_columns.loc[selected_columns['BX']-1 == ievent] + if len(selected_rows) == 0 and len(event) != 0: good = False number_of_missing_events += 1 @@ -245,7 +251,12 @@ def compare(comparison_filename="", fail_on_error=False, file_location='./', pre data = val # Raise exception if the values for a given entry don't match - if selected_rows['DATA'][offset+ival] != data: + adata = selected_rows['DATA'][offset+ival] + + if ("AS_" in comparison_filename) and ("n1" in comparison_filename): + adata=adata.replace("0x1","0x") + + if adata != data: good = False number_of_value_mismatches += 1 message = "The values for event "+str(ievent)+" address "+str(selected_rows['ADDR'][offset+ival])+" do not match!"\ diff --git a/emData/download.sh b/emData/download.sh index 13423793bff..49050439e20 100755 --- a/emData/download.sh +++ b/emData/download.sh @@ -171,6 +171,14 @@ sed -i 's/VMStubMERouter/VMSMERouter/g' fpga2_processingmodules.dat sed -i 's/VMStubMERouter/VMSMERouter/g' fpga1_processingmodules.dat +echo "Reduced CM FPGA1" +./generator_hdl.py ../../ --no_graph --mut IR -u 0 -d 2 -w fpga1_reducedcm_wires.dat -p fpga1_reducedcm_processingmodules.dat -m fpga1_reducedcm_memorymodules.dat -de 1 -sp 1 +./generator_hdl.py ../../ --no_graph --mut IR -u 0 -d 2 -w fpga1_reducedcm_wires.dat -p fpga1_reducedcm_processingmodules.dat -m fpga1_reducedcm_memorymodules.dat -de 1 -x -sp 1 +ls -ltr *.vhd +mkdir -p ../../IntegrationTests/ReducedCombinedConfig_FPGA1/{hdl,tb} +mv -fv memUtil_pkg.vhd SectorProcessor.vhd SectorProcessorFull.vhd ../../IntegrationTests/ReducedCombinedConfig_FPGA1/hdl/ +mv -fv tb_tf_top.vhd ../../IntegrationTests/ReducedCombinedConfig_FPGA1/tb/ + echo "CM FPGA1" ./generator_hdl.py ../../ --no_graph --mut IR -u 0 -d 2 -w fpga1_wires.dat -p fpga1_processingmodules.dat -m fpga1_memorymodules.dat -de 1 -sp 1 ./generator_hdl.py ../../ --no_graph --mut IR -u 0 -d 2 -w fpga1_wires.dat -p fpga1_processingmodules.dat -m fpga1_memorymodules.dat -de 1 -x -sp 1 diff --git a/emData/project_generation_scripts b/emData/project_generation_scripts index 53fc560b9e7..f1eefe045ef 160000 --- a/emData/project_generation_scripts +++ b/emData/project_generation_scripts @@ -1 +1 @@ -Subproject commit 53fc560b9e736b63b8730e4cb8586e7500c1af58 +Subproject commit f1eefe045efe2517b863b28c7bbb9e16c1d1af86