diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index f0b3fa64e61..a721e7ce78a 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -136,12 +136,12 @@ IR-quality-check: <<: *template_quality-check variables: VIVADO_VERSION: "2019.2" - CLANG_TIDY_FILES: '../TestBenches/InputRouter_test.cpp ../TopFunctions/CombinedConfig/InputRouterTop.cc' + CLANG_TIDY_FILES: '../TestBenches/InputRouter_test.cpp ../TopFunctions/CombinedConfig_FPGA2/InputRouterTop.cc' VMRCM-quality-check: <<: *template_quality-check variables: VIVADO_VERSION: "2019.2" - CLANG_TIDY_FILES: '../TestBenches/VMRouterCM_test.cpp ../TopFunctions/CombinedConfig/VMRouterCMTop_L2PHIA.cc' + CLANG_TIDY_FILES: '../TestBenches/VMRouterCM_test.cpp ../TopFunctions/CombinedConfig_FPGA2/VMRouterCMTop_L2PHIA.cc' VMSMER-quality-check: <<: *template_quality-check variables: @@ -151,7 +151,7 @@ TP-quality-check: <<: *template_quality-check variables: VIVADO_VERSION: "2019.2" - CLANG_TIDY_FILES: '../TestBenches/TrackletProcessor_test.cpp ../TopFunctions/CombinedConfig/TrackletProcessorTop.cc' + CLANG_TIDY_FILES: '../TestBenches/TrackletProcessor_test.cpp ../TopFunctions/CombinedConfig_FPGA2/TrackletProcessorTop.cc' PC-quality-check: <<: *template_quality-check variables: @@ -236,7 +236,7 @@ topReducedCombined-sim: allow_failure: true variables: VIVADO_VERSION: "2019.2" - PROJ_NAME: "ReducedCombinedConfig" + PROJ_NAME: "ReducedCombinedConfig_FPGA2" needs: - job: download - job: IR-vivado-hls-build @@ -259,7 +259,7 @@ topReducedCombined-check-results: allow_failure: true # FIXME: remove after all errors are fixed variables: VIVADO_VERSION: "2019.2" # Vivado not needed but it is part of the path that is called - PROJ_NAME: "ReducedCombinedConfig" + PROJ_NAME: "ReducedCombinedConfig_FPGA2" needs: - download - topReducedCombined-sim @@ -269,7 +269,7 @@ topReducedCombined-synth: allow_failure: true variables: VIVADO_VERSION: "2019.2" - PROJ_NAME: "ReducedCombinedConfig" + PROJ_NAME: "ReducedCombinedConfig_FPGA2" needs: - job: download - job: topReducedCombined-sim diff --git a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/Makefile b/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/Makefile deleted file mode 100644 index 0e43e045754..00000000000 --- a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/Makefile +++ /dev/null @@ -1,53 +0,0 @@ -core_file = scripts/xciMaker -core_dir = cgn -input_file = mem/in.txt -proj_path = ../../../../proj -hls_script_path = ../../script - -all: add_common_files $(core_file) hdl_add_files xciCreation kfin_adj $(input_file) apollo_input - -$(core_dir): - @mkdir cgn mem - make -C $(hls_script_path) -j 8 Work - ln -s ../../../../../emData/LUTsCMBarrel mem/LUTs - ln -s ../../../../../emData/MemPrintsCMBarrel mem/MemPrintsCMBarrel - ln -s ../../../../common hdl/common - -$(core_file): $(core_dir) - @python3 scripts/include_cores.py -s $(hls_script_path) - -kfin_adj: - @cd ../../../../KalmanFilter; git checkout f265d5a - @python3 scripts/kf_link_mod.py - -xciCreation: $(core_file) - make -f $(core_file) -j 8 all - -add_common_files: - @cd cfg; ln -s ../../../../common/cfg/*.dep . - @cd ucf; ln -s ../../../../common/ucf/*.tcl . - @cd scripts; ln -s ../../../../common/script/emp/*.py . - @cd scripts; ln -s ../../../../common/script/emp/*.tcl . - -hdl_add_files: $(core_file) - cd hdl; ln -s ../../../hdl/*.vhd . - -$(input_file): $(core_dir) - @python3 scripts/convert_emData2EMP_Link.py -d mem/MemPrintsCMBarrel/InputStubs -o $(input_file) - -apollo_input: $(input_file) - @python3 scripts/split_emp_input.py - -sim: $(input_file) $(core_file) $(core_dir) - @ln -s $(proj_path)/vsim/vsim/vsim.sim/sim_1/behav/xsim/out.txt mem/out.txt - @$(eval CORE_DIRS= $(wildcard $(core_dir)/*)) - @$(foreach core_dir,$(CORE_DIRS),ln -s ../../../../firmware/$(core_dir) $(hls_script_path);) - @ln -s ../../../common $(hls_script_path) - @ln -s ../../../../emData/MemPrintsCMBarrel $(hls_script_path)/MemPrints - @ln -s ../../../../emData/LUTsCMBarrel $(hls_script_path)/LUTs - @$(eval CORE_DIRS= $(wildcard $(core_dir)/*)) - @cd $(hls_script_path); vivado -mode batch -source makeProject.tcl - @cd $(hls_script_path); vivado -mode batch -source runSim.tcl - @python3 scripts/fwtosim_comparison.py -e mem/out.txt -s $(hls_script_path)/dataOut/TF_L1L2.txt - -.PHONY: sim all hdl_add_files xciCreation kfin_adj apollo_input core_patch diff --git a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/cfg/apollo.dep b/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/cfg/apollo.dep deleted file mode 100644 index 525616eb11a..00000000000 --- a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/cfg/apollo.dep +++ /dev/null @@ -1,13 +0,0 @@ -include payload.dep -src emp_project_decl.vhd -setup ../ucf/ip.tcl -#src ../scripts/pre_synth.tcl -#setup ../ucf/misc_synth.tcl - -src -c emp-fwk:components/datapath emp_data_types.vhd -src -c ipbus-firmware:components/ipbus_slaves ipbus_reg_v.vhd ipbus_ctrlreg_v.vhd ipbus_reg_types.vhd -src -c ipbus-firmware:components/ipbus_core ipbus_fabric_sel.vhd ipbus_package.vhd -src ../constrs/floorplan_emp.xdc - -addrtab -c emp-fwk:components/payload emp_payload.xml -include -c emp-fwk:boards/apollo/cm_v2/vu13p cm_v2.dep diff --git a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/constrs/floorplan_emp.xdc b/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/constrs/floorplan_emp.xdc deleted file mode 100644 index aa2ac05a19a..00000000000 --- a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/constrs/floorplan_emp.xdc +++ /dev/null @@ -1,240 +0,0 @@ -#this XDC contains physical constraints for the out-of-context combined barrel chain -create_pblock pblock_MPL3L4L5L6 -add_cells_to_pblock [get_pblocks pblock_MPL3L4L5L6] [get_cells -quiet [list \ - payload/tf_wrapper_1/SectorProcessor_1/MP_L3PHIA \ - payload/tf_wrapper_1/SectorProcessor_1/MP_L3PHIB \ - payload/tf_wrapper_1/SectorProcessor_1/MP_L3PHIC \ - payload/tf_wrapper_1/SectorProcessor_1/MP_L3PHID \ - payload/tf_wrapper_1/SectorProcessor_1/MP_L4PHIA \ - payload/tf_wrapper_1/SectorProcessor_1/MP_L4PHIB \ - payload/tf_wrapper_1/SectorProcessor_1/MP_L4PHIC \ - payload/tf_wrapper_1/SectorProcessor_1/MP_L4PHID \ - payload/tf_wrapper_1/SectorProcessor_1/MP_L5PHIA \ - payload/tf_wrapper_1/SectorProcessor_1/MP_L5PHIB \ - payload/tf_wrapper_1/SectorProcessor_1/MP_L5PHIC \ - payload/tf_wrapper_1/SectorProcessor_1/MP_L5PHID \ - payload/tf_wrapper_1/SectorProcessor_1/MP_L6PHIA \ - payload/tf_wrapper_1/SectorProcessor_1/MP_L6PHIB \ - payload/tf_wrapper_1/SectorProcessor_1/MP_L6PHID \ - payload/tf_wrapper_1/SectorProcessor_1/MP_L6PHIC]] -resize_pblock [get_pblocks pblock_MPL3L4L5L6] -add {CLOCKREGION_X0Y8:CLOCKREGION_X7Y9} -create_pblock pblock_MPL1L2 -add_cells_to_pblock [get_pblocks pblock_MPL1L2] [get_cells -quiet [list \ - payload/tf_wrapper_1/SectorProcessor_1/MP_L1PHIA \ - payload/tf_wrapper_1/SectorProcessor_1/MP_L1PHIB \ - payload/tf_wrapper_1/SectorProcessor_1/MP_L1PHIC \ - payload/tf_wrapper_1/SectorProcessor_1/MP_L1PHID \ - payload/tf_wrapper_1/SectorProcessor_1/MP_L1PHIE \ - payload/tf_wrapper_1/SectorProcessor_1/MP_L1PHIF \ - payload/tf_wrapper_1/SectorProcessor_1/MP_L1PHIG \ - payload/tf_wrapper_1/SectorProcessor_1/MP_L1PHIH \ - payload/tf_wrapper_1/SectorProcessor_1/MP_L2PHIA \ - payload/tf_wrapper_1/SectorProcessor_1/MP_L2PHIB \ - payload/tf_wrapper_1/SectorProcessor_1/MP_L2PHIC \ - payload/tf_wrapper_1/SectorProcessor_1/MP_L2PHID]] -resize_pblock [get_pblocks pblock_MPL1L2] -add {CLOCKREGION_X0Y4:CLOCKREGION_X7Y5} -create_pblock pblock_TPL1L2 -add_cells_to_pblock [get_pblocks pblock_TPL1L2] [get_cells -quiet [list \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2A \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2A_lut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2A_regionlut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2B \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2B_lut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2B_regionlut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2C \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2C_lut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2C_regionlut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2D \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2D_lut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2D_regionlut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2E \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2E_lut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2E_regionlut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2F \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2F_lut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2F_regionlut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2G \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2G_lut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2G_regionlut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2H \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2H_lut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2H_regionlut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2I \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2I_lut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2I_regionlut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2J \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2J_lut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2J_regionlut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2K \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2K_lut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2K_regionlut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2L \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2L_lut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2L_regionlut]] -resize_pblock [get_pblocks pblock_TPL1L2] -add {CLOCKREGION_X0Y11:CLOCKREGION_X7Y10} - -create_pblock pblock_TPL3L4 -add_cells_to_pblock [get_pblocks pblock_TPL3L4] [get_cells -quiet [list \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L2L3A \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L2L3A_lut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L2L3A_regionlut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L2L3B \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L2L3B_lut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L2L3B_regionlut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L2L3C \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L2L3C_lut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L2L3C_regionlut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L2L3D \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L2L3D_lut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L2L3D_regionlut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L3L4A \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L3L4A_lut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L3L4A_regionlut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L3L4B \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L3L4B_lut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L3L4B_regionlut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L3L4C \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L3L4C_lut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L3L4C_regionlut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L3L4D \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L3L4D_lut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L3L4D_regionlut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L5L6A \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L5L6A_lut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L5L6A_regionlut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L5L6B \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L5L6B_lut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L5L6B_regionlut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L5L6C \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L5L6C_lut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L5L6C_regionlut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L5L6D \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L5L6D_lut \ - payload/tf_wrapper_1/SectorProcessor_1/TP_L5L6D_regionlut]] -resize_pblock [get_pblocks pblock_TPL3L4] -add {CLOCKREGION_X0Y6:CLOCKREGION_X7Y7} - -create_pblock pblock_FTs -add_cells_to_pblock [get_pblocks pblock_FTs] [get_cells -quiet [list \ - {payload/tf_wrapper_1/SectorProcessor_1/FM_52_loop[*].FM_52} \ - {payload/tf_wrapper_1/SectorProcessor_1/FM_52_delay_loop[*].FM_52} \ - payload/tf_wrapper_1/SectorProcessor_1/FT_L1L2 \ - payload/tf_wrapper_1/SectorProcessor_1/FT_L2L3 \ - payload/tf_wrapper_1/SectorProcessor_1/FT_L3L4 \ - payload/tf_wrapper_1/SectorProcessor_1/FT_L5L6 \ - {payload/tf_wrapper_1/SectorProcessor_1/TPAR_70_loop[*].TPAR_70}]] -resize_pblock [get_pblocks pblock_FTs] -add {CLOCKREGION_X1Y0:CLOCKREGION_X6Y3} -create_pblock pblock_IRsVMRs -add_cells_to_pblock [get_pblocks pblock_IRsVMRs] [get_cells -quiet [list \ - {payload/tf_wrapper_1/SectorProcessor_1/IL_36_loop[*].IL_36}\ - payload/tf_wrapper_1/SectorProcessor_1/IR_2S_1_A \ - payload/tf_wrapper_1/SectorProcessor_1/IR_2S_1_B \ - payload/tf_wrapper_1/SectorProcessor_1/IR_2S_2_A \ - payload/tf_wrapper_1/SectorProcessor_1/IR_2S_2_B \ - payload/tf_wrapper_1/SectorProcessor_1/IR_2S_3_A \ - payload/tf_wrapper_1/SectorProcessor_1/IR_2S_3_B \ - payload/tf_wrapper_1/SectorProcessor_1/IR_2S_4_A \ - payload/tf_wrapper_1/SectorProcessor_1/IR_2S_4_B \ - payload/tf_wrapper_1/SectorProcessor_1/IR_PS10G_1_A \ - payload/tf_wrapper_1/SectorProcessor_1/IR_PS10G_1_B \ - payload/tf_wrapper_1/SectorProcessor_1/IR_PS10G_2_A \ - payload/tf_wrapper_1/SectorProcessor_1/IR_PS10G_2_B \ - payload/tf_wrapper_1/SectorProcessor_1/IR_PS10G_3_A \ - payload/tf_wrapper_1/SectorProcessor_1/IR_PS10G_3_B \ - payload/tf_wrapper_1/SectorProcessor_1/IR_PS_1_A \ - payload/tf_wrapper_1/SectorProcessor_1/IR_PS_1_B \ - payload/tf_wrapper_1/SectorProcessor_1/IR_PS_2_A \ - payload/tf_wrapper_1/SectorProcessor_1/IR_PS_2_B \ - payload/tf_wrapper_1/SectorProcessor_1/IR_neg2S_1_A \ - payload/tf_wrapper_1/SectorProcessor_1/IR_neg2S_1_B \ - payload/tf_wrapper_1/SectorProcessor_1/IR_neg2S_2_A \ - payload/tf_wrapper_1/SectorProcessor_1/IR_neg2S_2_B \ - payload/tf_wrapper_1/SectorProcessor_1/IR_neg2S_3_A \ - payload/tf_wrapper_1/SectorProcessor_1/IR_neg2S_3_B \ - payload/tf_wrapper_1/SectorProcessor_1/IR_neg2S_4_A \ - payload/tf_wrapper_1/SectorProcessor_1/IR_neg2S_4_B \ - payload/tf_wrapper_1/SectorProcessor_1/IR_negPS10G_1_A \ - payload/tf_wrapper_1/SectorProcessor_1/IR_negPS10G_1_B \ - payload/tf_wrapper_1/SectorProcessor_1/IR_negPS10G_2_A \ - payload/tf_wrapper_1/SectorProcessor_1/IR_negPS10G_2_B \ - payload/tf_wrapper_1/SectorProcessor_1/IR_negPS10G_3_A \ - payload/tf_wrapper_1/SectorProcessor_1/IR_negPS10G_3_B \ - payload/tf_wrapper_1/SectorProcessor_1/IR_negPS_1_A \ - payload/tf_wrapper_1/SectorProcessor_1/IR_negPS_1_B \ - payload/tf_wrapper_1/SectorProcessor_1/IR_negPS_2_A \ - payload/tf_wrapper_1/SectorProcessor_1/IR_negPS_2_B]] -resize_pblock [get_pblocks pblock_IRsVMRs] -add {CLOCKREGION_X1Y12:CLOCKREGION_X6Y15} - -create_pblock pblock_KF -add_cells_to_pblock [get_pblocks pblock_KF] [get_cells -quiet [list \ - payload/kf_wrapper_1]] -resize_pblock [get_pblocks pblock_KF] -add {CLOCKREGION_X0Y0:CLOCKREGION_X7Y3} - -create_pblock pblock_1 -resize_pblock [get_pblocks pblock_1] -add {CLOCKREGION_X0Y12:CLOCKREGION_X0Y15} -#set_property EXCLUDE_PLACEMENT 1 [get_pblocks pblock_1] -create_pblock pblock_2 -resize_pblock [get_pblocks pblock_2] -add {CLOCKREGION_X7Y12:CLOCKREGION_X7Y15} -#set_property EXCLUDE_PLACEMENT 1 [get_pblocks pblock_2] - -create_pblock pblock_3 -resize_pblock [get_pblocks pblock_3] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y3} -#set_property EXCLUDE_PLACEMENT 1 [get_pblocks pblock_3] -create_pblock pblock_4 -resize_pblock [get_pblocks pblock_4] -add {CLOCKREGION_X7Y0:CLOCKREGION_X7Y3} -#set_property EXCLUDE_PLACEMENT 1 [get_pblocks pblock_4] - -set_property USER_CLUSTER group_TP_L1L2A [get_cells [list payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2A payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2A_lut payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2A_regionlut]] -set_property USER_CLUSTER group_TP_L1L2B [get_cells [list payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2B payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2B_lut payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2B_regionlut]] -set_property USER_CLUSTER group_TP_L1L2C [get_cells [list payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2C payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2C_lut payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2C_regionlut]] -set_property USER_CLUSTER group_TP_L1L2D [get_cells [list payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2D payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2D_lut payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2D_regionlut]] -set_property USER_CLUSTER group_TP_L1L2E [get_cells [list payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2E payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2E_lut payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2E_regionlut]] -set_property USER_CLUSTER group_TP_L1L2F [get_cells [list payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2F payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2F_lut payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2F_regionlut]] -set_property USER_CLUSTER group_TP_L1L2G [get_cells [list payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2G payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2G_lut payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2G_regionlut]] -set_property USER_CLUSTER group_TP_L1L2H [get_cells [list payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2H payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2H_lut payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2H_regionlut]] -set_property USER_CLUSTER group_TP_L1L2I [get_cells [list payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2I payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2I_lut payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2I_regionlut]] -set_property USER_CLUSTER group_TP_L1L2J [get_cells [list payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2J payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2J_lut payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2J_regionlut]] -set_property USER_CLUSTER group_TP_L1L2K [get_cells [list payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2K payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2K_lut payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2K_regionlut]] -set_property USER_CLUSTER group_TP_L1L2L [get_cells [list payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2L payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2L_lut payload/tf_wrapper_1/SectorProcessor_1/TP_L1L2L_regionlut]] -set_property USER_CLUSTER group_TP_L2L3A [get_cells [list payload/tf_wrapper_1/SectorProcessor_1/TP_L2L3A payload/tf_wrapper_1/SectorProcessor_1/TP_L2L3A_lut payload/tf_wrapper_1/SectorProcessor_1/TP_L2L3A_regionlut]] -set_property USER_CLUSTER group_TP_L2L3B [get_cells [list payload/tf_wrapper_1/SectorProcessor_1/TP_L2L3B payload/tf_wrapper_1/SectorProcessor_1/TP_L2L3B_lut payload/tf_wrapper_1/SectorProcessor_1/TP_L2L3B_regionlut]] -set_property USER_CLUSTER group_TP_L2L3C [get_cells [list payload/tf_wrapper_1/SectorProcessor_1/TP_L2L3C payload/tf_wrapper_1/SectorProcessor_1/TP_L2L3C_lut payload/tf_wrapper_1/SectorProcessor_1/TP_L2L3C_regionlut]] -set_property USER_CLUSTER group_TP_L2L3D [get_cells [list payload/tf_wrapper_1/SectorProcessor_1/TP_L2L3D payload/tf_wrapper_1/SectorProcessor_1/TP_L2L3D_lut payload/tf_wrapper_1/SectorProcessor_1/TP_L2L3D_regionlut]] -set_property USER_CLUSTER group_TP_L3L4A [get_cells [list payload/tf_wrapper_1/SectorProcessor_1/TP_L3L4A payload/tf_wrapper_1/SectorProcessor_1/TP_L3L4A_lut payload/tf_wrapper_1/SectorProcessor_1/TP_L3L4A_regionlut]] -set_property USER_CLUSTER group_TP_L3L4B [get_cells [list payload/tf_wrapper_1/SectorProcessor_1/TP_L3L4B payload/tf_wrapper_1/SectorProcessor_1/TP_L3L4B_lut payload/tf_wrapper_1/SectorProcessor_1/TP_L3L4B_regionlut]] -set_property USER_CLUSTER group_TP_L3L4C [get_cells [list payload/tf_wrapper_1/SectorProcessor_1/TP_L3L4C payload/tf_wrapper_1/SectorProcessor_1/TP_L3L4C_lut payload/tf_wrapper_1/SectorProcessor_1/TP_L3L4C_regionlut]] -set_property USER_CLUSTER group_TP_L3L4D [get_cells [list payload/tf_wrapper_1/SectorProcessor_1/TP_L3L4D payload/tf_wrapper_1/SectorProcessor_1/TP_L3L4D_lut payload/tf_wrapper_1/SectorProcessor_1/TP_L3L4D_regionlut]] -set_property USER_CLUSTER group_TP_L5L6A [get_cells [list payload/tf_wrapper_1/SectorProcessor_1/TP_L5L6A payload/tf_wrapper_1/SectorProcessor_1/TP_L5L6A_lut payload/tf_wrapper_1/SectorProcessor_1/TP_L5L6A_regionlut]] -set_property USER_CLUSTER group_TP_L5L6B [get_cells [list payload/tf_wrapper_1/SectorProcessor_1/TP_L5L6B payload/tf_wrapper_1/SectorProcessor_1/TP_L5L6B_lut payload/tf_wrapper_1/SectorProcessor_1/TP_L5L6B_regionlut]] -set_property USER_CLUSTER group_TP_L5L6C [get_cells [list payload/tf_wrapper_1/SectorProcessor_1/TP_L5L6C payload/tf_wrapper_1/SectorProcessor_1/TP_L5L6C_lut payload/tf_wrapper_1/SectorProcessor_1/TP_L5L6C_regionlut]] -set_property USER_CLUSTER group_TP_L5L6D [get_cells [list payload/tf_wrapper_1/SectorProcessor_1/TP_L5L6D payload/tf_wrapper_1/SectorProcessor_1/TP_L5L6D_lut payload/tf_wrapper_1/SectorProcessor_1/TP_L5L6D_regionlut]] -set_property USER_CLUSTER group_MP_L1PHIA [get_cells payload/tf_wrapper_1/SectorProcessor_1/MP_L1PHIA] -set_property USER_CLUSTER group_MP_L1PHIB [get_cells payload/tf_wrapper_1/SectorProcessor_1/MP_L1PHIB] -set_property USER_CLUSTER group_MP_L1PHIC [get_cells payload/tf_wrapper_1/SectorProcessor_1/MP_L1PHIC] -set_property USER_CLUSTER group_MP_L1PHID [get_cells payload/tf_wrapper_1/SectorProcessor_1/MP_L1PHID] -set_property USER_CLUSTER group_MP_L1PHIE [get_cells payload/tf_wrapper_1/SectorProcessor_1/MP_L1PHIE] -set_property USER_CLUSTER group_MP_L1PHIF [get_cells payload/tf_wrapper_1/SectorProcessor_1/MP_L1PHIF] -set_property USER_CLUSTER group_MP_L1PHIG [get_cells payload/tf_wrapper_1/SectorProcessor_1/MP_L1PHIG] -set_property USER_CLUSTER group_MP_L1PHIH [get_cells payload/tf_wrapper_1/SectorProcessor_1/MP_L1PHIH] -set_property USER_CLUSTER group_MP_L2PHIA [get_cells payload/tf_wrapper_1/SectorProcessor_1/MP_L2PHIA] -set_property USER_CLUSTER group_MP_L2PHIB [get_cells payload/tf_wrapper_1/SectorProcessor_1/MP_L2PHIB] -set_property USER_CLUSTER group_MP_L2PHIC [get_cells payload/tf_wrapper_1/SectorProcessor_1/MP_L2PHIC] -set_property USER_CLUSTER group_MP_L2PHID [get_cells payload/tf_wrapper_1/SectorProcessor_1/MP_L2PHID] -set_property USER_CLUSTER group_MP_L3PHIA [get_cells payload/tf_wrapper_1/SectorProcessor_1/MP_L3PHIA] -set_property USER_CLUSTER group_MP_L3PHIB [get_cells payload/tf_wrapper_1/SectorProcessor_1/MP_L3PHIB] -set_property USER_CLUSTER group_MP_L3PHIC [get_cells payload/tf_wrapper_1/SectorProcessor_1/MP_L3PHIC] -set_property USER_CLUSTER group_MP_L3PHID [get_cells payload/tf_wrapper_1/SectorProcessor_1/MP_L3PHID] -set_property USER_CLUSTER group_MP_L4PHIA [get_cells payload/tf_wrapper_1/SectorProcessor_1/MP_L4PHIA] -set_property USER_CLUSTER group_MP_L4PHIB [get_cells payload/tf_wrapper_1/SectorProcessor_1/MP_L4PHIB] -set_property USER_CLUSTER group_MP_L4PHIC [get_cells payload/tf_wrapper_1/SectorProcessor_1/MP_L4PHIC] -set_property USER_CLUSTER group_MP_L4PHID [get_cells payload/tf_wrapper_1/SectorProcessor_1/MP_L4PHID] -set_property USER_CLUSTER group_MP_L5PHIA [get_cells payload/tf_wrapper_1/SectorProcessor_1/MP_L5PHIA] -set_property USER_CLUSTER group_MP_L5PHIB [get_cells payload/tf_wrapper_1/SectorProcessor_1/MP_L5PHIB] -set_property USER_CLUSTER group_MP_L5PHIC [get_cells payload/tf_wrapper_1/SectorProcessor_1/MP_L5PHIC] -set_property USER_CLUSTER group_MP_L5PHID [get_cells payload/tf_wrapper_1/SectorProcessor_1/MP_L5PHID] -set_property USER_CLUSTER group_MP_L6PHIA [get_cells payload/tf_wrapper_1/SectorProcessor_1/MP_L6PHIA] -set_property USER_CLUSTER group_MP_L6PHIB [get_cells payload/tf_wrapper_1/SectorProcessor_1/MP_L6PHIB] -set_property USER_CLUSTER group_MP_L6PHIC [get_cells payload/tf_wrapper_1/SectorProcessor_1/MP_L6PHIC] -set_property USER_CLUSTER group_MP_L6PHID [get_cells payload/tf_wrapper_1/SectorProcessor_1/MP_L6PHID] - - - diff --git a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/hdl/emp_cdc.vhd b/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/hdl/emp_cdc.vhd deleted file mode 100644 index b2635aee0f2..00000000000 --- a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/hdl/emp_cdc.vhd +++ /dev/null @@ -1,185 +0,0 @@ -------------------------------------------------------------------------------- --- Title : CDC firmware for slowed down track finding --- Project : -------------------------------------------------------------------------------- --- File : emp_cdc.vhd --- Author : Michael Oshiro --- Company : Cornell University --- Created : 2023-10-27 --- Last update: --- Platform : --- Standard : VHDL'93/02 -------------------------------------------------------------------------------- --- Description: Crosses clock domain to/from EMP datapath and TF firmware --- Notes : Currently, hard-coded for EMP links used in barrel FW test -------------------------------------------------------------------------------- --- Copyright (c) 2023 Cornell University -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2023-10-27 1.0 mcoshiro Created -------------------------------------------------------------------------------- -library ieee; -library UNISIM; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use work.emp_data_types.all; -use work.emp_device_decl.all; -use work.emp_ttc_decl.all; -use work.tf_pkg.all; -use work.memUtil_pkg.all; -use UNISIM.vcomponents.all; - -entity emp_cdc is - generic ( - channel_first : integer range 0 to (4*N_REGION-1) := 68; - channel_last : integer range 0 to (4*N_REGION-1) := 107 - ); - port ( - clk_i : in std_logic; - clk_o : in std_logic; - rst_i : in std_logic; - din_i : in ldata(4 * N_REGION - 1 downto 0); - din_o : out ldata(4 * N_REGION - 1 downto 0); - rst_o : out std_logic - ); -end entity emp_cdc; - -architecture rtl of emp_cdc is - - type arr_fifodout is array(channel_last downto channel_first) of std_logic_vector(63 downto 0); - type arr_fifodoutp is array(channel_last downto channel_first) of std_logic_vector(7 downto 0); - signal fifodout : arr_fifodout; - signal fifodoutp : arr_fifodoutp; - signal startread_toggle : std_logic := '0'; - signal startread_d : std_logic := '0'; - signal startread_dd : std_logic := '0'; - signal startread_ddd : std_logic := '0'; - signal startread : std_logic := '0'; - signal fiforead : std_logic := '0'; - signal rst_q : std_logic := '0'; - signal d_out : ldata(4 * N_REGION - 1 downto 0) := (others => LWORD_NULL); - -begin -- architecture rtl - - --reset CDC - cdc_reset : process (clk_o) is - begin - if rising_edge(clk_o) then - rst_q <= rst_i; - rst_o <= rst_q; - end if; - end process cdc_reset; - - --toggle synchronizer - cdc_startread_a : process (clk_i) is - begin - if rising_edge(clk_i) then - startread_toggle <= startread_toggle xor din_i(channel_first).last; - end if; - end process cdc_startread_a; - cdc_startread_b : process (clk_o) is - begin - if rising_edge(clk_o) then - startread_d <= startread_toggle; - startread_dd <= startread_d; - startread_ddd <= startread_dd; - startread <= startread_d xor startread_dd; - end if; - end process cdc_startread_b; - - --fifo read logic - p_fiforead : process (clk_o) is - begin - if rising_edge(clk_o) then - if startread = '1' then - fiforead <= '1'; - elsif fifodoutp(channel_first)(4) = '1' then - fiforead <= '0'; - else - fiforead <= fiforead; --latch - end if; - end if; - end process p_fiforead; - - GEN_FIFOS: for i in channel_first to channel_last generate - - --output logic - p_output: process (clk_o) is - begin -- process p_delay_data - if rising_edge(clk_o) then -- rising clock edge - if fiforead = '1' then - d_out(i).data <= fifodout(i); - d_out(i).valid <= fifodoutp(i)(0); - d_out(i).start <= fifodoutp(i)(1); - d_out(i).start_of_orbit <= fifodoutp(i)(2); - d_out(i).strobe <= fifodoutp(i)(3); - d_out(i).last <= fifodoutp(i)(4); - else - d_out(i).data <= x"0000000000000000"; - d_out(i).valid <= '0'; - d_out(i).start <= '0'; - d_out(i).start_of_orbit <= '0'; - d_out(i).strobe <= '0'; - d_out(i).last <= '0'; - end if; - end if; - end process p_output; - din_o(i) <= d_out(i); - - --FIFO - FIFO36_inst : FIFO36E2 - generic map ( - CLOCK_DOMAINS => "INDEPENDENT", - FIRST_WORD_FALL_THROUGH => "TRUE", - PROG_EMPTY_THRESH => 2, - PROG_FULL_THRESH => 64, - READ_WIDTH => 72, - REGISTER_MODE => "REGISTERED", - RSTREG_PRIORITY => "RSTREG", - WRITE_WIDTH => 72 - ) - port map ( - CASDOUT => open, - CASDOUTP => open, - CASNXTEMPTY => open, - CASPRVRDEN => open, - DOUT => fifodout(i), - DOUTP => fifodoutp(i), - EMPTY => open, - FULL => open, - PROGEMPTY => open, - PROGFULL => open, - RDCOUNT => open, - RDERR => open, - RDRSTBUSY => open, - WRCOUNT => open, - WRERR => open, - WRRSTBUSY => open, - CASDIN => X"0000000000000000", - CASDINP => X"00", - CASDOMUX => '0', - CASDOMUXEN => '1', - CASNXTRDEN => '0', - CASOREGIMUX => '0', - CASOREGIMUXEN => '1', - CASPRVEMPTY => '0', - RDCLK => clk_o, - RDEN => fiforead, - REGCE => '1', - RSTREG => '0', - SLEEP => '0', - RST => rst_i, - WRCLK => clk_i, - WREN => din_i(i).valid, - DIN => din_i(i).data, - DINP => "000" & din_i(i).last & din_i(i).strobe & din_i(i).start_of_orbit & din_i(i).start & din_i(i).valid, - INJECTDBITERR => '0', - INJECTSBITERR => '0', - DBITERR => open, - SBITERR => open, - ECCPARITY => open - ); - end generate GEN_FIFOS; - -end architecture rtl; diff --git a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/hdl/emp_project_decl.vhd b/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/hdl/emp_project_decl.vhd deleted file mode 100644 index f8daf389a2e..00000000000 --- a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/hdl/emp_project_decl.vhd +++ /dev/null @@ -1,68 +0,0 @@ - -library IEEE; -use IEEE.STD_LOGIC_1164.all; - -use work.emp_framework_decl.all; -use work.emp_device_types.all; -use work.emp_slink_types.all; - -package emp_project_decl is - - constant PAYLOAD_REV : std_logic_vector(31 downto 0) := X"12345678"; - - -- Latency buffer size - constant LB_ADDR_WIDTH : integer := 10; - - -- Clock setup - constant CLOCK_COMMON_RATIO : integer := 36; - constant CLOCK_RATIO : integer := 6; - constant CLOCK_AUX_DIV : clock_divisor_array_t := (18, 9, 4); -- Dividers of CLOCK_COMMON_RATIO * 40 MHz - - -- Only used by nullalgo - constant PAYLOAD_LATENCY : integer := 830; - - constant REGION_CONF : region_conf_array_t := ( - 0 => kDummyRegion, --service/c2c - 1 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), - 2 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), - 3 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), - 4 => kDummyRegion, --not routed - 5 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), - 6 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), - 7 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), - 8 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), - 9 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), - 10 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), - 11 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), - 12 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), - 13 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), - 14 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), - 15 => kDummyRegion, --not routed - ------cross - 16 => kDummyRegion, --not routed - 17 => (gty25, buf, no_fmt, no_buf, no_mgt), - 18 => (gty25, buf, no_fmt, no_buf, no_mgt), - 19 => (gty25, buf, no_fmt, no_buf, no_mgt), - 20 => kDummyRegion, --not routed - 21 => (gty25, buf, no_fmt, no_buf, no_mgt), - 22 => (gty25, buf, no_fmt, no_buf, no_mgt), - 23 => (gty25, buf, no_fmt, no_buf, no_mgt), - 24 => (gty25, buf, no_fmt, no_buf, no_mgt), - 25 => (gty25, buf, no_fmt, no_buf, no_mgt), - 26 => (gty25, buf, no_fmt, no_buf, no_mgt), - 27 => (no_mgt, no_buf, no_fmt, buf, gty25), - 28 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), - 29 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), - 30 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), - 31 => kDummyRegion, --service/tcds - others => kDummyRegion - ); - - -- Specify the slink quad using the corresponding region conf ID - -- Specify slink channels to enable using the channel mask - constant SLINK_CONF : slink_conf_array_t := ( - others => kNoSlink - ); - - -end emp_project_decl; diff --git a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/hdl/kf_wrapper.vhd b/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/hdl/kf_wrapper.vhd deleted file mode 100644 index 402586220e9..00000000000 --- a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/hdl/kf_wrapper.vhd +++ /dev/null @@ -1,64 +0,0 @@ -------------------------------------------------------------------------------- --- Title : kf wrapper --- Project : -------------------------------------------------------------------------------- --- File : kf_top.vhd --- Author : Filippo Marini --- Company : University of Colorado Boulder --- Created : 2022-11-04 --- Last update: 2023-02-24 --- Platform : --- Standard : VHDL'93/02 -------------------------------------------------------------------------------- --- Description: -------------------------------------------------------------------------------- --- Copyright (c) 2022 University of Colorado Boulder -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2022-11-04 1.0 fmarini Created -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; - -use work.hybrid_data_formats.all; -use work.hybrid_config.all; -use work.hybrid_data_types.all; - -entity kf_wrapper is - port ( - clk_i : in std_logic; - kfin_i : in t_channlesTB(numSeedTypes - 1 downto 0); - kfout_o : out t_frames(numLinksTFP - 1 downto 0) - ); -end entity kf_wrapper; - -architecture rtl of kf_wrapper is - - signal s_kfin_dout : t_channelsZHT(numSeedTypes - 1 downto 0); - signal s_kf_dout : t_channelsKF(numNodesKF - 1 downto 0); - -begin -- architecture rtl - - kfin_top_1 : entity work.kfin_top - port map ( - clk => clk_i, - kfin_din => kfin_i, - kfin_dout => s_kfin_dout - ); - - kf_top_1 : entity work.kf_top - port map ( - clk => clk_i, - kf_din => s_kfin_dout, - kf_dout => s_kf_dout - ); - - kfout_top_1 : entity work.kfout_top - port map ( - clk => clk_i, - kfout_din => s_kf_dout, - kfout_dout => kfout_o - ); - -end architecture rtl; diff --git a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/hdl/linktosecproc.vhd b/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/hdl/linktosecproc.vhd deleted file mode 100644 index d3af9bbfe56..00000000000 --- a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/hdl/linktosecproc.vhd +++ /dev/null @@ -1,174 +0,0 @@ -------------------------------------------------------------------------------- --- Title : link to sector processor --- Project : -------------------------------------------------------------------------------- --- File : linktosecproc.vhd --- Author : Filippo Marini --- Company : University of Colorado Boulder --- Created : 2022-06-27 --- Last update: 2023-04-06 --- Platform : --- Standard : VHDL'93/02 -------------------------------------------------------------------------------- --- Description: -------------------------------------------------------------------------------- --- Copyright (c) 2022 University of Colorado Boulder -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2022-06-27 1.0 fmarini Created -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use work.emp_data_types.all; -use work.emp_device_decl.all; -use work.emp_ttc_decl.all; --- emp thomas --- use work.hybrid_tools.all; --- use work.hybrid_config.all; --- use work.hybrid_data_types.all; --- use work.tracklet_config.all; --- use work.tracklet_data_types.all; --- emp US -use work.tf_pkg.all; -use work.memUtil_pkg.all; -use work.memUtil_aux_pkg.all; - -entity linktosecproc is - port ( - clk_i : in std_logic; - rst_i : in std_logic; - ttc_i : in ttc_stuff_array(N_REGION - 1 downto 0); - din_i : in ldata(4 * N_REGION - 1 downto 0); - ir_start_o : out std_logic; - bx_o : out std_logic_vector(2 downto 0); - DL_39_link_AV_dout : out t_arr_DL_39_DATA; - DL_39_link_empty_neg : out t_arr_DL_39_1b; - DL_39_link_read : in t_arr_DL_39_1b - ); -end entity linktosecproc; - -architecture rtl of linktosecproc is - - -- signal s_tracklet_reset : t_resets(numPPquads - 1 downto 0); - -- signal s_tracklet_isol : t_stubsDTC; - -- signal s_tracklet_data : t_datas(numInputsIR - 1 downto 0); - signal s_ir_start : std_logic; - signal s_ir_start_srff : std_logic; - signal s_din_d : ldata(4 * N_REGION - 1 downto 0); - signal s_din_dd : ldata(4 * N_REGION - 1 downto 0); - -begin -- architecture rtl - - -- tracklet_isolation_in_1 : entity work.tracklet_isolation_in - -- port map ( - -- clk => clk_i, - -- in_ttc => ttc_i, - -- in_din => din_i, - -- in_reset => s_tracklet_reset, - -- in_dout => s_tracklet_isol - -- ); - - -- tracklet_format_in_1 : entity work.tracklet_format_in - -- port map ( - -- clk => clk_i, - -- in_reset => s_tracklet_reset, - -- in_din => s_tracklet_isol, - -- in_dout => s_tracklet_data - -- ); - - GEN_DELAYED_DATA: for i in 68 to 107 generate - p_delay_data: process (clk_i) is - begin -- process p_delay_data - if rising_edge(clk_i) then -- rising clock edge - s_din_d(i).data <= din_i(i).data; - s_din_dd(i).data <= s_din_d(i).data; - s_din_d(i).valid <= din_i(i).valid; - end if; - end process p_delay_data; - end generate GEN_DELAYED_DATA; - - ----------------------------------------------------------------------------- - -- Connect input link data to IR in Sector Processor - ----------------------------------------------------------------------------- - --DL_39_link_AV_DOUT(PS10G_1_A) <= s_din_d(0).data(38 downto 0); - --DL_39_link_AV_DOUT(PS10G_2_A) <= s_din_d(1).data(38 downto 0); - --DL_39_link_AV_DOUT(PS10G_3_A) <= s_din_d(2).data(38 downto 0); - --DL_39_link_AV_DOUT(PS_1_A) <= s_din_d(3).data(38 downto 0); - --DL_39_link_AV_DOUT(PS_2_A) <= s_din_d(4).data(38 downto 0); - --DL_39_link_AV_DOUT(twoS_1_A) <= s_din_d(5).data(38 downto 0); - --DL_39_link_AV_DOUT(twoS_2_A) <= s_din_d(6).data(38 downto 0); - --DL_39_link_AV_DOUT(twoS_3_A) <= s_din_d(7).data(38 downto 0); - --DL_39_link_AV_DOUT(twoS_4_A) <= s_din_d(8).data(38 downto 0); - - DL_39_link_AV_DOUT(PS10G_1_A) <= s_din_dd(68).data(38 downto 0); - DL_39_link_AV_DOUT(PS10G_1_B) <= s_din_dd(69).data(38 downto 0); - DL_39_link_AV_DOUT(PS10G_2_A) <= s_din_dd(70).data(38 downto 0); - DL_39_link_AV_DOUT(PS10G_2_B) <= s_din_dd(71).data(38 downto 0); - DL_39_link_AV_DOUT(PS10G_3_A) <= s_din_dd(72).data(38 downto 0); - DL_39_link_AV_DOUT(PS10G_3_B) <= s_din_dd(73).data(38 downto 0); - DL_39_link_AV_DOUT(PS_1_A) <= s_din_dd(74).data(38 downto 0); - DL_39_link_AV_DOUT(PS_1_B) <= s_din_dd(75).data(38 downto 0); - DL_39_link_AV_DOUT(PS_2_A) <= s_din_dd(76).data(38 downto 0); - DL_39_link_AV_DOUT(PS_2_B) <= s_din_dd(77).data(38 downto 0); - DL_39_link_AV_DOUT(negPS10G_1_A) <= s_din_dd(78).data(38 downto 0); - DL_39_link_AV_DOUT(negPS10G_1_B) <= s_din_dd(79).data(38 downto 0); - DL_39_link_AV_DOUT(negPS10G_2_A) <= s_din_dd(84).data(38 downto 0); - DL_39_link_AV_DOUT(negPS10G_2_B) <= s_din_dd(85).data(38 downto 0); - DL_39_link_AV_DOUT(negPS10G_3_A) <= s_din_dd(86).data(38 downto 0); - DL_39_link_AV_DOUT(negPS10G_3_B) <= s_din_dd(87).data(38 downto 0); - DL_39_link_AV_DOUT(negPS_1_A) <= s_din_dd(88).data(38 downto 0); - DL_39_link_AV_DOUT(negPS_1_B) <= s_din_dd(89).data(38 downto 0); - DL_39_link_AV_DOUT(negPS_2_A) <= s_din_dd(90).data(38 downto 0); - DL_39_link_AV_DOUT(negPS_2_B) <= s_din_dd(91).data(38 downto 0); - DL_39_link_AV_DOUT(twoS_1_A) <= s_din_dd(92).data(38 downto 0); - DL_39_link_AV_DOUT(twoS_1_B) <= s_din_dd(93).data(38 downto 0); - DL_39_link_AV_DOUT(twoS_2_A) <= s_din_dd(94).data(38 downto 0); - DL_39_link_AV_DOUT(twoS_2_B) <= s_din_dd(95).data(38 downto 0); - DL_39_link_AV_DOUT(twoS_3_A) <= s_din_dd(96).data(38 downto 0); - DL_39_link_AV_DOUT(twoS_3_B) <= s_din_dd(97).data(38 downto 0); - DL_39_link_AV_DOUT(twoS_4_A) <= s_din_dd(98).data(38 downto 0); - DL_39_link_AV_DOUT(twoS_4_B) <= s_din_dd(99).data(38 downto 0); - DL_39_link_AV_DOUT(neg2S_1_A) <= s_din_dd(100).data(38 downto 0); - DL_39_link_AV_DOUT(neg2S_1_B) <= s_din_dd(101).data(38 downto 0); - DL_39_link_AV_DOUT(neg2S_2_A) <= s_din_dd(102).data(38 downto 0); - DL_39_link_AV_DOUT(neg2S_2_B) <= s_din_dd(103).data(38 downto 0); - DL_39_link_AV_DOUT(neg2S_3_A) <= s_din_dd(104).data(38 downto 0); - DL_39_link_AV_DOUT(neg2S_3_B) <= s_din_dd(105).data(38 downto 0); - DL_39_link_AV_DOUT(neg2S_4_A) <= s_din_dd(106).data(38 downto 0); - DL_39_link_AV_DOUT(neg2S_4_B) <= s_din_dd(107).data(38 downto 0); - - ----------------------------------------------------------------------------- - -- Generate start signal - ----------------------------------------------------------------------------- - set_reset_ffd_1 : entity work.set_reset_ffd - port map ( - clk_i => clk_i, - set_i => s_din_d(68).valid, - reset_i => rst_i, - q_o => s_ir_start_srff - ); - - - s_ir_start <= s_din_d(68).valid or s_ir_start_srff; - ir_start_o <= s_ir_start; - - p_bx_count : process (clk_i) is - variable v_bx : natural; - variable v_word_count : natural := 1; - begin -- process p_bx_count - if rising_edge(clk_i) then -- rising clock edge - if s_ir_start = '1' then - if v_word_count < MAX_ENTRIES then - v_word_count := v_word_count + 1; - else - v_word_count := 1; - v_bx := v_bx + 1; - end if; - end if; - bx_o <= std_logic_vector(to_unsigned(v_bx, bx_o'length)); - end if; - end process p_bx_count; - -end architecture rtl; diff --git a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/hdl/payload.vhd b/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/hdl/payload.vhd deleted file mode 100644 index d92135f9505..00000000000 --- a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/hdl/payload.vhd +++ /dev/null @@ -1,179 +0,0 @@ -------------------------------------------------------------------------------- --- Title : payload --- Project : -------------------------------------------------------------------------------- --- File : payload.vhd --- Author : Filippo Marini --- Company : University of Colorado Boulder --- Created : 2022-06-21 --- Last update: 2023-06-02 --- Platform : --- Standard : VHDL'93/02 -------------------------------------------------------------------------------- --- Description: -------------------------------------------------------------------------------- --- Copyright (c) 2022 University of Colorado Boulder -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2022-06-21 1.0 fmarini Created -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use work.ipbus.all; -use work.emp_data_types.all; -use work.emp_device_decl.all; -use work.emp_ttc_decl.all; -use work.emp_slink_types.all; --- tf -use work.tf_pkg.all; -use work.memUtil_pkg.all; -use work.memUtil_aux_pkg.all; -use work.tf_interface_pkg.all; -use work.hybrid_data_types.all; -use work.hybrid_config.all; -use work.hybrid_data_formats.all; - -entity emp_payload is - port ( - clk : in std_logic; --unused - rst : in std_logic; - ipb_in : in ipb_wbus; --unused - clk40 : in std_logic; --unused - clk_payload : in std_logic_vector(2 downto 0); - rst_payload : in std_logic_vector(2 downto 0); --unused - clk_p : in std_logic; - rst_loc : in std_logic_vector(N_REGION - 1 downto 0); --unused - clken_loc : in std_logic_vector(N_REGION - 1 downto 0); --unused - ctrs : in ttc_stuff_array(N_REGION - 1 downto 0); --in linktosecproc, but unused - d : in ldata(4 * N_REGION - 1 downto 0); - ipb_out : out ipb_rbus; --unused - bc0 : out std_logic; --unused - q : out ldata(4 * N_REGION - 1 downto 0); - gpio : out std_logic_vector(29 downto 0); --unused - gpio_en : out std_logic_vector(29 downto 0); --unused - slink_q : out slink_input_data_quad_array(SLINK_MAX_QUADS - 1 downto 0); --unused - backpressure : in std_logic_vector(SLINK_MAX_QUADS - 1 downto 0) --unused - ); -end; - -architecture rtl of emp_payload is - - signal s_IR_data : t_arr_DL_39_DATA; - signal s_ir_start : std_logic; - signal s_bx : std_logic_vector(2 downto 0); - signal s_TW_104_stream_data : t_arr_TW_104_DATA; - signal s_TW_104_stream_valid : t_arr_TW_104_1b; - signal s_BW_46_stream_data : t_arr_BW_46_DATA; - signal s_BW_46_stream_valid : t_arr_BW_46_1b; - signal s_FT_bx_out_vld : std_logic; - signal s_tftokf : t_channlesTB(numTW_104 - 1 downto 0); - signal s_kfout : t_frames(numLinksTFP - 1 downto 0); - signal s_tfout : ldata(numLinksTFP - 1 downto 0); - -begin -- architecture rtl - - ----------------------------------------------------------------------------- - -- EMP ports - ----------------------------------------------------------------------------- - slink_q <= (others => SLINK_INPUT_DATA_ARRAY_NULL); - gpio <= (others => '0'); - gpio_en <= (others => '0'); - ipb_out <= IPB_RBUS_NULL; - bc0 <= '0'; - - ----------------------------------------------------------------------------- - -- Link to Sector Processor formatter - ----------------------------------------------------------------------------- - linktosecproc_1 : entity work.linktosecproc - port map ( - clk_i => clk_p, - rst_i => rst, - ttc_i => ctrs, - din_i => d, - ir_start_o => s_ir_start, - bx_o => s_bx, - DL_39_link_AV_dout => s_IR_data, - DL_39_link_empty_neg => open, - DL_39_link_read => (others => '0') - ); - - ----------------------------------------------------------------------------- - -- Sector Processor - ----------------------------------------------------------------------------- - tf_wrapper_1 : entity work.tf_wrapper - port map ( - clk => clk_p, - reset => rst, - IR_start => s_ir_start, - IR_bx_in => s_bx, - FT_bx_out => open, - FT_bx_out_vld => s_FT_bx_out_vld, - FT_done => open, - DL_39_link_AV_dout => s_IR_data, - DL_39_link_empty_neg => (others => '1'), - DL_39_link_read => open, - TW_104_stream_AV_din => s_TW_104_stream_data, - TW_104_stream_A_full_neg => (others => '1'), - TW_104_stream_A_write => s_TW_104_stream_valid, - BW_46_stream_AV_din => s_BW_46_stream_data, - BW_46_stream_A_full_neg => (others => '1'), - BW_46_stream_A_write => s_BW_46_stream_valid - ); - - ----------------------------------------------------------------------------- - -- Sector Processor to Link formatter - ----------------------------------------------------------------------------- - -- secproctolink_1 : entity work.secproctolink - -- port map ( - -- clk_i => clk_p, - -- TW_104_stream_data_i => s_TW_104_stream_data, - -- TW_104_stream_write_i => s_TW_104_stream_valid, - -- TW_104_stream_full_neg_o => open, - -- BW_46_stream_data_i => s_BW_46_stream_data, - -- BW_46_stream_write_i => s_BW_46_stream_valid, - -- BW_46_stream_full_neg_i => open, - -- dout_o => q - -- ); - - ----------------------------------------------------------------------------- - -- Sector Processor to KF formatter - ----------------------------------------------------------------------------- - tf_to_kf_1 : entity work.tf_to_kf - port map ( - clk_i => clk_p, - TW_104_data_i => s_TW_104_stream_data, - TW_104_valid_i => s_TW_104_stream_valid, - BW_46_data_i => s_BW_46_stream_data, - BW_46_valid_i => s_BW_46_stream_valid, - kf_reset_i => s_FT_bx_out_vld, - tftokf_o => s_tftokf - ); - - ----------------------------------------------------------------------------- - -- KF - ----------------------------------------------------------------------------- - kf_wrapper_1 : entity work.kf_wrapper - port map ( - clk_i => clk_p, - kfin_i => s_tftokf, - kfout_o => s_kfout - ); - - ----------------------------------------------------------------------------- - -- Output step - ----------------------------------------------------------------------------- - kfout_isolation_out_1 : entity work.kfout_isolation_out - port map ( - clk => clk_p, - out_packet => conv(d), - out_din => s_kfout, - out_dout => s_tfout - ); - - q(108) <= s_tfout(0); - q(109) <= s_tfout(1); - --q(120).strobe <= '1'; - --q(121).strobe <= '1'; - -end architecture rtl; diff --git a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/hdl/payload_altclock.vhd b/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/hdl/payload_altclock.vhd deleted file mode 100644 index 6eb4670ca56..00000000000 --- a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/hdl/payload_altclock.vhd +++ /dev/null @@ -1,216 +0,0 @@ -------------------------------------------------------------------------------- --- Title : payload --- Project : -------------------------------------------------------------------------------- --- File : payload.vhd --- Author : Filippo Marini --- Company : University of Colorado Boulder --- Created : 2022-06-21 --- Last update: 2023-06-02 --- Platform : --- Standard : VHDL'93/02 -------------------------------------------------------------------------------- --- Description: -------------------------------------------------------------------------------- --- Copyright (c) 2022 University of Colorado Boulder -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2022-06-21 1.0 fmarini Created -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use work.ipbus.all; -use work.emp_data_types.all; -use work.emp_device_decl.all; -use work.emp_ttc_decl.all; -use work.emp_slink_types.all; --- tf -use work.tf_pkg.all; -use work.memUtil_pkg.all; -use work.tf_interface_pkg.all; -use work.hybrid_data_types.all; -use work.hybrid_config.all; -use work.hybrid_data_formats.all; - -entity emp_payload is - port ( - clk : in std_logic; --unused - rst : in std_logic; - ipb_in : in ipb_wbus; --unused - clk40 : in std_logic; --unused - clk_payload : in std_logic_vector(2 downto 0); - rst_payload : in std_logic_vector(2 downto 0); --unused - clk_p : in std_logic; - rst_loc : in std_logic_vector(N_REGION - 1 downto 0); --unused - clken_loc : in std_logic_vector(N_REGION - 1 downto 0); --unused - ctrs : in ttc_stuff_array(N_REGION - 1 downto 0); --in linktosecproc, but unused - d : in ldata(4 * N_REGION - 1 downto 0); - ipb_out : out ipb_rbus; --unused - bc0 : out std_logic; --unused - q : out ldata(4 * N_REGION - 1 downto 0); - gpio : out std_logic_vector(29 downto 0); --unused - gpio_en : out std_logic_vector(29 downto 0); --unused - slink_q : out slink_input_data_quad_array(SLINK_MAX_QUADS - 1 downto 0); --unused - backpressure : in std_logic_vector(SLINK_MAX_QUADS - 1 downto 0) --unused - ); -end; - -architecture rtl of emp_payload is - - signal s_IR_data : t_arr_DL_39_DATA; - signal s_ir_start : std_logic; - signal s_bx : std_logic_vector(2 downto 0); - signal s_TW_98_stream_data : t_arr_TW_98_DATA; - signal s_TW_98_stream_valid : t_arr_TW_98_1b; - signal s_BW_46_stream_data : t_arr_BW_46_DATA; - signal s_BW_46_stream_valid : t_arr_BW_46_1b; - signal s_FT_bx_out_vld : std_logic; - signal rst_p : std_logic; - signal s_tftokf : t_channlesTB(numTW_98 - 1 downto 0); - signal s_kfout : t_frames(numLinksTFP - 1 downto 0); - signal s_tfout : ldata(numLinksTFP - 1 downto 0); - signal s_tfin : ldata(4 * N_REGION - 1 downto 0); - signal s_tfoutout : ldata(4 * N_REGION - 1 downto 0); - -begin -- architecture rtl - - ----------------------------------------------------------------------------- - -- EMP ports - ----------------------------------------------------------------------------- - slink_q <= (others => SLINK_INPUT_DATA_ARRAY_NULL); - gpio <= (others => '0'); - gpio_en <= (others => '0'); - ipb_out <= IPB_RBUS_NULL; - bc0 <= '0'; - - emp_cdc_1 : entity work.emp_cdc - generic map ( - channel_first => 68, - channel_last => 107 - ) - port map ( - clk_i => clk_p, - clk_o => clk_payload(1), - rst_i => rst, - din_i => d, - din_o => s_tfin, - rst_o => rst_p - ); - - ----------------------------------------------------------------------------- - -- Link to Sector Processor formatter - ----------------------------------------------------------------------------- - linktosecproc_1 : entity work.linktosecproc - port map ( - clk_i => clk_payload(1), - --clk_i => clk_p, - rst_i => rst_p, - --rst_i => rst, - ttc_i => ctrs, - din_i => s_tfin, - ir_start_o => s_ir_start, - bx_o => s_bx, - DL_39_link_AV_dout => s_IR_data, - DL_39_link_empty_neg => open, - DL_39_link_read => (others => '0') - ); - - ----------------------------------------------------------------------------- - -- Sector Processor - ----------------------------------------------------------------------------- - SectorProcessor_1 : entity work.SectorProcessor - port map ( - clk => clk_payload(1), - --clk => clk_p, - reset => rst_p, - --reset => rst, - IR_start => s_ir_start, - IR_bx_in => s_bx, - FT_bx_out => open, - FT_bx_out_vld => s_FT_bx_out_vld, - FT_done => open, - DL_39_link_AV_dout => s_IR_data, - DL_39_link_empty_neg => (others => '1'), - DL_39_link_read => open, - TW_98_stream_AV_din => s_TW_98_stream_data, - TW_98_stream_A_full_neg => (others => '1'), - TW_98_stream_A_write => s_TW_98_stream_valid, - BW_46_stream_AV_din => s_BW_46_stream_data, - BW_46_stream_A_full_neg => (others => '1'), - BW_46_stream_A_write => s_BW_46_stream_valid - ); - - ----------------------------------------------------------------------------- - -- Sector Processor to Link formatter - ----------------------------------------------------------------------------- - -- secproctolink_1 : entity work.secproctolink - -- port map ( - -- clk_i => clk_p, - -- TW_98_stream_data_i => s_TW_98_stream_data, - -- TW_98_stream_write_i => s_TW_98_stream_valid, - -- TW_98_stream_full_neg_o => open, - -- BW_46_stream_data_i => s_BW_46_stream_data, - -- BW_46_stream_write_i => s_BW_46_stream_valid, - -- BW_46_stream_full_neg_i => open, - -- dout_o => q - -- ); - - ----------------------------------------------------------------------------- - -- Sector Processor to KF formatter - ----------------------------------------------------------------------------- - tf_to_kf_1 : entity work.tf_to_kf - port map ( - clk_i => clk_payload(1), - --clk_i => clk_p, - TW_98_data_i => s_TW_98_stream_data, - TW_98_valid_i => s_TW_98_stream_valid, - BW_46_data_i => s_BW_46_stream_data, - BW_46_valid_i => s_BW_46_stream_valid, - kf_reset_i => s_FT_bx_out_vld, - tftokf_o => s_tftokf - ); - - ----------------------------------------------------------------------------- - -- KF - ----------------------------------------------------------------------------- - kf_wrapper_1 : entity work.kf_wrapper - port map ( - clk_i => clk_payload(1), - --clk_i => clk_p, - kfin_i => s_tftokf, - kfout_o => s_kfout - ); - - ----------------------------------------------------------------------------- - -- Output step - ----------------------------------------------------------------------------- - kfout_isolation_out_1 : entity work.kfout_isolation_out - port map ( - clk => clk_payload(1), - --clk => clk_p, - out_packet => conv(s_tfin), - out_din => s_kfout, - out_dout => s_tfout - ); - - s_tfoutout(120) <= s_tfout(0); - s_tfoutout(121) <= s_tfout(1); - --q(120).strobe <= '1'; - --q(121).strobe <= '1'; - - emp_cdc_2 : entity work.emp_cdc - generic map ( - channel_first => 120, - channel_last => 121 - ) - port map ( - clk_i => clk_payload(1), - clk_o => clk_p, - rst_i => rst_p, - din_i => s_tfoutout, - din_o => q, - rst_o => open - ); - -end architecture rtl; diff --git a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/hdl/tf_wrapper.vhd b/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/hdl/tf_wrapper.vhd deleted file mode 100644 index c50f05e8921..00000000000 --- a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/hdl/tf_wrapper.vhd +++ /dev/null @@ -1,236 +0,0 @@ -------------------------------------------------------------------------------- --- Title : tf wrapper --- Project : -------------------------------------------------------------------------------- --- File : tf_wrapper.vhd --- Author : Michael Oshiro --- Company : Cornell University --- Created : 2024-01-19 --- Last update: 2024-01-19 --- Platform : --- Standard : VHDL'93/02 -------------------------------------------------------------------------------- --- Description: Simple module to pack/unpack SectorProcessor inputs into vectors -------------------------------------------------------------------------------- --- Copyright (c) 2024 Cornell University -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2022-01-19 1.0 oshiro Created -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; - -use work.memUtil_pkg.all; -use work.memUtil_aux_pkg.all; - -entity tf_wrapper is - port ( - clk : in std_logic; - reset : in std_logic; - IR_start : in std_logic; - IR_bx_in : in std_logic_vector(2 downto 0); - FT_bx_out : out std_logic_vector(2 downto 0); - FT_bx_out_vld : out std_logic; - FT_done : out std_logic; - DL_39_link_AV_dout : in t_arr_DL_39_DATA; - DL_39_link_empty_neg : in t_arr_DL_39_1b; - DL_39_link_read : out t_arr_DL_39_1b; - TW_104_stream_AV_din : out t_arr_TW_104_DATA; - TW_104_stream_A_full_neg : in t_arr_TW_104_1b; - TW_104_stream_A_write : out t_arr_TW_104_1b; - BW_46_stream_AV_din : out t_arr_BW_46_DATA; - BW_46_stream_A_full_neg : in t_arr_BW_46_1b; - BW_46_stream_A_write : out t_arr_BW_46_1b - ); -end entity tf_wrapper; - -architecture rtl of tf_wrapper is - -begin -- architecture rtl - - SectorProcessor_1 : entity work.SectorProcessor - port map ( - clk => clk, - reset => reset, - IR_start => IR_start, - IR_bx_in => IR_bx_in, - FT_bx_out_0 => FT_bx_out, - FT_bx_out_vld => FT_bx_out_vld, - FT_done => FT_done, - FT_L1L2_last_track => open, - FT_L1L2_last_track_vld => open, - FT_L2L3_last_track => open, - FT_L2L3_last_track_vld => open, - FT_L3L4_last_track => open, - FT_L3L4_last_track_vld => open, - FT_L5L6_last_track => open, - FT_L5L6_last_track_vld => open, - DL_PS10G_1_A_link_AV_dout => DL_39_link_AV_dout(PS10G_1_A), - DL_PS10G_1_A_link_empty_neg => DL_39_link_empty_neg(PS10G_1_A), - DL_PS10G_1_A_link_read => DL_39_link_read(PS10G_1_A), - DL_PS10G_1_B_link_AV_dout => DL_39_link_AV_dout(PS10G_1_B), - DL_PS10G_1_B_link_empty_neg => DL_39_link_empty_neg(PS10G_1_B), - DL_PS10G_1_B_link_read => DL_39_link_read(PS10G_1_B), - DL_PS10G_2_A_link_AV_dout => DL_39_link_AV_dout(PS10G_2_A), - DL_PS10G_2_A_link_empty_neg => DL_39_link_empty_neg(PS10G_2_A), - DL_PS10G_2_A_link_read => DL_39_link_read(PS10G_2_A), - DL_PS10G_2_B_link_AV_dout => DL_39_link_AV_dout(PS10G_2_B), - DL_PS10G_2_B_link_empty_neg => DL_39_link_empty_neg(PS10G_2_B), - DL_PS10G_2_B_link_read => DL_39_link_read(PS10G_2_B), - DL_PS10G_3_A_link_AV_dout => DL_39_link_AV_dout(PS10G_3_A), - DL_PS10G_3_A_link_empty_neg => DL_39_link_empty_neg(PS10G_3_A), - DL_PS10G_3_A_link_read => DL_39_link_read(PS10G_3_A), - DL_PS10G_3_B_link_AV_dout => DL_39_link_AV_dout(PS10G_3_B), - DL_PS10G_3_B_link_empty_neg => DL_39_link_empty_neg(PS10G_3_B), - DL_PS10G_3_B_link_read => DL_39_link_read(PS10G_3_B), - DL_PS_1_A_link_AV_dout => DL_39_link_AV_dout(PS_1_A), - DL_PS_1_A_link_empty_neg => DL_39_link_empty_neg(PS_1_A), - DL_PS_1_A_link_read => DL_39_link_read(PS_1_A), - DL_PS_1_B_link_AV_dout => DL_39_link_AV_dout(PS_1_B), - DL_PS_1_B_link_empty_neg => DL_39_link_empty_neg(PS_1_B), - DL_PS_1_B_link_read => DL_39_link_read(PS_1_B), - DL_PS_2_A_link_AV_dout => DL_39_link_AV_dout(PS_2_A), - DL_PS_2_A_link_empty_neg => DL_39_link_empty_neg(PS_2_A), - DL_PS_2_A_link_read => DL_39_link_read(PS_2_A), - DL_PS_2_B_link_AV_dout => DL_39_link_AV_dout(PS_2_B), - DL_PS_2_B_link_empty_neg => DL_39_link_empty_neg(PS_2_B), - DL_PS_2_B_link_read => DL_39_link_read(PS_2_B), - DL_negPS10G_1_A_link_AV_dout => DL_39_link_AV_dout(negPS10G_1_A), - DL_negPS10G_1_A_link_empty_neg => DL_39_link_empty_neg(negPS10G_1_A), - DL_negPS10G_1_A_link_read => DL_39_link_read(negPS10G_1_A), - DL_negPS10G_1_B_link_AV_dout => DL_39_link_AV_dout(negPS10G_1_B), - DL_negPS10G_1_B_link_empty_neg => DL_39_link_empty_neg(negPS10G_1_B), - DL_negPS10G_1_B_link_read => DL_39_link_read(negPS10G_1_B), - DL_negPS10G_2_A_link_AV_dout => DL_39_link_AV_dout(negPS10G_2_A), - DL_negPS10G_2_A_link_empty_neg => DL_39_link_empty_neg(negPS10G_2_A), - DL_negPS10G_2_A_link_read => DL_39_link_read(negPS10G_2_A), - DL_negPS10G_2_B_link_AV_dout => DL_39_link_AV_dout(negPS10G_2_B), - DL_negPS10G_2_B_link_empty_neg => DL_39_link_empty_neg(negPS10G_2_B), - DL_negPS10G_2_B_link_read => DL_39_link_read(negPS10G_2_B), - DL_negPS10G_3_A_link_AV_dout => DL_39_link_AV_dout(negPS10G_3_A), - DL_negPS10G_3_A_link_empty_neg => DL_39_link_empty_neg(negPS10G_3_A), - DL_negPS10G_3_A_link_read => DL_39_link_read(negPS10G_3_A), - DL_negPS10G_3_B_link_AV_dout => DL_39_link_AV_dout(negPS10G_3_B), - DL_negPS10G_3_B_link_empty_neg => DL_39_link_empty_neg(negPS10G_3_B), - DL_negPS10G_3_B_link_read => DL_39_link_read(negPS10G_3_B), - DL_negPS_1_A_link_AV_dout => DL_39_link_AV_dout(negPS_1_A), - DL_negPS_1_A_link_empty_neg => DL_39_link_empty_neg(negPS_1_A), - DL_negPS_1_A_link_read => DL_39_link_read(negPS_1_A), - DL_negPS_1_B_link_AV_dout => DL_39_link_AV_dout(negPS_1_B), - DL_negPS_1_B_link_empty_neg => DL_39_link_empty_neg(negPS_1_B), - DL_negPS_1_B_link_read => DL_39_link_read(negPS_1_B), - DL_negPS_2_A_link_AV_dout => DL_39_link_AV_dout(negPS_2_A), - DL_negPS_2_A_link_empty_neg => DL_39_link_empty_neg(negPS_2_A), - DL_negPS_2_A_link_read => DL_39_link_read(negPS_2_A), - DL_negPS_2_B_link_AV_dout => DL_39_link_AV_dout(negPS_2_B), - DL_negPS_2_B_link_empty_neg => DL_39_link_empty_neg(negPS_2_B), - DL_negPS_2_B_link_read => DL_39_link_read(negPS_2_B), - DL_twoS_1_A_link_AV_dout => DL_39_link_AV_dout(twoS_1_A), - DL_twoS_1_A_link_empty_neg => DL_39_link_empty_neg(twoS_1_A), - DL_twoS_1_A_link_read => DL_39_link_read(twoS_1_A), - DL_twoS_1_B_link_AV_dout => DL_39_link_AV_dout(twoS_1_B), - DL_twoS_1_B_link_empty_neg => DL_39_link_empty_neg(twoS_1_B), - DL_twoS_1_B_link_read => DL_39_link_read(twoS_1_B), - DL_twoS_2_A_link_AV_dout => DL_39_link_AV_dout(twoS_2_A), - DL_twoS_2_A_link_empty_neg => DL_39_link_empty_neg(twoS_2_A), - DL_twoS_2_A_link_read => DL_39_link_read(twoS_2_A), - DL_twoS_2_B_link_AV_dout => DL_39_link_AV_dout(twoS_2_B), - DL_twoS_2_B_link_empty_neg => DL_39_link_empty_neg(twoS_2_B), - DL_twoS_2_B_link_read => DL_39_link_read(twoS_2_B), - DL_twoS_3_A_link_AV_dout => DL_39_link_AV_dout(twoS_3_A), - DL_twoS_3_A_link_empty_neg => DL_39_link_empty_neg(twoS_3_A), - DL_twoS_3_A_link_read => DL_39_link_read(twoS_3_A), - DL_twoS_3_B_link_AV_dout => DL_39_link_AV_dout(twoS_3_B), - DL_twoS_3_B_link_empty_neg => DL_39_link_empty_neg(twoS_3_B), - DL_twoS_3_B_link_read => DL_39_link_read(twoS_3_B), - DL_twoS_4_A_link_AV_dout => DL_39_link_AV_dout(twoS_4_A), - DL_twoS_4_A_link_empty_neg => DL_39_link_empty_neg(twoS_4_A), - DL_twoS_4_A_link_read => DL_39_link_read(twoS_4_A), - DL_twoS_4_B_link_AV_dout => DL_39_link_AV_dout(twoS_4_B), - DL_twoS_4_B_link_empty_neg => DL_39_link_empty_neg(twoS_4_B), - DL_twoS_4_B_link_read => DL_39_link_read(twoS_4_B), - DL_neg2S_1_A_link_AV_dout => DL_39_link_AV_dout(neg2S_1_A), - DL_neg2S_1_A_link_empty_neg => DL_39_link_empty_neg(neg2S_1_A), - DL_neg2S_1_A_link_read => DL_39_link_read(neg2S_1_A), - DL_neg2S_1_B_link_AV_dout => DL_39_link_AV_dout(neg2S_1_B), - DL_neg2S_1_B_link_empty_neg => DL_39_link_empty_neg(neg2S_1_B), - DL_neg2S_1_B_link_read => DL_39_link_read(neg2S_1_B), - DL_neg2S_2_A_link_AV_dout => DL_39_link_AV_dout(neg2S_2_A), - DL_neg2S_2_A_link_empty_neg => DL_39_link_empty_neg(neg2S_2_A), - DL_neg2S_2_A_link_read => DL_39_link_read(neg2S_2_A), - DL_neg2S_2_B_link_AV_dout => DL_39_link_AV_dout(neg2S_2_B), - DL_neg2S_2_B_link_empty_neg => DL_39_link_empty_neg(neg2S_2_B), - DL_neg2S_2_B_link_read => DL_39_link_read(neg2S_2_B), - DL_neg2S_3_A_link_AV_dout => DL_39_link_AV_dout(neg2S_3_A), - DL_neg2S_3_A_link_empty_neg => DL_39_link_empty_neg(neg2S_3_A), - DL_neg2S_3_A_link_read => DL_39_link_read(neg2S_3_A), - DL_neg2S_3_B_link_AV_dout => DL_39_link_AV_dout(neg2S_3_B), - DL_neg2S_3_B_link_empty_neg => DL_39_link_empty_neg(neg2S_3_B), - DL_neg2S_3_B_link_read => DL_39_link_read(neg2S_3_B), - DL_neg2S_4_A_link_AV_dout => DL_39_link_AV_dout(neg2S_4_A), - DL_neg2S_4_A_link_empty_neg => DL_39_link_empty_neg(neg2S_4_A), - DL_neg2S_4_A_link_read => DL_39_link_read(neg2S_4_A), - DL_neg2S_4_B_link_AV_dout => DL_39_link_AV_dout(neg2S_4_B), - DL_neg2S_4_B_link_empty_neg => DL_39_link_empty_neg(neg2S_4_B), - DL_neg2S_4_B_link_read => DL_39_link_read(neg2S_4_B), - TW_L1L2_stream_AV_din => TW_104_stream_AV_din(L1L2), - TW_L1L2_stream_A_full_neg => TW_104_stream_A_full_neg(L1L2), - TW_L1L2_stream_A_write => TW_104_stream_A_write(L1L2), - TW_L2L3_stream_AV_din => TW_104_stream_AV_din(L2L3), - TW_L2L3_stream_A_full_neg => TW_104_stream_A_full_neg(L2L3), - TW_L2L3_stream_A_write => TW_104_stream_A_write(L2L3), - TW_L3L4_stream_AV_din => TW_104_stream_AV_din(L3L4), - TW_L3L4_stream_A_full_neg => TW_104_stream_A_full_neg(L3L4), - TW_L3L4_stream_A_write => TW_104_stream_A_write(L3L4), - TW_L5L6_stream_AV_din => TW_104_stream_AV_din(L5L6), - TW_L5L6_stream_A_full_neg => TW_104_stream_A_full_neg(L5L6), - TW_L5L6_stream_A_write => TW_104_stream_A_write(L5L6), - BW_L1L2_L3_stream_AV_din => BW_46_stream_AV_din(L1L2_L3), - BW_L1L2_L3_stream_A_full_neg => BW_46_stream_A_full_neg(L1L2_L3), - BW_L1L2_L3_stream_A_write => BW_46_stream_A_write(L1L2_L3), - BW_L1L2_L4_stream_AV_din => BW_46_stream_AV_din(L1L2_L4), - BW_L1L2_L4_stream_A_full_neg => BW_46_stream_A_full_neg(L1L2_L4), - BW_L1L2_L4_stream_A_write => BW_46_stream_A_write(L1L2_L4), - BW_L1L2_L5_stream_AV_din => BW_46_stream_AV_din(L1L2_L5), - BW_L1L2_L5_stream_A_full_neg => BW_46_stream_A_full_neg(L1L2_L5), - BW_L1L2_L5_stream_A_write => BW_46_stream_A_write(L1L2_L5), - BW_L1L2_L6_stream_AV_din => BW_46_stream_AV_din(L1L2_L6), - BW_L1L2_L6_stream_A_full_neg => BW_46_stream_A_full_neg(L1L2_L6), - BW_L1L2_L6_stream_A_write => BW_46_stream_A_write(L1L2_L6), - BW_L2L3_L1_stream_AV_din => BW_46_stream_AV_din(L2L3_L1), - BW_L2L3_L1_stream_A_full_neg => BW_46_stream_A_full_neg(L2L3_L1), - BW_L2L3_L1_stream_A_write => BW_46_stream_A_write(L2L3_L1), - BW_L2L3_L4_stream_AV_din => BW_46_stream_AV_din(L2L3_L4), - BW_L2L3_L4_stream_A_full_neg => BW_46_stream_A_full_neg(L2L3_L4), - BW_L2L3_L4_stream_A_write => BW_46_stream_A_write(L2L3_L4), - BW_L2L3_L5_stream_AV_din => BW_46_stream_AV_din(L2L3_L5), - BW_L2L3_L5_stream_A_full_neg => BW_46_stream_A_full_neg(L2L3_L5), - BW_L2L3_L5_stream_A_write => BW_46_stream_A_write(L2L3_L5), - BW_L3L4_L1_stream_AV_din => BW_46_stream_AV_din(L3L4_L1), - BW_L3L4_L1_stream_A_full_neg => BW_46_stream_A_full_neg(L3L4_L1), - BW_L3L4_L1_stream_A_write => BW_46_stream_A_write(L3L4_L1), - BW_L3L4_L2_stream_AV_din => BW_46_stream_AV_din(L3L4_L2), - BW_L3L4_L2_stream_A_full_neg => BW_46_stream_A_full_neg(L3L4_L2), - BW_L3L4_L2_stream_A_write => BW_46_stream_A_write(L3L4_L2), - BW_L3L4_L5_stream_AV_din => BW_46_stream_AV_din(L3L4_L5), - BW_L3L4_L5_stream_A_full_neg => BW_46_stream_A_full_neg(L3L4_L5), - BW_L3L4_L5_stream_A_write => BW_46_stream_A_write(L3L4_L5), - BW_L3L4_L6_stream_AV_din => BW_46_stream_AV_din(L3L4_L6), - BW_L3L4_L6_stream_A_full_neg => BW_46_stream_A_full_neg(L3L4_L6), - BW_L3L4_L6_stream_A_write => BW_46_stream_A_write(L3L4_L6), - BW_L5L6_L1_stream_AV_din => BW_46_stream_AV_din(L5L6_L1), - BW_L5L6_L1_stream_A_full_neg => BW_46_stream_A_full_neg(L5L6_L1), - BW_L5L6_L1_stream_A_write => BW_46_stream_A_write(L5L6_L1), - BW_L5L6_L2_stream_AV_din => BW_46_stream_AV_din(L5L6_L2), - BW_L5L6_L2_stream_A_full_neg => BW_46_stream_A_full_neg(L5L6_L2), - BW_L5L6_L2_stream_A_write => BW_46_stream_A_write(L5L6_L2), - BW_L5L6_L3_stream_AV_din => BW_46_stream_AV_din(L5L6_L3), - BW_L5L6_L3_stream_A_full_neg => BW_46_stream_A_full_neg(L5L6_L3), - BW_L5L6_L3_stream_A_write => BW_46_stream_A_write(L5L6_L3), - BW_L5L6_L4_stream_AV_din => BW_46_stream_AV_din(L5L6_L4), - BW_L5L6_L4_stream_A_full_neg => BW_46_stream_A_full_neg(L5L6_L4), - BW_L5L6_L4_stream_A_write => BW_46_stream_A_write(L5L6_L4) - ); - -end architecture rtl; diff --git a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/scripts/convert_emData2EMP_Link.py b/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/scripts/convert_emData2EMP_Link.py deleted file mode 100644 index 4934d6e26ce..00000000000 --- a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/scripts/convert_emData2EMP_Link.py +++ /dev/null @@ -1,108 +0,0 @@ -import argparse -import os - -# Run with python3 in work/proj/ -# Converts InputRouter input data from emData to EMP format - -def parseArguments(): - # Create argument parser - parser = argparse.ArgumentParser(description="Convert an emData/ memory data file into a EMP format file. Link-file mapping is done editing the header of the script.") - - # Optional arguments - parser.add_argument("-d", "--directory", dest="inputDir", help="directory containing input data", type=str, default="emData/MemPrintsReduced/InputStubs/") - parser.add_argument("-o","--outFile", dest="outFile", help="output file name", type=str, default="Link_EMP.txt") - - # Parse arguments - args = parser.parse_args() - - return args - -# Files in order in which they are referred to in memUtil_pkg.vhd. -# with key being channel number. -channel_names = ["PS10G_1_A", "PS10G_1_B", "PS10G_2_A", "PS10G_2_B", "PS10G_3_A", "PS10G_3_B", "PS_1_A", "PS_1_B", "PS_2_A", "PS_2_B", "negPS10G_1_A", "negPS10G_1_B", "negPS10G_2_A", "negPS10G_2_B", "negPS10G_3_A", "negPS10G_3_B", "negPS_1_A", "negPS_1_B", "negPS_2_A", "negPS_2_B", "2S_1_A", "2S_1_B", "2S_2_A", "2S_2_B", "2S_3_A", "2S_3_B", "2S_4_A", "2S_4_B", "neg2S_1_A", "neg2S_1_B", "neg2S_2_A", "neg2S_2_B", "neg2S_3_A", "neg2S_3_B", "neg2S_4_A", "neg2S_4_B"] -channel_numbers = [68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107] - -mapping = {} -for ich in range(len(channel_names)): - mapping[channel_numbers[ich]] = "Link_DL_"+channel_names[ich]+"_04.dat" - -#channels = ["q00c0","q00c1","q00c2","q00c3","q01c0","q01c1","q01c2","q01c3","q02c0","q02c1","q02c2","q02c3","q03c0","q03c1","q03c2","q03c3"] - -empWordLen=16 # Hex chars in an EMP data word -clksInTM=108 # Length of TM period in clock cycles -clksInGap=6 # Gap when no valid data sent. - -if __name__ == '__main__': - - args = parseArguments() - - outFile = open(args.outFile, 'w') - - allData = {} - for chan, fileName in mapping.items(): - file = open(args.inputDir + "/" + fileName, 'r') - lines = file.readlines() - for line in lines: - words = line.split() - if len(words) == 6: - eventNumber = int(words[5]) - allData[(eventNumber,chan)] = [] - if len(words) == 3: - addr = words[0] - data = words[2] - empData = data[2:].zfill(empWordLen) - allData[(eventNumber,chan)].append(empData) - - outFile.write("ID: x0\n") - outFile.write("Metadata: (strobe,) start of orbit, start of packet, end of packet, valid\n") - outFile.write("\n") - outFile.write(" Link ") - for chan in mapping: - outFile.write("%s " %(str(chan).zfill(3))) - outFile.write("\n") - - gapData = "0000000000000000" - nullData = "0000000000000000" - md_null = "0000" - md_valid = "0001" - md_soe = "0101" - md_soo = "1101" - md_eoe = "0011" - iClk = 0 - - for event in range(1+eventNumber): - for iFrame in range(0,clksInTM): - iFrameCorr = iFrame - clksInGap - iClk += 1 - outFile.write("Frame %s " %(str(iClk-1).zfill(4))) - for chan in mapping: - theKey = (event,chan) - empDataList = allData[theKey] - if (iFrame < clksInGap): - outFile.write("%s " %md_null) - outFile.write("%s " %gapData) - elif (iFrameCorr < len(empDataList)): - if (event == 0) : - if (iFrameCorr == 0) : - outFile.write("%s " %md_soo) - elif (iFrame == clksInTM - 1) : - outFile.write("%s " %md_eoe) - else : - outFile.write("%s " %md_valid) - else : - if (iFrameCorr == 0) : - outFile.write("%s " %md_soe) - elif (iFrame == clksInTM - 1) : - outFile.write("%s " %md_eoe) - else : - outFile.write("%s " %md_valid) - outFile.write("%s " %empDataList[iFrameCorr]) - else: - if (iFrame == clksInTM - 1) : - outFile.write("%s " %md_eoe) - else : - outFile.write("%s " %md_valid) - outFile.write("%s " %nullData) - outFile.write("\n") - print("Output written to file ",args.outFile) - diff --git a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/ucf/ip.tcl b/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/ucf/ip.tcl deleted file mode 100644 index a8e841ce929..00000000000 --- a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/ucf/ip.tcl +++ /dev/null @@ -1,4 +0,0 @@ -catch {get_property ip_repo_paths [current_project]} curr_ip_path -set set_ip_path "set_property ip_repo_paths {${curr_ip_path} ../../../src/firmware-hls/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/cgn/} \[\current_project\]" -eval ${set_ip_path} -update_ip_catalog diff --git a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/ucf/vsim.tcl b/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/ucf/vsim.tcl deleted file mode 100644 index b6f27fa0f2d..00000000000 --- a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/ucf/vsim.tcl +++ /dev/null @@ -1,11 +0,0 @@ -set_property SOURCE_SET sources_1 [get_filesets sim_1] -add_files -fileset sim_1 -norecurse ../../src/firmware-hls/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/mem/in.txt - -# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention. -set_property source_mgmt_mode None [current_project] -set_property top top [get_filesets sim_1] -set_property top_lib xil_defaultlib [get_filesets sim_1] -set_property target_language VHDL [current_project] -set_property simulator_language VHDL [current_project] -# Re-enabling previously disabled source management mode. -set_property source_mgmt_mode All [current_project] diff --git a/IntegrationTests/CombinedBarrelConfig/script/Makefile b/IntegrationTests/CombinedBarrelConfig/script/Makefile deleted file mode 100644 index 40a2aa2c0d1..00000000000 --- a/IntegrationTests/CombinedBarrelConfig/script/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# Define base directory of firmware-hls clone. -FIRMWARE=$(shell git rev-parse --show-toplevel) - -# MODIFY THESE LINES WHEN COPYING AND PASTING THIS MAKEFILE -TOP_FUNCS=$(FIRMWARE)/TopFunctions/CombinedBarrelConfig -MODULES=InputRouterTop_IR_DTC_2S_1_A InputRouterTop_IR_DTC_2S_1_B InputRouterTop_IR_DTC_2S_2_A InputRouterTop_IR_DTC_2S_2_B InputRouterTop_IR_DTC_2S_3_A InputRouterTop_IR_DTC_2S_3_B InputRouterTop_IR_DTC_2S_4_A InputRouterTop_IR_DTC_2S_4_B InputRouterTop_IR_DTC_neg2S_1_A InputRouterTop_IR_DTC_neg2S_1_B InputRouterTop_IR_DTC_neg2S_2_A InputRouterTop_IR_DTC_neg2S_2_B InputRouterTop_IR_DTC_neg2S_3_A InputRouterTop_IR_DTC_neg2S_3_B InputRouterTop_IR_DTC_neg2S_4_A InputRouterTop_IR_DTC_neg2S_4_B InputRouterTop_IR_DTC_negPS10G_1_A InputRouterTop_IR_DTC_negPS10G_1_B InputRouterTop_IR_DTC_negPS10G_2_A InputRouterTop_IR_DTC_negPS10G_2_B InputRouterTop_IR_DTC_negPS10G_3_A InputRouterTop_IR_DTC_negPS10G_3_B InputRouterTop_IR_DTC_negPS_1_A InputRouterTop_IR_DTC_negPS_1_B InputRouterTop_IR_DTC_negPS_2_A InputRouterTop_IR_DTC_negPS_2_B InputRouterTop_IR_DTC_PS10G_1_A InputRouterTop_IR_DTC_PS10G_1_B InputRouterTop_IR_DTC_PS10G_2_A InputRouterTop_IR_DTC_PS10G_2_B InputRouterTop_IR_DTC_PS10G_3_A InputRouterTop_IR_DTC_PS10G_3_B InputRouterTop_IR_DTC_PS_1_A InputRouterTop_IR_DTC_PS_1_B InputRouterTop_IR_DTC_PS_2_A InputRouterTop_IR_DTC_PS_2_B VMRouterCMTop_L1PHIA VMRouterCMTop_L1PHIB VMRouterCMTop_L1PHIC VMRouterCMTop_L1PHID VMRouterCMTop_L1PHIE VMRouterCMTop_L1PHIF VMRouterCMTop_L1PHIG VMRouterCMTop_L1PHIH VMRouterCMTop_L2PHIA VMRouterCMTop_L2PHIB VMRouterCMTop_L2PHIC VMRouterCMTop_L2PHID VMRouterCMTop_L3PHIA VMRouterCMTop_L3PHIB VMRouterCMTop_L3PHIC VMRouterCMTop_L3PHID VMRouterCMTop_L4PHIA VMRouterCMTop_L4PHIB VMRouterCMTop_L4PHIC VMRouterCMTop_L4PHID VMRouterCMTop_L5PHIA VMRouterCMTop_L5PHIB VMRouterCMTop_L5PHIC VMRouterCMTop_L5PHID VMRouterCMTop_L6PHIA VMRouterCMTop_L6PHIB VMRouterCMTop_L6PHIC VMRouterCMTop_L6PHID TrackletProcessor_L1L2A TrackletProcessor_L1L2B TrackletProcessor_L1L2C TrackletProcessor_L1L2D TrackletProcessor_L1L2E TrackletProcessor_L1L2F TrackletProcessor_L1L2G TrackletProcessor_L1L2H TrackletProcessor_L1L2I TrackletProcessor_L1L2J TrackletProcessor_L1L2K TrackletProcessor_L1L2L TrackletProcessor_L2L3A TrackletProcessor_L2L3B TrackletProcessor_L2L3C TrackletProcessor_L2L3D TrackletProcessor_L3L4A TrackletProcessor_L3L4B TrackletProcessor_L3L4C TrackletProcessor_L3L4D TrackletProcessor_L5L6A TrackletProcessor_L5L6B TrackletProcessor_L5L6C TrackletProcessor_L5L6D MatchProcessor_L1PHIA MatchProcessor_L1PHIB MatchProcessor_L1PHIC MatchProcessor_L1PHID MatchProcessor_L1PHIE MatchProcessor_L1PHIF MatchProcessor_L1PHIG MatchProcessor_L1PHIH MatchProcessor_L2PHIA MatchProcessor_L2PHIB MatchProcessor_L2PHIC MatchProcessor_L2PHID MatchProcessor_L3PHIA MatchProcessor_L3PHIB MatchProcessor_L3PHIC MatchProcessor_L3PHID MatchProcessor_L4PHIA MatchProcessor_L4PHIB MatchProcessor_L4PHIC MatchProcessor_L4PHID MatchProcessor_L5PHIA MatchProcessor_L5PHIB MatchProcessor_L5PHIC MatchProcessor_L5PHID MatchProcessor_L6PHIA MatchProcessor_L6PHIB MatchProcessor_L6PHIC MatchProcessor_L6PHID TrackBuilder_L1L2 TrackBuilder_L2L3 TrackBuilder_L3L4 TrackBuilder_L5L6 - -# Include rules for making the project. -include $(FIRMWARE)/IntegrationTests/common/script/Makefile.mk diff --git a/IntegrationTests/CombinedBarrelConfig/script/floorplan.xdc b/IntegrationTests/CombinedBarrelConfig/script/floorplan.xdc deleted file mode 100644 index 1102e1f787a..00000000000 --- a/IntegrationTests/CombinedBarrelConfig/script/floorplan.xdc +++ /dev/null @@ -1,235 +0,0 @@ -#this XDC contains physical constraints for the out-of-context combined barrel chain -create_pblock pblock_MPL3L4L5L6 -add_cells_to_pblock [get_pblocks pblock_MPL3L4L5L6] [get_cells -quiet [list \ - MP_L3PHIA \ - MP_L3PHIB \ - MP_L3PHIC \ - MP_L3PHID \ - MP_L4PHIA \ - MP_L4PHIB \ - MP_L4PHIC \ - MP_L4PHID \ - MP_L5PHIA \ - MP_L5PHIB \ - MP_L5PHIC \ - MP_L5PHID \ - MP_L6PHIA \ - MP_L6PHIB \ - MP_L6PHID \ - MP_L6PHIC]] -resize_pblock [get_pblocks pblock_MPL3L4L5L6] -add {CLOCKREGION_X0Y8:CLOCKREGION_X7Y9} -create_pblock pblock_MPL1L2 -add_cells_to_pblock [get_pblocks pblock_MPL1L2] [get_cells -quiet [list \ - MP_L1PHIA \ - MP_L1PHIB \ - MP_L1PHIC \ - MP_L1PHID \ - MP_L1PHIE \ - MP_L1PHIF \ - MP_L1PHIG \ - MP_L1PHIH \ - MP_L2PHIA \ - MP_L2PHIB \ - MP_L2PHIC \ - MP_L2PHID]] -resize_pblock [get_pblocks pblock_MPL1L2] -add {CLOCKREGION_X0Y4:CLOCKREGION_X7Y5} -create_pblock pblock_TPL1L2 -add_cells_to_pblock [get_pblocks pblock_TPL1L2] [get_cells -quiet [list \ - TP_L1L2A \ - TP_L1L2A_lut \ - TP_L1L2A_regionlut \ - TP_L1L2B \ - TP_L1L2B_lut \ - TP_L1L2B_regionlut \ - TP_L1L2C \ - TP_L1L2C_lut \ - TP_L1L2C_regionlut \ - TP_L1L2D \ - TP_L1L2D_lut \ - TP_L1L2D_regionlut \ - TP_L1L2E \ - TP_L1L2E_lut \ - TP_L1L2E_regionlut \ - TP_L1L2F \ - TP_L1L2F_lut \ - TP_L1L2F_regionlut \ - TP_L1L2G \ - TP_L1L2G_lut \ - TP_L1L2G_regionlut \ - TP_L1L2H \ - TP_L1L2H_lut \ - TP_L1L2H_regionlut \ - TP_L1L2I \ - TP_L1L2I_lut \ - TP_L1L2I_regionlut \ - TP_L1L2J \ - TP_L1L2J_lut \ - TP_L1L2J_regionlut \ - TP_L1L2K \ - TP_L1L2K_lut \ - TP_L1L2K_regionlut \ - TP_L1L2L \ - TP_L1L2L_lut \ - TP_L1L2L_regionlut]] -resize_pblock [get_pblocks pblock_TPL1L2] -add {CLOCKREGION_X0Y11:CLOCKREGION_X7Y10} - -create_pblock pblock_TPL3L4 -add_cells_to_pblock [get_pblocks pblock_TPL3L4] [get_cells -quiet [list \ - TP_L2L3A \ - TP_L2L3A_lut \ - TP_L2L3A_regionlut \ - TP_L2L3B \ - TP_L2L3B_lut \ - TP_L2L3B_regionlut \ - TP_L2L3C \ - TP_L2L3C_lut \ - TP_L2L3C_regionlut \ - TP_L2L3D \ - TP_L2L3D_lut \ - TP_L2L3D_regionlut \ - TP_L3L4A \ - TP_L3L4A_lut \ - TP_L3L4A_regionlut \ - TP_L3L4B \ - TP_L3L4B_lut \ - TP_L3L4B_regionlut \ - TP_L3L4C \ - TP_L3L4C_lut \ - TP_L3L4C_regionlut \ - TP_L3L4D \ - TP_L3L4D_lut \ - TP_L3L4D_regionlut \ - TP_L5L6A \ - TP_L5L6A_lut \ - TP_L5L6A_regionlut \ - TP_L5L6B \ - TP_L5L6B_lut \ - TP_L5L6B_regionlut \ - TP_L5L6C \ - TP_L5L6C_lut \ - TP_L5L6C_regionlut \ - TP_L5L6D \ - TP_L5L6D_lut \ - TP_L5L6D_regionlut]] -resize_pblock [get_pblocks pblock_TPL3L4] -add {CLOCKREGION_X0Y6:CLOCKREGION_X7Y7} - -create_pblock pblock_FTs -add_cells_to_pblock [get_pblocks pblock_FTs] [get_cells -quiet [list \ - {FM_52_loop[*].FM_52} \ - {FM_52_delay_loop[*].FM_52} \ - FT_L1L2 \ - FT_L2L3 \ - FT_L3L4 \ - FT_L5L6 \ - {TPAR_70_loop[*].TPAR_70}]] -resize_pblock [get_pblocks pblock_FTs] -add {CLOCKREGION_X1Y0:CLOCKREGION_X6Y3} -create_pblock pblock_IRsVMRs -add_cells_to_pblock [get_pblocks pblock_IRsVMRs] [get_cells -quiet [list \ - {IL_36_loop[*].IL_36}\ - IR_2S_1_A \ - IR_2S_1_B \ - IR_2S_2_A \ - IR_2S_2_B \ - IR_2S_3_A \ - IR_2S_3_B \ - IR_2S_4_A \ - IR_2S_4_B \ - IR_PS10G_1_A \ - IR_PS10G_1_B \ - IR_PS10G_2_A \ - IR_PS10G_2_B \ - IR_PS10G_3_A \ - IR_PS10G_3_B \ - IR_PS_1_A \ - IR_PS_1_B \ - IR_PS_2_A \ - IR_PS_2_B \ - IR_neg2S_1_A \ - IR_neg2S_1_B \ - IR_neg2S_2_A \ - IR_neg2S_2_B \ - IR_neg2S_3_A \ - IR_neg2S_3_B \ - IR_neg2S_4_A \ - IR_neg2S_4_B \ - IR_negPS10G_1_A \ - IR_negPS10G_1_B \ - IR_negPS10G_2_A \ - IR_negPS10G_2_B \ - IR_negPS10G_3_A \ - IR_negPS10G_3_B \ - IR_negPS_1_A \ - IR_negPS_1_B \ - IR_negPS_2_A \ - IR_negPS_2_B]] -resize_pblock [get_pblocks pblock_IRsVMRs] -add {CLOCKREGION_X1Y12:CLOCKREGION_X6Y15} - -create_pblock pblock_1 -resize_pblock [get_pblocks pblock_1] -add {CLOCKREGION_X0Y12:CLOCKREGION_X0Y15} -set_property EXCLUDE_PLACEMENT 1 [get_pblocks pblock_1] -create_pblock pblock_2 -resize_pblock [get_pblocks pblock_2] -add {CLOCKREGION_X7Y12:CLOCKREGION_X7Y15} -set_property EXCLUDE_PLACEMENT 1 [get_pblocks pblock_2] - -create_pblock pblock_3 -resize_pblock [get_pblocks pblock_3] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y3} -set_property EXCLUDE_PLACEMENT 1 [get_pblocks pblock_3] -create_pblock pblock_4 -resize_pblock [get_pblocks pblock_4] -add {CLOCKREGION_X7Y0:CLOCKREGION_X7Y3} -set_property EXCLUDE_PLACEMENT 1 [get_pblocks pblock_4] - -set_property USER_CLUSTER group_TP_L1L2A [get_cells [list TP_L1L2A TP_L1L2A_lut TP_L1L2A_regionlut]] -set_property USER_CLUSTER group_TP_L1L2B [get_cells [list TP_L1L2B TP_L1L2B_lut TP_L1L2B_regionlut]] -set_property USER_CLUSTER group_TP_L1L2C [get_cells [list TP_L1L2C TP_L1L2C_lut TP_L1L2C_regionlut]] -set_property USER_CLUSTER group_TP_L1L2D [get_cells [list TP_L1L2D TP_L1L2D_lut TP_L1L2D_regionlut]] -set_property USER_CLUSTER group_TP_L1L2E [get_cells [list TP_L1L2E TP_L1L2E_lut TP_L1L2E_regionlut]] -set_property USER_CLUSTER group_TP_L1L2F [get_cells [list TP_L1L2F TP_L1L2F_lut TP_L1L2F_regionlut]] -set_property USER_CLUSTER group_TP_L1L2G [get_cells [list TP_L1L2G TP_L1L2G_lut TP_L1L2G_regionlut]] -set_property USER_CLUSTER group_TP_L1L2H [get_cells [list TP_L1L2H TP_L1L2H_lut TP_L1L2H_regionlut]] -set_property USER_CLUSTER group_TP_L1L2I [get_cells [list TP_L1L2I TP_L1L2I_lut TP_L1L2I_regionlut]] -set_property USER_CLUSTER group_TP_L1L2J [get_cells [list TP_L1L2J TP_L1L2J_lut TP_L1L2J_regionlut]] -set_property USER_CLUSTER group_TP_L1L2K [get_cells [list TP_L1L2K TP_L1L2K_lut TP_L1L2K_regionlut]] -set_property USER_CLUSTER group_TP_L1L2L [get_cells [list TP_L1L2L TP_L1L2L_lut TP_L1L2L_regionlut]] -set_property USER_CLUSTER group_TP_L2L3A [get_cells [list TP_L2L3A TP_L2L3A_lut TP_L2L3A_regionlut]] -set_property USER_CLUSTER group_TP_L2L3B [get_cells [list TP_L2L3B TP_L2L3B_lut TP_L2L3B_regionlut]] -set_property USER_CLUSTER group_TP_L2L3C [get_cells [list TP_L2L3C TP_L2L3C_lut TP_L2L3C_regionlut]] -set_property USER_CLUSTER group_TP_L2L3D [get_cells [list TP_L2L3D TP_L2L3D_lut TP_L2L3D_regionlut]] -set_property USER_CLUSTER group_TP_L3L4A [get_cells [list TP_L3L4A TP_L3L4A_lut TP_L3L4A_regionlut]] -set_property USER_CLUSTER group_TP_L3L4B [get_cells [list TP_L3L4B TP_L3L4B_lut TP_L3L4B_regionlut]] -set_property USER_CLUSTER group_TP_L3L4C [get_cells [list TP_L3L4C TP_L3L4C_lut TP_L3L4C_regionlut]] -set_property USER_CLUSTER group_TP_L3L4D [get_cells [list TP_L3L4D TP_L3L4D_lut TP_L3L4D_regionlut]] -set_property USER_CLUSTER group_TP_L5L6A [get_cells [list TP_L5L6A TP_L5L6A_lut TP_L5L6A_regionlut]] -set_property USER_CLUSTER group_TP_L5L6B [get_cells [list TP_L5L6B TP_L5L6B_lut TP_L5L6B_regionlut]] -set_property USER_CLUSTER group_TP_L5L6C [get_cells [list TP_L5L6C TP_L5L6C_lut TP_L5L6C_regionlut]] -set_property USER_CLUSTER group_TP_L5L6D [get_cells [list TP_L5L6D TP_L5L6D_lut TP_L5L6D_regionlut]] -set_property USER_CLUSTER group_MP_L1PHIA [get_cells MP_L1PHIA] -set_property USER_CLUSTER group_MP_L1PHIB [get_cells MP_L1PHIB] -set_property USER_CLUSTER group_MP_L1PHIC [get_cells MP_L1PHIC] -set_property USER_CLUSTER group_MP_L1PHID [get_cells MP_L1PHID] -set_property USER_CLUSTER group_MP_L1PHIE [get_cells MP_L1PHIE] -set_property USER_CLUSTER group_MP_L1PHIF [get_cells MP_L1PHIF] -set_property USER_CLUSTER group_MP_L1PHIG [get_cells MP_L1PHIG] -set_property USER_CLUSTER group_MP_L1PHIH [get_cells MP_L1PHIH] -set_property USER_CLUSTER group_MP_L2PHIA [get_cells MP_L2PHIA] -set_property USER_CLUSTER group_MP_L2PHIB [get_cells MP_L2PHIB] -set_property USER_CLUSTER group_MP_L2PHIC [get_cells MP_L2PHIC] -set_property USER_CLUSTER group_MP_L2PHID [get_cells MP_L2PHID] -set_property USER_CLUSTER group_MP_L3PHIA [get_cells MP_L3PHIA] -set_property USER_CLUSTER group_MP_L3PHIB [get_cells MP_L3PHIB] -set_property USER_CLUSTER group_MP_L3PHIC [get_cells MP_L3PHIC] -set_property USER_CLUSTER group_MP_L3PHID [get_cells MP_L3PHID] -set_property USER_CLUSTER group_MP_L4PHIA [get_cells MP_L4PHIA] -set_property USER_CLUSTER group_MP_L4PHIB [get_cells MP_L4PHIB] -set_property USER_CLUSTER group_MP_L4PHIC [get_cells MP_L4PHIC] -set_property USER_CLUSTER group_MP_L4PHID [get_cells MP_L4PHID] -set_property USER_CLUSTER group_MP_L5PHIA [get_cells MP_L5PHIA] -set_property USER_CLUSTER group_MP_L5PHIB [get_cells MP_L5PHIB] -set_property USER_CLUSTER group_MP_L5PHIC [get_cells MP_L5PHIC] -set_property USER_CLUSTER group_MP_L5PHID [get_cells MP_L5PHID] -set_property USER_CLUSTER group_MP_L6PHIA [get_cells MP_L6PHIA] -set_property USER_CLUSTER group_MP_L6PHIB [get_cells MP_L6PHIB] -set_property USER_CLUSTER group_MP_L6PHIC [get_cells MP_L6PHIC] -set_property USER_CLUSTER group_MP_L6PHID [get_cells MP_L6PHID] - - - diff --git a/IntegrationTests/CombinedBarrelConfig/script/makeProject.tcl b/IntegrationTests/CombinedBarrelConfig/script/makeProject.tcl deleted file mode 100644 index 7a523583f75..00000000000 --- a/IntegrationTests/CombinedBarrelConfig/script/makeProject.tcl +++ /dev/null @@ -1,168 +0,0 @@ -# Create Vivado project, with user HDL files & IP. -# Run this in IntegrationTests/xyz/script/ - -# Create project -set projName "Work" -set FPGA "xcvu13p-flga2577-2-e" -create_project -force ${projName} ./${projName} -part $FPGA -set_property target_language VHDL [current_project] - -# Rebuild user HLS IP repos index before adding any source files -set_property ip_repo_paths "./" [get_filesets sources_1] -update_ip_catalog -rebuild - -# Create .xci files for user HLS IP -create_ip -name InputRouterTop_IR_DTC_PS10G_1_A -module_name IR_PS10G_1_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_PS10G_1_B -module_name IR_PS10G_1_B -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_PS10G_2_A -module_name IR_PS10G_2_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_PS10G_2_B -module_name IR_PS10G_2_B -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_PS10G_3_A -module_name IR_PS10G_3_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_PS10G_3_B -module_name IR_PS10G_3_B -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_PS_1_A -module_name IR_PS_1_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_PS_1_B -module_name IR_PS_1_B -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_PS_2_A -module_name IR_PS_2_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_PS_2_B -module_name IR_PS_2_B -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_2S_1_A -module_name IR_2S_1_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_2S_1_B -module_name IR_2S_1_B -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_2S_2_A -module_name IR_2S_2_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_2S_2_B -module_name IR_2S_2_B -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_2S_3_A -module_name IR_2S_3_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_2S_3_B -module_name IR_2S_3_B -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_2S_4_A -module_name IR_2S_4_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_2S_4_B -module_name IR_2S_4_B -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_negPS10G_1_A -module_name IR_negPS10G_1_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_negPS10G_1_B -module_name IR_negPS10G_1_B -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_negPS10G_2_A -module_name IR_negPS10G_2_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_negPS10G_2_B -module_name IR_negPS10G_2_B -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_negPS10G_3_A -module_name IR_negPS10G_3_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_negPS10G_3_B -module_name IR_negPS10G_3_B -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_negPS_1_A -module_name IR_negPS_1_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_negPS_1_B -module_name IR_negPS_1_B -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_negPS_2_A -module_name IR_negPS_2_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_negPS_2_B -module_name IR_negPS_2_B -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_neg2S_1_A -module_name IR_neg2S_1_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_neg2S_1_B -module_name IR_neg2S_1_B -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_neg2S_2_A -module_name IR_neg2S_2_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_neg2S_2_B -module_name IR_neg2S_2_B -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_neg2S_3_A -module_name IR_neg2S_3_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_neg2S_3_B -module_name IR_neg2S_3_B -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_neg2S_4_A -module_name IR_neg2S_4_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_neg2S_4_B -module_name IR_neg2S_4_B -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L1PHIA -module_name VMR_L1PHIA -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L1PHIB -module_name VMR_L1PHIB -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L1PHIC -module_name VMR_L1PHIC -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L1PHID -module_name VMR_L1PHID -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L1PHIE -module_name VMR_L1PHIE -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L1PHIF -module_name VMR_L1PHIF -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L1PHIG -module_name VMR_L1PHIG -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L1PHIH -module_name VMR_L1PHIH -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L2PHIA -module_name VMR_L2PHIA -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L2PHIB -module_name VMR_L2PHIB -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L2PHIC -module_name VMR_L2PHIC -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L2PHID -module_name VMR_L2PHID -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L3PHIA -module_name VMR_L3PHIA -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L3PHIB -module_name VMR_L3PHIB -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L3PHIC -module_name VMR_L3PHIC -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L3PHID -module_name VMR_L3PHID -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L4PHIA -module_name VMR_L4PHIA -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L4PHIB -module_name VMR_L4PHIB -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L4PHIC -module_name VMR_L4PHIC -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L4PHID -module_name VMR_L4PHID -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L5PHIA -module_name VMR_L5PHIA -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L5PHIB -module_name VMR_L5PHIB -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L5PHIC -module_name VMR_L5PHIC -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L5PHID -module_name VMR_L5PHID -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L6PHIA -module_name VMR_L6PHIA -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L6PHIB -module_name VMR_L6PHIB -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L6PHIC -module_name VMR_L6PHIC -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L6PHID -module_name VMR_L6PHID -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L1L2A -module_name TP_L1L2A -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L1L2B -module_name TP_L1L2B -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L1L2C -module_name TP_L1L2C -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L1L2D -module_name TP_L1L2D -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L1L2E -module_name TP_L1L2E -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L1L2F -module_name TP_L1L2F -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L1L2G -module_name TP_L1L2G -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L1L2H -module_name TP_L1L2H -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L1L2I -module_name TP_L1L2I -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L1L2J -module_name TP_L1L2J -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L1L2K -module_name TP_L1L2K -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L1L2L -module_name TP_L1L2L -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L2L3A -module_name TP_L2L3A -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L2L3B -module_name TP_L2L3B -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L2L3C -module_name TP_L2L3C -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L2L3D -module_name TP_L2L3D -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L3L4A -module_name TP_L3L4A -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L3L4B -module_name TP_L3L4B -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L3L4C -module_name TP_L3L4C -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L3L4D -module_name TP_L3L4D -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L5L6A -module_name TP_L5L6A -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L5L6B -module_name TP_L5L6B -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L5L6C -module_name TP_L5L6C -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L5L6D -module_name TP_L5L6D -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L1PHIA -module_name MP_L1PHIA -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L1PHIB -module_name MP_L1PHIB -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L1PHIC -module_name MP_L1PHIC -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L1PHID -module_name MP_L1PHID -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L1PHIE -module_name MP_L1PHIE -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L1PHIF -module_name MP_L1PHIF -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L1PHIG -module_name MP_L1PHIG -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L1PHIH -module_name MP_L1PHIH -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L2PHIA -module_name MP_L2PHIA -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L2PHIB -module_name MP_L2PHIB -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L2PHIC -module_name MP_L2PHIC -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L2PHID -module_name MP_L2PHID -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L3PHIA -module_name MP_L3PHIA -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L3PHIB -module_name MP_L3PHIB -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L3PHIC -module_name MP_L3PHIC -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L3PHID -module_name MP_L3PHID -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L4PHIA -module_name MP_L4PHIA -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L4PHIB -module_name MP_L4PHIB -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L4PHIC -module_name MP_L4PHIC -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L4PHID -module_name MP_L4PHID -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L5PHIA -module_name MP_L5PHIA -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L5PHIB -module_name MP_L5PHIB -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L5PHIC -module_name MP_L5PHIC -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L5PHID -module_name MP_L5PHID -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L6PHIA -module_name MP_L6PHIA -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L6PHIB -module_name MP_L6PHIB -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L6PHIC -module_name MP_L6PHIC -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L6PHID -module_name MP_L6PHID -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackBuilder_L1L2 -module_name FT_L1L2 -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackBuilder_L2L3 -module_name FT_L2L3 -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackBuilder_L3L4 -module_name FT_L3L4 -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackBuilder_L5L6 -module_name FT_L5L6 -vendor xilinx.com -library hls -version 1.0 - - -# Provide name of top-level HDL (without .vhd extension). -#set topLevelHDL "SectorProcessor" -set topLevelHDL "SectorProcessorFull" - -# Add HDL for algo -add_files -fileset sources_1 [glob ../hdl/SectorProcessor.vhd] -add_files -fileset sources_1 [glob ../hdl/SectorProcessorFull.vhd] -add_files -fileset sources_1 [glob ../hdl/memUtil_pkg.vhd] -add_files -fileset sources_1 [glob common/hdl/*.vhd] -remove_files -fileset sources_1 [glob common/hdl/latency_monitor.vhd] -remove_files -fileset sources_1 [glob common/hdl/tf_mem_new.vhd] - - -# Add HDL for TB -add_files -fileset sim_1 [glob ../tb/tb_tf_top.vhd] - -# Add constraints (clock etc.) -add_files -fileset constrs_1 [glob common/hdl/constraints.xdc] -add_files -fileset constrs_1 [glob floorplan.xdc] - -# Set 'sim_1' fileset properties -set_property file_type {VHDL 2008} [get_files -filter {FILE_TYPE == VHDL}] -set_property top -value ${topLevelHDL} -objects [get_filesets sim_1] -set_property top -value "tb_tf_top" -objects [get_filesets sim_1] -set_property xsim.simulate.runtime -value "0us" -objects [get_filesets sim_1] -set_property simulator_language VHDL [current_project] - -update_compile_order -fileset sources_1 - -puts "INFO: Project created: ${projName}" - -exit diff --git a/IntegrationTests/CombinedBarrelConfig/tb/start_bx.wcfg b/IntegrationTests/CombinedBarrelConfig/tb/start_bx.wcfg deleted file mode 100644 index 92b530a8d90..00000000000 --- a/IntegrationTests/CombinedBarrelConfig/tb/start_bx.wcfg +++ /dev/null @@ -1,92 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - clk - clk - - - addr_nentA[4:0] - addr_nentA[4:0] - - - sa_RAM_nentA0[0:31][3:0] - sa_RAM_nentA0[0:31][3:0] - - - sa_RAM_nentA1[0:31][3:0] - sa_RAM_nentA1[0:31][3:0] - - - sa_RAM_nentA2[0:31][3:0] - sa_RAM_nentA2[0:31][3:0] - - - sa_RAM_nentA3[0:31][3:0] - sa_RAM_nentA3[0:31][3:0] - - - sa_RAM_nentA4[0:31][3:0] - sa_RAM_nentA4[0:31][3:0] - - - sa_RAM_nentA5[0:31][3:0] - sa_RAM_nentA5[0:31][3:0] - - - sa_RAM_nentA6[0:31][3:0] - sa_RAM_nentA6[0:31][3:0] - - - sa_RAM_nentA7[0:31][3:0] - sa_RAM_nentA7[0:31][3:0] - - - addr_nentA[4:0] - addr_nentA[4:0] - - - addr_nentB[4:0] - addr_nentB[4:0] - - - dout_nentA[31:0] - dout_nentA[31:0] - - - ap_done - ap_done - - - ap_start - ap_start - - - ap_done - ap_done - - - ap_done - ap_done - - diff --git a/IntegrationTests/CombinedConfig/IRtoTP/tb/start_bx.wcfg b/IntegrationTests/CombinedConfig/IRtoTP/tb/start_bx.wcfg deleted file mode 100644 index caabab0b4e9..00000000000 --- a/IntegrationTests/CombinedConfig/IRtoTP/tb/start_bx.wcfg +++ /dev/null @@ -1,36 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - clk - clk - - - ap_done - ap_done - - - ap_done - ap_done - - diff --git a/IntegrationTests/CombinedConfig_FPGA2/script/Makefile b/IntegrationTests/CombinedConfig_FPGA2/script/Makefile index fa36d21923e..f4af08f6a03 100644 --- a/IntegrationTests/CombinedConfig_FPGA2/script/Makefile +++ b/IntegrationTests/CombinedConfig_FPGA2/script/Makefile @@ -3,8 +3,9 @@ FIRMWARE=$(shell git rev-parse --show-toplevel) # MODIFY THESE LINES WHEN COPYING AND PASTING THIS MAKEFILE TOP_FUNCS=$(FIRMWARE)/TopFunctions/CombinedConfig_FPGA2 -MODULES=ProjectionCalculator_L1L2ABC ProjectionCalculator_L1L2DE ProjectionCalculator_L1L2F ProjectionCalculator_L1L2G ProjectionCalculator_L1L2HI ProjectionCalculator_L1L2JKL ProjectionCalculator_L2L3ABCD ProjectionCalculator_L3L4AB ProjectionCalculator_L3L4CD ProjectionCalculator_L5L6ABCD ProjectionCalculator_D1D2ABCD ProjectionCalculator_D3D4ABCD ProjectionCalculator_L1D1ABCD ProjectionCalculator_L1D1EFGH ProjectionCalculator_L2D1ABCD MatchProcessor_L1PHIA MatchProcessor_L1PHIB MatchProcessor_L1PHIC MatchProcessor_L1PHID MatchProcessor_L1PHIE MatchProcessor_L1PHIF MatchProcessor_L1PHIG MatchProcessor_L1PHIH MatchProcessor_L2PHIA MatchProcessor_L2PHIB MatchProcessor_L2PHIC MatchProcessor_L2PHID MatchProcessor_L3PHIA MatchProcessor_L3PHIB MatchProcessor_L3PHIC MatchProcessor_L3PHID MatchProcessor_L4PHIA MatchProcessor_L4PHIB MatchProcessor_L4PHIC MatchProcessor_L4PHID MatchProcessor_L5PHIA MatchProcessor_L5PHIB MatchProcessor_L5PHIC MatchProcessor_L5PHID MatchProcessor_L6PHIA MatchProcessor_L6PHIB MatchProcessor_L6PHIC MatchProcessor_L6PHID MatchProcessor_D1PHIA MatchProcessor_D1PHIB MatchProcessor_D1PHIC MatchProcessor_D1PHID MatchProcessor_D2PHIA MatchProcessor_D2PHIB MatchProcessor_D2PHIC MatchProcessor_D2PHID MatchProcessor_D3PHIA MatchProcessor_D3PHIB MatchProcessor_D3PHIC MatchProcessor_D3PHID MatchProcessor_D4PHIA MatchProcessor_D4PHIB MatchProcessor_D4PHIC MatchProcessor_D4PHID MatchProcessor_D5PHIA MatchProcessor_D5PHIB MatchProcessor_D5PHIC MatchProcessor_D5PHID TrackBuilder_L1L2 TrackBuilder_L2L3 TrackBuilder_L3L4 TrackBuilder_L5L6 TrackBuilder_D1D2 TrackBuilder_D3D4 TrackBuilder_L1D1 TrackBuilder_L2D1 VMStubMERouterTop_L1PHIA VMStubMERouterTop_L1PHIB VMStubMERouterTop_L1PHIC VMStubMERouterTop_L1PHID VMStubMERouterTop_L1PHIE VMStubMERouterTop_L1PHIF VMStubMERouterTop_L1PHIG VMStubMERouterTop_L1PHIH VMStubMERouterTop_L2PHIA VMStubMERouterTop_L2PHIB VMStubMERouterTop_L2PHIC VMStubMERouterTop_L2PHID VMStubMERouterTop_L3PHIA VMStubMERouterTop_L3PHIB VMStubMERouterTop_L3PHIC VMStubMERouterTop_L3PHID VMStubMERouterTop_L4PHIA VMStubMERouterTop_L4PHIB VMStubMERouterTop_L4PHIC VMStubMERouterTop_L4PHID VMStubMERouterTop_L5PHIA VMStubMERouterTop_L5PHIB VMStubMERouterTop_L5PHIC VMStubMERouterTop_L5PHID VMStubMERouterTop_L6PHIA VMStubMERouterTop_L6PHIB VMStubMERouterTop_L6PHIC VMStubMERouterTop_L6PHID VMStubMERouterTop_D1PHIA VMStubMERouterTop_D1PHIB VMStubMERouterTop_D1PHIC VMStubMERouterTop_D1PHID VMStubMERouterTop_D2PHIA VMStubMERouterTop_D2PHIB VMStubMERouterTop_D2PHIC VMStubMERouterTop_D2PHID VMStubMERouterTop_D3PHIA VMStubMERouterTop_D3PHIB VMStubMERouterTop_D3PHIC VMStubMERouterTop_D3PHID VMStubMERouterTop_D4PHIA VMStubMERouterTop_D4PHIB VMStubMERouterTop_D4PHIC VMStubMERouterTop_D4PHID VMStubMERouterTop_D5PHIA VMStubMERouterTop_D5PHIB VMStubMERouterTop_D5PHIC VMStubMERouterTop_D5PHID +MODULES=ProjectionCalculator_L1L2ABC ProjectionCalculator_L1L2DE ProjectionCalculator_L1L2F ProjectionCalculator_L1L2G ProjectionCalculator_L1L2HI ProjectionCalculator_L1L2JKL ProjectionCalculator_L2L3ABCD ProjectionCalculator_L3L4AB ProjectionCalculator_L3L4CD ProjectionCalculator_L5L6ABCD ProjectionCalculator_D1D2ABCD ProjectionCalculator_D3D4ABCD ProjectionCalculator_L1D1ABCD ProjectionCalculator_L1D1EFGH ProjectionCalculator_L2D1ABCD MatchProcessor_L1PHIA MatchProcessor_L1PHIB MatchProcessor_L1PHIC MatchProcessor_L1PHID MatchProcessor_L1PHIE MatchProcessor_L1PHIF MatchProcessor_L1PHIG MatchProcessor_L1PHIH MatchProcessor_L2PHIA MatchProcessor_L2PHIB MatchProcessor_L2PHIC MatchProcessor_L2PHID MatchProcessor_L3PHIA MatchProcessor_L3PHIB MatchProcessor_L3PHIC MatchProcessor_L3PHID MatchProcessor_L4PHIA MatchProcessor_L4PHIB MatchProcessor_L4PHIC MatchProcessor_L4PHID MatchProcessor_L5PHIA MatchProcessor_L5PHIB MatchProcessor_L5PHIC MatchProcessor_L5PHID MatchProcessor_L6PHIA MatchProcessor_L6PHIB MatchProcessor_L6PHIC MatchProcessor_L6PHID MatchProcessor_D1PHIA MatchProcessor_D1PHIB MatchProcessor_D1PHIC MatchProcessor_D1PHID MatchProcessor_D2PHIA MatchProcessor_D2PHIB MatchProcessor_D2PHIC MatchProcessor_D2PHID MatchProcessor_D3PHIA MatchProcessor_D3PHIB MatchProcessor_D3PHIC MatchProcessor_D3PHID MatchProcessor_D4PHIA MatchProcessor_D4PHIB MatchProcessor_D4PHIC MatchProcessor_D4PHID MatchProcessor_D5PHIA MatchProcessor_D5PHIB MatchProcessor_D5PHIC MatchProcessor_D5PHID TrackBuilder_AAAA TrackBuilder_BBBB VMStubMERouterTop_L1PHIA VMStubMERouterTop_L1PHIB VMStubMERouterTop_L1PHIC VMStubMERouterTop_L1PHID VMStubMERouterTop_L1PHIE VMStubMERouterTop_L1PHIF VMStubMERouterTop_L1PHIG VMStubMERouterTop_L1PHIH VMStubMERouterTop_L2PHIA VMStubMERouterTop_L2PHIB VMStubMERouterTop_L2PHIC VMStubMERouterTop_L2PHID VMStubMERouterTop_L3PHIA VMStubMERouterTop_L3PHIB VMStubMERouterTop_L3PHIC VMStubMERouterTop_L3PHID VMStubMERouterTop_L4PHIA VMStubMERouterTop_L4PHIB VMStubMERouterTop_L4PHIC VMStubMERouterTop_L4PHID VMStubMERouterTop_L5PHIA VMStubMERouterTop_L5PHIB VMStubMERouterTop_L5PHIC VMStubMERouterTop_L5PHID VMStubMERouterTop_L6PHIA VMStubMERouterTop_L6PHIB VMStubMERouterTop_L6PHIC VMStubMERouterTop_L6PHID VMStubMERouterTop_D1PHIA VMStubMERouterTop_D1PHIB VMStubMERouterTop_D1PHIC VMStubMERouterTop_D1PHID VMStubMERouterTop_D2PHIA VMStubMERouterTop_D2PHIB VMStubMERouterTop_D2PHIC VMStubMERouterTop_D2PHID VMStubMERouterTop_D3PHIA VMStubMERouterTop_D3PHIB VMStubMERouterTop_D3PHIC VMStubMERouterTop_D3PHID VMStubMERouterTop_D4PHIA VMStubMERouterTop_D4PHIB VMStubMERouterTop_D4PHIC VMStubMERouterTop_D4PHID VMStubMERouterTop_D5PHIA VMStubMERouterTop_D5PHIB VMStubMERouterTop_D5PHIC VMStubMERouterTop_D5PHID +#MatchProcessor_L3PHIB_E MatchProcessor_L3PHIC_E MatchProcessor_L4PHIB_E MatchProcessor_L4PHIC_E MatchProcessor_L5PHIB_E MatchProcessor_L5PHIC_E MatchProcessor_L6PHIB_E MatchProcessor_L6PHIC_E MatchProcessor_D3PHIB_E MatchProcessor_D3PHIC_E MatchProcessor_D4PHIB_E MatchProcessor_D4PHIC_E # Include rules for making the project. include $(FIRMWARE)/IntegrationTests/common/script/Makefile.mk diff --git a/IntegrationTests/CombinedConfig_FPGA2/script/floorplan.xdc b/IntegrationTests/CombinedConfig_FPGA2/script/floorplan.xdc index 41d96c73171..f87c34267f7 100644 --- a/IntegrationTests/CombinedConfig_FPGA2/script/floorplan.xdc +++ b/IntegrationTests/CombinedConfig_FPGA2/script/floorplan.xdc @@ -1173,73 +1173,105 @@ resize_pblock [get_pblocks pblock_MPD5B] -add {CLOCKREGION_X2Y4:CLOCKREGION_X6Y7 resize_pblock [get_pblocks pblock_MPD5C] -add {CLOCKREGION_X2Y4:CLOCKREGION_X6Y7} resize_pblock [get_pblocks pblock_MPD5D] -add {CLOCKREGION_X2Y4:CLOCKREGION_X6Y7} -create_pblock pblock_FTL1L2 -add_cells_to_pblock [get_pblocks pblock_FTL1L2] [get_cells -quiet [list \ - FT_L1L2 \ - FM_L1L2_L3PHIA_DELAY \ - FM_L1L2_L3PHIA \ - FM_L1L2_L3PHIB_DELAY \ - FM_L1L2_L3PHIB \ - FM_L1L2_L3PHIC_DELAY \ - FM_L1L2_L3PHIC \ - FM_L1L2_L3PHID_DELAY \ - FM_L1L2_L3PHID \ - FM_L1L2_L4PHIA_DELAY \ - FM_L1L2_L4PHIA \ - FM_L1L2_L4PHIB_DELAY \ - FM_L1L2_L4PHIB \ - FM_L1L2_L4PHIC_DELAY \ - FM_L1L2_L4PHIC \ - FM_L1L2_L4PHID_DELAY \ - FM_L1L2_L4PHID \ - FM_L1L2_L5PHIA_DELAY \ - FM_L1L2_L5PHIA \ - FM_L1L2_L5PHIB_DELAY \ - FM_L1L2_L5PHIB \ - FM_L1L2_L5PHIC_DELAY \ - FM_L1L2_L5PHIC \ - FM_L1L2_L5PHID_DELAY \ - FM_L1L2_L5PHID \ - FM_L1L2_L6PHIA_DELAY \ - FM_L1L2_L6PHIA \ - FM_L1L2_L6PHIB_DELAY \ - FM_L1L2_L6PHIB \ - FM_L1L2_L6PHIC_DELAY \ - FM_L1L2_L6PHIC \ - FM_L1L2_L6PHID_DELAY \ - FM_L1L2_L6PHID \ - FM_L1L2_D1PHIA_DELAY \ - FM_L1L2_D1PHIA \ - FM_L1L2_D1PHIB_DELAY \ - FM_L1L2_D1PHIB \ - FM_L1L2_D1PHIC_DELAY \ - FM_L1L2_D1PHIC \ - FM_L1L2_D1PHID_DELAY \ - FM_L1L2_D1PHID \ - FM_L1L2_D2PHIA_DELAY \ - FM_L1L2_D2PHIA \ - FM_L1L2_D2PHIB_DELAY \ - FM_L1L2_D2PHIB \ - FM_L1L2_D2PHIC_DELAY \ - FM_L1L2_D2PHIC \ - FM_L1L2_D2PHID_DELAY \ - FM_L1L2_D2PHID \ - FM_L1L2_D3PHIA_DELAY \ - FM_L1L2_D3PHIA \ - FM_L1L2_D3PHIB_DELAY \ - FM_L1L2_D3PHIB \ - FM_L1L2_D3PHIC_DELAY \ - FM_L1L2_D3PHIC \ - FM_L1L2_D3PHID_DELAY \ - FM_L1L2_D3PHID \ - FM_L1L2_D4PHIA_DELAY \ - FM_L1L2_D4PHIA \ - FM_L1L2_D4PHIB_DELAY \ - FM_L1L2_D4PHIB \ - FM_L1L2_D4PHIC_DELAY \ - FM_L1L2_D4PHIC \ - FM_L1L2_D4PHID_DELAY \ - FM_L1L2_D4PHID \ +create_pblock pblock_TBAAAA +add_cells_to_pblock [get_pblocks pblock_TBAAAA] [get_cells -quiet [list \ + TB_AAAA \ + FM_AAAA_L1PHIA_DELAY \ + FM_AAAA_L1PHIA \ + FM_AAAA_L1PHIB_DELAY \ + FM_AAAA_L1PHIB \ + FM_AAAA_L1PHIC_DELAY \ + FM_AAAA_L1PHIC \ + FM_AAAA_L1PHID_DELAY \ + FM_AAAA_L1PHID \ + FM_AAAA_L1PHIE_DELAY \ + FM_AAAA_L1PHIE \ + FM_AAAA_L1PHIF_DELAY \ + FM_AAAA_L1PHIF \ + FM_AAAA_L1PHIG_DELAY \ + FM_AAAA_L1PHIG \ + FM_AAAA_L1PHIH_DELAY \ + FM_AAAA_L1PHIH \ + FM_AAAA_L2PHIA_DELAY \ + FM_AAAA_L2PHIA \ + FM_AAAA_L2PHIB_DELAY \ + FM_AAAA_L2PHIB \ + FM_AAAA_L2PHIC_DELAY \ + FM_AAAA_L2PHIC \ + FM_AAAA_L2PHID_DELAY \ + FM_AAAA_L2PHID \ + FM_AAAA_L3PHIA_DELAY \ + FM_AAAA_L3PHIA \ + FM_AAAA_L3PHIB_DELAY \ + FM_AAAA_L3PHIB \ + FM_AAAA_L3PHIC_DELAY \ + FM_AAAA_L3PHIC \ + FM_AAAA_L3PHID_DELAY \ + FM_AAAA_L3PHID \ + FM_AAAA_L4PHIA_DELAY \ + FM_AAAA_L4PHIA \ + FM_AAAA_L4PHIB_DELAY \ + FM_AAAA_L4PHIB \ + FM_AAAA_L4PHIC_DELAY \ + FM_AAAA_L4PHIC \ + FM_AAAA_L4PHID_DELAY \ + FM_AAAA_L4PHID \ + FM_AAAA_L5PHIA_DELAY \ + FM_AAAA_L5PHIA \ + FM_AAAA_L5PHIB_DELAY \ + FM_AAAA_L5PHIB \ + FM_AAAA_L5PHIC_DELAY \ + FM_AAAA_L5PHIC \ + FM_AAAA_L5PHID_DELAY \ + FM_AAAA_L5PHID \ + FM_AAAA_L6PHIA_DELAY \ + FM_AAAA_L6PHIA \ + FM_AAAA_L6PHIB_DELAY \ + FM_AAAA_L6PHIB \ + FM_AAAA_L6PHIC_DELAY \ + FM_AAAA_L6PHIC \ + FM_AAAA_L6PHID_DELAY \ + FM_AAAA_L6PHID \ + FM_AAAA_D1PHIA_DELAY \ + FM_AAAA_D1PHIA \ + FM_AAAA_D1PHIB_DELAY \ + FM_AAAA_D1PHIB \ + FM_AAAA_D1PHIC_DELAY \ + FM_AAAA_D1PHIC \ + FM_AAAA_D1PHID_DELAY \ + FM_AAAA_D1PHID \ + FM_AAAA_D2PHIA_DELAY \ + FM_AAAA_D2PHIA \ + FM_AAAA_D2PHIB_DELAY \ + FM_AAAA_D2PHIB \ + FM_AAAA_D2PHIC_DELAY \ + FM_AAAA_D2PHIC \ + FM_AAAA_D2PHID_DELAY \ + FM_AAAA_D2PHID \ + FM_AAAA_D3PHIA_DELAY \ + FM_AAAA_D3PHIA \ + FM_AAAA_D3PHIB_DELAY \ + FM_AAAA_D3PHIB \ + FM_AAAA_D3PHIC_DELAY \ + FM_AAAA_D3PHIC \ + FM_AAAA_D3PHID_DELAY \ + FM_AAAA_D3PHID \ + FM_AAAA_D4PHIA_DELAY \ + FM_AAAA_D4PHIA \ + FM_AAAA_D4PHIB_DELAY \ + FM_AAAA_D4PHIB \ + FM_AAAA_D4PHIC_DELAY \ + FM_AAAA_D4PHIC \ + FM_AAAA_D4PHID_DELAY \ + FM_AAAA_D4PHID \ + FM_AAAA_D5PHIA_DELAY \ + FM_AAAA_D5PHIA \ + FM_AAAA_D5PHIB_DELAY \ + FM_AAAA_D5PHIB \ + FM_AAAA_D5PHIC_DELAY \ + FM_AAAA_D5PHIC \ + FM_AAAA_D5PHID_DELAY \ + FM_AAAA_D5PHID \ MPAR_L1L2ABC_DELAY \ MPAR_L1L2ABC \ MPAR_L1L2DE_DELAY \ @@ -1252,389 +1284,130 @@ add_cells_to_pblock [get_pblocks pblock_FTL1L2] [get_cells -quiet [list \ MPAR_L1L2HI \ MPAR_L1L2JKL_DELAY \ MPAR_L1L2JKL \ - ]] - -create_pblock pblock_FTL2L3 -add_cells_to_pblock [get_pblocks pblock_FTL2L3] [get_cells -quiet [list \ - FT_L2L3 \ - FM_L2L3_L1PHIA_DELAY \ - FM_L2L3_L1PHIA \ - FM_L2L3_L1PHIB_DELAY \ - FM_L2L3_L1PHIB \ - FM_L2L3_L1PHIC_DELAY \ - FM_L2L3_L1PHIC \ - FM_L2L3_L1PHID_DELAY \ - FM_L2L3_L1PHID \ - FM_L2L3_L1PHIE_DELAY \ - FM_L2L3_L1PHIE \ - FM_L2L3_L1PHIF_DELAY \ - FM_L2L3_L1PHIF \ - FM_L2L3_L1PHIG_DELAY \ - FM_L2L3_L1PHIG \ - FM_L2L3_L1PHIH_DELAY \ - FM_L2L3_L1PHIH \ - FM_L2L3_L4PHIA_DELAY \ - FM_L2L3_L4PHIA \ - FM_L2L3_L4PHIB_DELAY \ - FM_L2L3_L4PHIB \ - FM_L2L3_L4PHIC_DELAY \ - FM_L2L3_L4PHIC \ - FM_L2L3_L4PHID_DELAY \ - FM_L2L3_L4PHID \ - FM_L2L3_L5PHIA_DELAY \ - FM_L2L3_L5PHIA \ - FM_L2L3_L5PHIB_DELAY \ - FM_L2L3_L5PHIB \ - FM_L2L3_L5PHIC_DELAY \ - FM_L2L3_L5PHIC \ - FM_L2L3_L5PHID_DELAY \ - FM_L2L3_L5PHID \ - FM_L2L3_D1PHIA_DELAY \ - FM_L2L3_D1PHIA \ - FM_L2L3_D1PHIB_DELAY \ - FM_L2L3_D1PHIB \ - FM_L2L3_D1PHIC_DELAY \ - FM_L2L3_D1PHIC \ - FM_L2L3_D1PHID_DELAY \ - FM_L2L3_D1PHID \ - FM_L2L3_D2PHIA_DELAY \ - FM_L2L3_D2PHIA \ - FM_L2L3_D2PHIB_DELAY \ - FM_L2L3_D2PHIB \ - FM_L2L3_D2PHIC_DELAY \ - FM_L2L3_D2PHIC \ - FM_L2L3_D2PHID_DELAY \ - FM_L2L3_D2PHID \ - FM_L2L3_D3PHIA_DELAY \ - FM_L2L3_D3PHIA \ - FM_L2L3_D3PHIB_DELAY \ - FM_L2L3_D3PHIB \ - FM_L2L3_D3PHIC_DELAY \ - FM_L2L3_D3PHIC \ - FM_L2L3_D3PHID_DELAY \ - FM_L2L3_D3PHID \ - FM_L2L3_D4PHIA_DELAY \ - FM_L2L3_D4PHIA \ - FM_L2L3_D4PHIB_DELAY \ - FM_L2L3_D4PHIB \ - FM_L2L3_D4PHIC_DELAY \ - FM_L2L3_D4PHIC \ - FM_L2L3_D4PHID_DELAY \ - FM_L2L3_D4PHID \ MPAR_L2L3ABCD_DELAY \ MPAR_L2L3ABCD \ + MPAR_L5L6ABCD_DELAY \ + MPAR_L5L6ABCD \ + MPAR_L2D1ABCD_DELAY \ + MPAR_L2D1ABCD \ ]] - -create_pblock pblock_FTL3L4 -add_cells_to_pblock [get_pblocks pblock_FTL3L4] [get_cells -quiet [list \ - FT_L3L4 \ - FM_L3L4_L1PHIA_DELAY \ - FM_L3L4_L1PHIA \ - FM_L3L4_L1PHIB_DELAY \ - FM_L3L4_L1PHIB \ - FM_L3L4_L1PHIC_DELAY \ - FM_L3L4_L1PHIC \ - FM_L3L4_L1PHID_DELAY \ - FM_L3L4_L1PHID \ - FM_L3L4_L1PHIE_DELAY \ - FM_L3L4_L1PHIE \ - FM_L3L4_L1PHIF_DELAY \ - FM_L3L4_L1PHIF \ - FM_L3L4_L1PHIG_DELAY \ - FM_L3L4_L1PHIG \ - FM_L3L4_L1PHIH_DELAY \ - FM_L3L4_L1PHIH \ - FM_L3L4_L2PHIA_DELAY \ - FM_L3L4_L2PHIA \ - FM_L3L4_L2PHIB_DELAY \ - FM_L3L4_L2PHIB \ - FM_L3L4_L2PHIC_DELAY \ - FM_L3L4_L2PHIC \ - FM_L3L4_L2PHID_DELAY \ - FM_L3L4_L2PHID \ - FM_L3L4_L5PHIA_DELAY \ - FM_L3L4_L5PHIA \ - FM_L3L4_L5PHIB_DELAY \ - FM_L3L4_L5PHIB \ - FM_L3L4_L5PHIC_DELAY \ - FM_L3L4_L5PHIC \ - FM_L3L4_L5PHID_DELAY \ - FM_L3L4_L5PHID \ - FM_L3L4_L6PHIA_DELAY \ - FM_L3L4_L6PHIA \ - FM_L3L4_L6PHIB_DELAY \ - FM_L3L4_L6PHIB \ - FM_L3L4_L6PHIC_DELAY \ - FM_L3L4_L6PHIC \ - FM_L3L4_L6PHID_DELAY \ - FM_L3L4_L6PHID \ - FM_L3L4_D1PHIA_DELAY \ - FM_L3L4_D1PHIA \ - FM_L3L4_D1PHIB_DELAY \ - FM_L3L4_D1PHIB \ - FM_L3L4_D1PHIC_DELAY \ - FM_L3L4_D1PHIC \ - FM_L3L4_D1PHID_DELAY \ - FM_L3L4_D1PHID \ - FM_L3L4_D2PHIA_DELAY \ - FM_L3L4_D2PHIA \ - FM_L3L4_D2PHIB_DELAY \ - FM_L3L4_D2PHIB \ - FM_L3L4_D2PHIC_DELAY \ - FM_L3L4_D2PHIC \ - FM_L3L4_D2PHID_DELAY \ - FM_L3L4_D2PHID \ + +create_pblock pblock_TBBBBB +add_cells_to_pblock [get_pblocks pblock_TBBBBB] [get_cells -quiet [list \ + TB_BBBB \ + FM_BBBB_L1PHIA_DELAY \ + FM_BBBB_L1PHIA \ + FM_BBBB_L1PHIB_DELAY \ + FM_BBBB_L1PHIB \ + FM_BBBB_L1PHIC_DELAY \ + FM_BBBB_L1PHIC \ + FM_BBBB_L1PHID_DELAY \ + FM_BBBB_L1PHID \ + FM_BBBB_L1PHIE_DELAY \ + FM_BBBB_L1PHIE \ + FM_BBBB_L1PHIF_DELAY \ + FM_BBBB_L1PHIF \ + FM_BBBB_L1PHIG_DELAY \ + FM_BBBB_L1PHIG \ + FM_BBBB_L1PHIH_DELAY \ + FM_BBBB_L1PHIH \ + FM_BBBB_L2PHIA_DELAY \ + FM_BBBB_L2PHIA \ + FM_BBBB_L2PHIB_DELAY \ + FM_BBBB_L2PHIB \ + FM_BBBB_L2PHIC_DELAY \ + FM_BBBB_L2PHIC \ + FM_BBBB_L2PHID_DELAY \ + FM_BBBB_L2PHID \ + FM_BBBB_L3PHIA_DELAY \ + FM_BBBB_L3PHIA \ + FM_BBBB_L3PHIB_DELAY \ + FM_BBBB_L3PHIB \ + FM_BBBB_L3PHIC_DELAY \ + FM_BBBB_L3PHIC \ + FM_BBBB_L3PHID_DELAY \ + FM_BBBB_L3PHID \ + FM_BBBB_L4PHIA_DELAY \ + FM_BBBB_L4PHIA \ + FM_BBBB_L4PHIB_DELAY \ + FM_BBBB_L4PHIB \ + FM_BBBB_L4PHIC_DELAY \ + FM_BBBB_L4PHIC \ + FM_BBBB_L4PHID_DELAY \ + FM_BBBB_L4PHID \ + FM_BBBB_L5PHIA_DELAY \ + FM_BBBB_L5PHIA \ + FM_BBBB_L5PHIB_DELAY \ + FM_BBBB_L5PHIB \ + FM_BBBB_L5PHIC_DELAY \ + FM_BBBB_L5PHIC \ + FM_BBBB_L5PHID_DELAY \ + FM_BBBB_L5PHID \ + FM_BBBB_L6PHIA_DELAY \ + FM_BBBB_L6PHIA \ + FM_BBBB_L6PHIB_DELAY \ + FM_BBBB_L6PHIB \ + FM_BBBB_L6PHIC_DELAY \ + FM_BBBB_L6PHIC \ + FM_BBBB_L6PHID_DELAY \ + FM_BBBB_L6PHID \ + FM_BBBB_D1PHIA_DELAY \ + FM_BBBB_D1PHIA \ + FM_BBBB_D1PHIB_DELAY \ + FM_BBBB_D1PHIB \ + FM_BBBB_D1PHIC_DELAY \ + FM_BBBB_D1PHIC \ + FM_BBBB_D1PHID_DELAY \ + FM_BBBB_D1PHID \ + FM_BBBB_D2PHIA_DELAY \ + FM_BBBB_D2PHIA \ + FM_BBBB_D2PHIB_DELAY \ + FM_BBBB_D2PHIB \ + FM_BBBB_D2PHIC_DELAY \ + FM_BBBB_D2PHIC \ + FM_BBBB_D2PHID_DELAY \ + FM_BBBB_D2PHID \ + FM_BBBB_D3PHIA_DELAY \ + FM_BBBB_D3PHIA \ + FM_BBBB_D3PHIB_DELAY \ + FM_BBBB_D3PHIB \ + FM_BBBB_D3PHIC_DELAY \ + FM_BBBB_D3PHIC \ + FM_BBBB_D3PHID_DELAY \ + FM_BBBB_D3PHID \ + FM_BBBB_D4PHIA_DELAY \ + FM_BBBB_D4PHIA \ + FM_BBBB_D4PHIB_DELAY \ + FM_BBBB_D4PHIB \ + FM_BBBB_D4PHIC_DELAY \ + FM_BBBB_D4PHIC \ + FM_BBBB_D4PHID_DELAY \ + FM_BBBB_D4PHID \ + FM_BBBB_D5PHIA_DELAY \ + FM_BBBB_D5PHIA \ + FM_BBBB_D5PHIB_DELAY \ + FM_BBBB_D5PHIB \ + FM_BBBB_D5PHIC_DELAY \ + FM_BBBB_D5PHIC \ + FM_BBBB_D5PHID_DELAY \ + FM_BBBB_D5PHID \ MPAR_L3L4AB_DELAY \ MPAR_L3L4AB \ MPAR_L3L4CD_DELAY \ MPAR_L3L4CD \ - ]] - -create_pblock pblock_FTL5L6 -add_cells_to_pblock [get_pblocks pblock_FTL5L6] [get_cells -quiet [list \ - FT_L5L6 \ - FM_L5L6_L1PHIA_DELAY \ - FM_L5L6_L1PHIA \ - FM_L5L6_L1PHIB_DELAY \ - FM_L5L6_L1PHIB \ - FM_L5L6_L1PHIC_DELAY \ - FM_L5L6_L1PHIC \ - FM_L5L6_L1PHID_DELAY \ - FM_L5L6_L1PHID \ - FM_L5L6_L1PHIE_DELAY \ - FM_L5L6_L1PHIE \ - FM_L5L6_L1PHIF_DELAY \ - FM_L5L6_L1PHIF \ - FM_L5L6_L1PHIG_DELAY \ - FM_L5L6_L1PHIG \ - FM_L5L6_L1PHIH_DELAY \ - FM_L5L6_L1PHIH \ - FM_L5L6_L2PHIA_DELAY \ - FM_L5L6_L2PHIA \ - FM_L5L6_L2PHIB_DELAY \ - FM_L5L6_L2PHIB \ - FM_L5L6_L2PHIC_DELAY \ - FM_L5L6_L2PHIC \ - FM_L5L6_L2PHID_DELAY \ - FM_L5L6_L2PHID \ - FM_L5L6_L3PHIA_DELAY \ - FM_L5L6_L3PHIA \ - FM_L5L6_L3PHIB_DELAY \ - FM_L5L6_L3PHIB \ - FM_L5L6_L3PHIC_DELAY \ - FM_L5L6_L3PHIC \ - FM_L5L6_L3PHID_DELAY \ - FM_L5L6_L3PHID \ - FM_L5L6_L4PHIA_DELAY \ - FM_L5L6_L4PHIA \ - FM_L5L6_L4PHIB_DELAY \ - FM_L5L6_L4PHIB \ - FM_L5L6_L4PHIC_DELAY \ - FM_L5L6_L4PHIC \ - FM_L5L6_L4PHID_DELAY \ - FM_L5L6_L4PHID \ - MPAR_L5L6ABCD_DELAY \ - MPAR_L5L6ABCD \ - ]] - -create_pblock pblock_FTD1D2 -add_cells_to_pblock [get_pblocks pblock_FTD1D2] [get_cells -quiet [list \ - FT_D1D2 \ - FM_D1D2_L1PHIA_DELAY \ - FM_D1D2_L1PHIA \ - FM_D1D2_L1PHIB_DELAY \ - FM_D1D2_L1PHIB \ - FM_D1D2_L1PHIC_DELAY \ - FM_D1D2_L1PHIC \ - FM_D1D2_L1PHID_DELAY \ - FM_D1D2_L1PHID \ - FM_D1D2_L1PHIE_DELAY \ - FM_D1D2_L1PHIE \ - FM_D1D2_L1PHIF_DELAY \ - FM_D1D2_L1PHIF \ - FM_D1D2_L1PHIG_DELAY \ - FM_D1D2_L1PHIG \ - FM_D1D2_L1PHIH_DELAY \ - FM_D1D2_L1PHIH \ - FM_D1D2_L2PHIA_DELAY \ - FM_D1D2_L2PHIA \ - FM_D1D2_L2PHIB_DELAY \ - FM_D1D2_L2PHIB \ - FM_D1D2_L2PHIC_DELAY \ - FM_D1D2_L2PHIC \ - FM_D1D2_L2PHID_DELAY \ - FM_D1D2_L2PHID \ - FM_D1D2_D3PHIA_DELAY \ - FM_D1D2_D3PHIA \ - FM_D1D2_D3PHIB_DELAY \ - FM_D1D2_D3PHIB \ - FM_D1D2_D3PHIC_DELAY \ - FM_D1D2_D3PHIC \ - FM_D1D2_D3PHID_DELAY \ - FM_D1D2_D3PHID \ - FM_D1D2_D4PHIA_DELAY \ - FM_D1D2_D4PHIA \ - FM_D1D2_D4PHIB_DELAY \ - FM_D1D2_D4PHIB \ - FM_D1D2_D4PHIC_DELAY \ - FM_D1D2_D4PHIC \ - FM_D1D2_D4PHID_DELAY \ - FM_D1D2_D4PHID \ - FM_D1D2_D5PHIA_DELAY \ - FM_D1D2_D5PHIA \ - FM_D1D2_D5PHIB_DELAY \ - FM_D1D2_D5PHIB \ - FM_D1D2_D5PHIC_DELAY \ - FM_D1D2_D5PHIC \ - FM_D1D2_D5PHID_DELAY \ - FM_D1D2_D5PHID \ MPAR_D1D2ABCD_DELAY \ MPAR_D1D2ABCD \ - ]] - -create_pblock pblock_FTD3D4 -add_cells_to_pblock [get_pblocks pblock_FTD3D4] [get_cells -quiet [list \ - FT_D3D4 \ - FM_D3D4_L1PHIA_DELAY \ - FM_D3D4_L1PHIA \ - FM_D3D4_L1PHIB_DELAY \ - FM_D3D4_L1PHIB \ - FM_D3D4_L1PHIC_DELAY \ - FM_D3D4_L1PHIC \ - FM_D3D4_L1PHID_DELAY \ - FM_D3D4_L1PHID \ - FM_D3D4_L1PHIE_DELAY \ - FM_D3D4_L1PHIE \ - FM_D3D4_L1PHIF_DELAY \ - FM_D3D4_L1PHIF \ - FM_D3D4_L1PHIG_DELAY \ - FM_D3D4_L1PHIG \ - FM_D3D4_L1PHIH_DELAY \ - FM_D3D4_L1PHIH \ - FM_D3D4_D1PHIA_DELAY \ - FM_D3D4_D1PHIA \ - FM_D3D4_D1PHIB_DELAY \ - FM_D3D4_D1PHIB \ - FM_D3D4_D1PHIC_DELAY \ - FM_D3D4_D1PHIC \ - FM_D3D4_D1PHID_DELAY \ - FM_D3D4_D1PHID \ - FM_D3D4_D2PHIA_DELAY \ - FM_D3D4_D2PHIA \ - FM_D3D4_D2PHIB_DELAY \ - FM_D3D4_D2PHIB \ - FM_D3D4_D2PHIC_DELAY \ - FM_D3D4_D2PHIC \ - FM_D3D4_D2PHID_DELAY \ - FM_D3D4_D2PHID \ - FM_D3D4_D5PHIA_DELAY \ - FM_D3D4_D5PHIA \ - FM_D3D4_D5PHIB_DELAY \ - FM_D3D4_D5PHIB \ - FM_D3D4_D5PHIC_DELAY \ - FM_D3D4_D5PHIC \ - FM_D3D4_D5PHID_DELAY \ - FM_D3D4_D5PHID \ MPAR_D3D4ABCD_DELAY \ MPAR_D3D4ABCD \ + MPAR_L1D1AB_DELAY \ + MPAR_L1D1AB \ + MPAR_L1D1CD_DELAY \ + MPAR_L1D1CD \ ]] -create_pblock pblock_FTL1D1 -add_cells_to_pblock [get_pblocks pblock_FTL1D1] [get_cells -quiet [list \ - FT_L1D1 \ - FM_L1D1_D2PHIA_DELAY \ - FM_L1D1_D2PHIA \ - FM_L1D1_D2PHIB_DELAY \ - FM_L1D1_D2PHIB \ - FM_L1D1_D2PHIC_DELAY \ - FM_L1D1_D2PHIC \ - FM_L1D1_D2PHID_DELAY \ - FM_L1D1_D2PHID \ - FM_L1D1_D3PHIA_DELAY \ - FM_L1D1_D3PHIA \ - FM_L1D1_D3PHIB_DELAY \ - FM_L1D1_D3PHIB \ - FM_L1D1_D3PHIC_DELAY \ - FM_L1D1_D3PHIC \ - FM_L1D1_D3PHID_DELAY \ - FM_L1D1_D3PHID \ - FM_L1D1_D4PHIA_DELAY \ - FM_L1D1_D4PHIA \ - FM_L1D1_D4PHIB_DELAY \ - FM_L1D1_D4PHIB \ - FM_L1D1_D4PHIC_DELAY \ - FM_L1D1_D4PHIC \ - FM_L1D1_D4PHID_DELAY \ - FM_L1D1_D4PHID \ - FM_L1D1_D5PHIA_DELAY \ - FM_L1D1_D5PHIA \ - FM_L1D1_D5PHIB_DELAY \ - FM_L1D1_D5PHIB \ - FM_L1D1_D5PHIC_DELAY \ - FM_L1D1_D5PHIC \ - FM_L1D1_D5PHID_DELAY \ - FM_L1D1_D5PHID \ - MPAR_L1D1ABCD_DELAY \ - MPAR_L1D1ABCD \ - MPAR_L1D1EFGH_DELAY \ - MPAR_L1D1EFGH \ - ]] - -create_pblock pblock_FTL2D1 -add_cells_to_pblock [get_pblocks pblock_FTL2D1] [get_cells -quiet [list \ - FT_L2D1 \ - FM_L2D1_L1PHIA_DELAY \ - FM_L2D1_L1PHIA \ - FM_L2D1_L1PHIB_DELAY \ - FM_L2D1_L1PHIB \ - FM_L2D1_L1PHIC_DELAY \ - FM_L2D1_L1PHIC \ - FM_L2D1_L1PHID_DELAY \ - FM_L2D1_L1PHID \ - FM_L2D1_L1PHIE_DELAY \ - FM_L2D1_L1PHIE \ - FM_L2D1_L1PHIF_DELAY \ - FM_L2D1_L1PHIF \ - FM_L2D1_L1PHIG_DELAY \ - FM_L2D1_L1PHIG \ - FM_L2D1_L1PHIH_DELAY \ - FM_L2D1_L1PHIH \ - FM_L2D1_D2PHIA_DELAY \ - FM_L2D1_D2PHIA \ - FM_L2D1_D2PHIB_DELAY \ - FM_L2D1_D2PHIB \ - FM_L2D1_D2PHIC_DELAY \ - FM_L2D1_D2PHIC \ - FM_L2D1_D2PHID_DELAY \ - FM_L2D1_D2PHID \ - FM_L2D1_D3PHIA_DELAY \ - FM_L2D1_D3PHIA \ - FM_L2D1_D3PHIB_DELAY \ - FM_L2D1_D3PHIB \ - FM_L2D1_D3PHIC_DELAY \ - FM_L2D1_D3PHIC \ - FM_L2D1_D3PHID_DELAY \ - FM_L2D1_D3PHID \ - FM_L2D1_D4PHIA_DELAY \ - FM_L2D1_D4PHIA \ - FM_L2D1_D4PHIB_DELAY \ - FM_L2D1_D4PHIB \ - FM_L2D1_D4PHIC_DELAY \ - FM_L2D1_D4PHIC \ - FM_L2D1_D4PHID_DELAY \ - FM_L2D1_D4PHID \ - MPAR_L2D1ABCD_DELAY \ - MPAR_L2D1ABCD \ - ]] - -resize_pblock [get_pblocks pblock_FTL2L3] -add {CLOCKREGION_X1Y0:CLOCKREGION_X2Y3} -resize_pblock [get_pblocks pblock_FTL3L4] -add {CLOCKREGION_X1Y0:CLOCKREGION_X2Y3} -resize_pblock [get_pblocks pblock_FTL5L6] -add {CLOCKREGION_X1Y0:CLOCKREGION_X2Y3} -resize_pblock [get_pblocks pblock_FTL1D1] -add {CLOCKREGION_X1Y0:CLOCKREGION_X2Y3} -resize_pblock [get_pblocks pblock_FTL1L2] -add {CLOCKREGION_X1Y4:CLOCKREGION_X2Y7} -resize_pblock [get_pblocks pblock_FTD1D2] -add {CLOCKREGION_X1Y4:CLOCKREGION_X2Y7} -resize_pblock [get_pblocks pblock_FTD3D4] -add {CLOCKREGION_X1Y4:CLOCKREGION_X2Y7} -resize_pblock [get_pblocks pblock_FTL2D1] -add {CLOCKREGION_X1Y4:CLOCKREGION_X2Y7} + +resize_pblock [get_pblocks pblock_TBAAAA] -add {CLOCKREGION_X1Y0:CLOCKREGION_X2Y7} +resize_pblock [get_pblocks pblock_TBBBBB] -add {CLOCKREGION_X1Y0:CLOCKREGION_X2Y7} set_property IS_SOFT FALSE [get_pblocks pblock_*] diff --git a/IntegrationTests/CombinedConfig_FPGA2/script/makeProject.tcl b/IntegrationTests/CombinedConfig_FPGA2/script/makeProject.tcl index 43cbea626c7..e464a4c02e0 100644 --- a/IntegrationTests/CombinedConfig_FPGA2/script/makeProject.tcl +++ b/IntegrationTests/CombinedConfig_FPGA2/script/makeProject.tcl @@ -124,15 +124,20 @@ create_ip -name MatchProcessor_D5PHIA -module_name MP_D5PHIA -vendor xilinx.com create_ip -name MatchProcessor_D5PHIB -module_name MP_D5PHIB -vendor xilinx.com -library hls -version 1.0 create_ip -name MatchProcessor_D5PHIC -module_name MP_D5PHIC -vendor xilinx.com -library hls -version 1.0 create_ip -name MatchProcessor_D5PHID -module_name MP_D5PHID -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackBuilder_L1L2 -module_name FT_L1L2 -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackBuilder_L2L3 -module_name FT_L2L3 -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackBuilder_L3L4 -module_name FT_L3L4 -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackBuilder_L5L6 -module_name FT_L5L6 -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackBuilder_D1D2 -module_name FT_D1D2 -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackBuilder_D3D4 -module_name FT_D3D4 -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackBuilder_L1D1 -module_name FT_L1D1 -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackBuilder_L2D1 -module_name FT_L2D1 -vendor xilinx.com -library hls -version 1.0 - +#create_ip -name MatchProcessor_L3PHIB_E -module_name MP_L3PHIB_E -vendor xilinx.com -library hls -version 1.0 +#create_ip -name MatchProcessor_L3PHIC_E -module_name MP_L3PHIC_E -vendor xilinx.com -library hls -version 1.0 +#create_ip -name MatchProcessor_L4PHIB_E -module_name MP_L4PHIB_E -vendor xilinx.com -library hls -version 1.0 +#create_ip -name MatchProcessor_L4PHIC_E -module_name MP_L4PHIC_E -vendor xilinx.com -library hls -version 1.0 +#create_ip -name MatchProcessor_L5PHIB_E -module_name MP_L5PHIB_E -vendor xilinx.com -library hls -version 1.0 +#create_ip -name MatchProcessor_L5PHIC_E -module_name MP_L5PHIC_E -vendor xilinx.com -library hls -version 1.0 +#create_ip -name MatchProcessor_L6PHIB_E -module_name MP_L6PHIB_E -vendor xilinx.com -library hls -version 1.0 +#create_ip -name MatchProcessor_L6PHIC_E -module_name MP_L6PHIC_E -vendor xilinx.com -library hls -version 1.0 +#create_ip -name MatchProcessor_D3PHIB_E -module_name MP_D3PHIB_E -vendor xilinx.com -library hls -version 1.0 +#create_ip -name MatchProcessor_D3PHIC_E -module_name MP_D3PHIC_E -vendor xilinx.com -library hls -version 1.0 +#create_ip -name MatchProcessor_D4PHIB_E -module_name MP_D4PHIB_E -vendor xilinx.com -library hls -version 1.0 +#create_ip -name MatchProcessor_D4PHIC_E -module_name MP_D4PHIC_E -vendor xilinx.com -library hls -version 1.0 +create_ip -name TrackBuilder_AAAA -module_name TB_AAAA -vendor xilinx.com -library hls -version 1.0 +create_ip -name TrackBuilder_BBBB -module_name TB_BBBB -vendor xilinx.com -library hls -version 1.0 # Provide name of top-level HDL (without .vhd extension). #set topLevelHDL "SectorProcessor" diff --git a/IntegrationTests/CombinedConfig_FPGA2/script/runSim.tcl b/IntegrationTests/CombinedConfig_FPGA2/script/runSim.tcl index 817858524b1..d63c52f28ff 100644 --- a/IntegrationTests/CombinedConfig_FPGA2/script/runSim.tcl +++ b/IntegrationTests/CombinedConfig_FPGA2/script/runSim.tcl @@ -16,4 +16,4 @@ open_wave_config {../tb/start_bx.wcfg} restart # Need 4us + 0.45us per event (50us for 100 events, but 10us for quick test). -run 2.5 us +run 50 us diff --git a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/Makefile b/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/Makefile deleted file mode 100644 index 6fbec263cac..00000000000 --- a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/Makefile +++ /dev/null @@ -1,53 +0,0 @@ -core_file = scripts/xciMaker -core_dir = cgn -input_file = mem/in.txt -proj_path = ../../../../proj -hls_script_path = ../../script - -all: add_common_files $(core_file) hdl_add_files xciCreation kfin_adj $(input_file) apollo_input - -$(core_dir): - @mkdir cgn mem - make -C $(hls_script_path) -j 8 Work - ln -s ../../../../../emData/LUTsCMReduced mem/LUTs - ln -s ../../../../../emData/MemPrintsReducedCM mem/MemPrintsReducedCM - ln -s ../../../../common hdl/common - -$(core_file): $(core_dir) - @python3 scripts/include_cores.py -s $(hls_script_path) - -kfin_adj: - @cd ../../../../KalmanFilter; git checkout d0d3ba5 - @python3 scripts/kf_link_mod.py - -xciCreation: $(core_file) - make -f $(core_file) -j 8 all - -add_common_files: - @cd cfg; ln -s ../../../../common/cfg/*.dep . - @cd ucf; ln -s ../../../../common/ucf/*.tcl . - @cd scripts; ln -s ../../../../common/script/emp/*.py . - @cd scripts; ln -s ../../../../common/script/emp/*.tcl . - -hdl_add_files: $(core_file) - cd hdl; ln -s ../../../hdl/*.vhd . - -$(input_file): $(core_dir) - @python3 scripts/convert_emData2EMP_Link.py -d mem/MemPrintsReducedCM/InputStubs -o $(input_file) - -apollo_input: $(input_file) - @python3 scripts/split_emp_input.py - -sim: $(input_file) $(core_file) $(core_dir) - @ln -s $(proj_path)/vsim/vsim/vsim.sim/sim_1/behav/xsim/out.txt mem/out.txt - @$(eval CORE_DIRS= $(wildcard $(core_dir)/*)) - @$(foreach core_dir,$(CORE_DIRS),ln -s ../../../../firmware/$(core_dir) $(hls_script_path);) - @ln -s ../../../common $(hls_script_path) - @ln -s ../../../../emData/MemPrintsReducedCM $(hls_script_path)/MemPrints - @ln -s ../../../../emData/LUTsCMReduced $(hls_script_path)/LUTs - @$(eval CORE_DIRS= $(wildcard $(core_dir)/*)) - @cd $(hls_script_path); vivado -mode batch -source makeProject.tcl - @cd $(hls_script_path); vivado -mode batch -source runSim.tcl - @python3 scripts/fwtosim_comparison.py -e mem/out.txt -s $(hls_script_path)/dataOut/TF_L1L2.txt - -.PHONY: sim all hdl_add_files xciCreation kfin_adj apollo_input core_patch diff --git a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/cfg/apollo.dep b/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/cfg/apollo.dep deleted file mode 100644 index 952aa677ae6..00000000000 --- a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/cfg/apollo.dep +++ /dev/null @@ -1,13 +0,0 @@ -include payload.dep -src emp_project_decl.vhd -setup ../ucf/ip.tcl -#src ../scripts/pre_synth.tcl -#setup ../ucf/misc_synth.tcl - -src -c emp-fwk:components/datapath emp_data_types.vhd -src -c ipbus-firmware:components/ipbus_slaves ipbus_reg_v.vhd ipbus_ctrlreg_v.vhd ipbus_reg_types.vhd -src -c ipbus-firmware:components/ipbus_core ipbus_fabric_sel.vhd ipbus_package.vhd - - -addrtab -c emp-fwk:components/payload emp_payload.xml -include -c emp-fwk:boards/apollo/cm_v2/vu13p cm_v2.dep diff --git a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/hdl/emp_project_decl.vhd b/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/hdl/emp_project_decl.vhd deleted file mode 100644 index cdc8e0e1329..00000000000 --- a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/hdl/emp_project_decl.vhd +++ /dev/null @@ -1,69 +0,0 @@ - -library IEEE; -use IEEE.STD_LOGIC_1164.all; - -use work.emp_framework_decl.all; -use work.emp_device_types.all; -use work.emp_slink_types.all; - -package emp_project_decl is - - constant PAYLOAD_REV : std_logic_vector(31 downto 0) := X"12345678"; - - -- Latency buffer size - constant LB_ADDR_WIDTH : integer := 10; - - -- Clock setup - constant CLOCK_COMMON_RATIO : integer := 36; - constant CLOCK_RATIO : integer := 6; - constant CLOCK_AUX_DIV : clock_divisor_array_t := (18, 9, 4); -- Dividers of CLOCK_COMMON_RATIO * 40 MHz - - -- Only used by nullalgo - --constant PAYLOAD_LATENCY : integer := 805; - constant PAYLOAD_LATENCY : integer := 823; - - constant REGION_CONF : region_conf_array_t := ( - 0 => kDummyRegion, --service/c2c - 1 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), - 2 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), - 3 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), - 4 => kDummyRegion, --not routed - 5 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), - 6 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), - 7 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), - 8 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), - 9 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), - 10 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), - 11 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), - 12 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), - 13 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), - 14 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), - 15 => kDummyRegion, --not routed - ------cross - 16 => kDummyRegion, --not routed - 17 => (gty25, buf, no_fmt, no_buf, no_mgt), - 18 => (gty25, buf, no_fmt, no_buf, no_mgt), - 19 => (gty25, buf, no_fmt, no_buf, no_mgt), - 20 => kDummyRegion, --not routed - 21 => (gty25, buf, no_fmt, no_buf, no_mgt), - 22 => (gty25, buf, no_fmt, no_buf, no_mgt), - 23 => (gty25, buf, no_fmt, no_buf, no_mgt), - 24 => (gty25, buf, no_fmt, no_buf, no_mgt), - 25 => (gty25, buf, no_fmt, no_buf, no_mgt), - 26 => (gty25, buf, no_fmt, no_buf, no_mgt), - 27 => (no_mgt, no_buf, no_fmt, buf, gty25), - 28 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), - 29 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), - 30 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), - 31 => kDummyRegion, --service/tcds - others => kDummyRegion - ); - - -- Specify the slink quad using the corresponding region conf ID - -- Specify slink channels to enable using the channel mask - constant SLINK_CONF : slink_conf_array_t := ( - others => kNoSlink - ); - - -end emp_project_decl; diff --git a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/hdl/kf_wrapper.vhd b/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/hdl/kf_wrapper.vhd deleted file mode 100644 index 9cbe3756eba..00000000000 --- a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/hdl/kf_wrapper.vhd +++ /dev/null @@ -1,64 +0,0 @@ -------------------------------------------------------------------------------- --- Title : kf wrapper --- Project : -------------------------------------------------------------------------------- --- File : kf_top.vhd --- Author : Filippo Marini --- Company : University of Colorado Boulder --- Created : 2022-11-04 --- Last update: 2023-02-24 --- Platform : --- Standard : VHDL'93/02 -------------------------------------------------------------------------------- --- Description: -------------------------------------------------------------------------------- --- Copyright (c) 2022 University of Colorado Boulder -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2022-11-04 1.0 fmarini Created -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; - -use work.hybrid_data_formats.all; -use work.hybrid_config.all; -use work.hybrid_data_types.all; - -entity kf_wrapper is - port ( - clk_i : in std_logic; - kfin_i : in t_channlesTB(numSeedTypes - 1 downto 0); - kfout_o : out t_frames(numLinksTFP - 1 downto 0) - ); -end entity kf_wrapper; - -architecture rtl of kf_wrapper is - - signal s_kfin_dout : t_channelsZHT(numSeedTypes - 1 downto 0); - signal s_kf_dout : t_channelsKF(numNodesKF - 1 downto 0); - -begin -- architecture rtl - - kfin_top_1 : entity work.kfin_top - port map ( - clk => clk_i, - kfin_din => kfin_i, - kfin_dout => s_kfin_dout - ); - - kf_top_1 : entity work.kf_top - port map ( - clk => clk_i, - kf_din => s_kfin_dout, - kf_dout => s_kf_dout - ); - - kfout_top_1 : entity work.kfout_top_conv - port map ( - clk => clk_i, - kfout_din => s_kf_dout, - kfout_dout => kfout_o - ); - -end architecture rtl; diff --git a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/hdl/linktosecproc.vhd b/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/hdl/linktosecproc.vhd deleted file mode 100644 index 008ca2f34b3..00000000000 --- a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/hdl/linktosecproc.vhd +++ /dev/null @@ -1,137 +0,0 @@ -------------------------------------------------------------------------------- --- Title : link to sector processor --- Project : -------------------------------------------------------------------------------- --- File : linktosecproc.vhd --- Author : Filippo Marini --- Company : University of Colorado Boulder --- Created : 2022-06-27 --- Last update: 2023-04-06 --- Platform : --- Standard : VHDL'93/02 -------------------------------------------------------------------------------- --- Description: -------------------------------------------------------------------------------- --- Copyright (c) 2022 University of Colorado Boulder -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2022-06-27 1.0 fmarini Created -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use work.emp_data_types.all; -use work.emp_device_decl.all; -use work.emp_ttc_decl.all; --- emp thomas --- use work.hybrid_tools.all; --- use work.hybrid_config.all; --- use work.hybrid_data_types.all; --- use work.tracklet_config.all; --- use work.tracklet_data_types.all; --- emp US -use work.tf_pkg.all; -use work.memUtil_pkg.all; -use work.memUtil_aux_pkg.all; - -entity linktosecproc is - port ( - clk_i : in std_logic; - rst_i : in std_logic; - ttc_i : in ttc_stuff_array(N_REGION - 1 downto 0); - din_i : in ldata(4 * N_REGION - 1 downto 0); - ir_start_o : out std_logic; - bx_o : out std_logic_vector(2 downto 0); - DL_39_link_AV_dout : out t_arr_DL_39_DATA; - DL_39_link_empty_neg : out t_arr_DL_39_1b; - DL_39_link_read : in t_arr_DL_39_1b - ); -end entity linktosecproc; - -architecture rtl of linktosecproc is - - -- signal s_tracklet_reset : t_resets(numPPquads - 1 downto 0); - -- signal s_tracklet_isol : t_stubsDTC; - -- signal s_tracklet_data : t_datas(numInputsIR - 1 downto 0); - signal s_ir_start : std_logic; - signal s_ir_start_srff : std_logic; - signal s_din_d : ldata(4 * N_REGION - 1 downto 0); - signal s_din_dd : ldata(4 * N_REGION - 1 downto 0); - -begin -- architecture rtl - - -- tracklet_isolation_in_1 : entity work.tracklet_isolation_in - -- port map ( - -- clk => clk_i, - -- in_ttc => ttc_i, - -- in_din => din_i, - -- in_reset => s_tracklet_reset, - -- in_dout => s_tracklet_isol - -- ); - - -- tracklet_format_in_1 : entity work.tracklet_format_in - -- port map ( - -- clk => clk_i, - -- in_reset => s_tracklet_reset, - -- in_din => s_tracklet_isol, - -- in_dout => s_tracklet_data - -- ); - - GEN_DELAYED_DATA: for i in 68 to 76 generate - p_delay_data: process (clk_i) is - begin -- process p_delay_data - if rising_edge(clk_i) then -- rising clock edge - s_din_d(i).data <= din_i(i).data; - s_din_dd(i).data <= s_din_d(i).data; - s_din_d(i).valid <= din_i(i).valid; - end if; - end process p_delay_data; - end generate GEN_DELAYED_DATA; - - ----------------------------------------------------------------------------- - -- Connect input link data to IR in Sector Processor - ----------------------------------------------------------------------------- - DL_39_link_AV_DOUT(PS10G_1_A) <= s_din_dd(68).data(38 downto 0); - DL_39_link_AV_DOUT(PS10G_2_A) <= s_din_dd(69).data(38 downto 0); - DL_39_link_AV_DOUT(PS10G_3_A) <= s_din_dd(70).data(38 downto 0); - DL_39_link_AV_DOUT(PS_1_A) <= s_din_dd(71).data(38 downto 0); - DL_39_link_AV_DOUT(PS_2_A) <= s_din_dd(72).data(38 downto 0); - DL_39_link_AV_DOUT(twoS_1_A) <= s_din_dd(73).data(38 downto 0); - DL_39_link_AV_DOUT(twoS_2_A) <= s_din_dd(74).data(38 downto 0); - DL_39_link_AV_DOUT(twoS_3_A) <= s_din_dd(75).data(38 downto 0); - DL_39_link_AV_DOUT(twoS_4_A) <= s_din_dd(76).data(38 downto 0); - - ----------------------------------------------------------------------------- - -- Generate start signal - ----------------------------------------------------------------------------- - set_reset_ffd_1 : entity work.set_reset_ffd - port map ( - clk_i => clk_i, - set_i => s_din_d(68).valid, - reset_i => rst_i, - q_o => s_ir_start_srff - ); - - - s_ir_start <= s_din_d(68).valid or s_ir_start_srff; - ir_start_o <= s_ir_start; - - p_bx_count : process (clk_i) is - variable v_bx : natural; - variable v_word_count : natural := 1; - begin -- process p_bx_count - if rising_edge(clk_i) then -- rising clock edge - if s_ir_start = '1' then - if v_word_count < MAX_ENTRIES then - v_word_count := v_word_count + 1; - else - v_word_count := 1; - v_bx := v_bx + 1; - end if; - end if; - bx_o <= std_logic_vector(to_unsigned(v_bx, bx_o'length)); - end if; - end process p_bx_count; - -end architecture rtl; diff --git a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/hdl/payload.vhd b/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/hdl/payload.vhd deleted file mode 100644 index 624bae3835f..00000000000 --- a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/hdl/payload.vhd +++ /dev/null @@ -1,179 +0,0 @@ -------------------------------------------------------------------------------- --- Title : payload --- Project : -------------------------------------------------------------------------------- --- File : payload.vhd --- Author : Filippo Marini --- Company : University of Colorado Boulder --- Created : 2022-06-21 --- Last update: 2023-06-02 --- Platform : --- Standard : VHDL'93/02 -------------------------------------------------------------------------------- --- Description: -------------------------------------------------------------------------------- --- Copyright (c) 2022 University of Colorado Boulder -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2022-06-21 1.0 fmarini Created -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use work.ipbus.all; -use work.emp_data_types.all; -use work.emp_device_decl.all; -use work.emp_ttc_decl.all; -use work.emp_slink_types.all; --- tf -use work.tf_pkg.all; -use work.memUtil_pkg.all; -use work.memUtil_aux_pkg.all; -use work.tf_interface_pkg.all; -use work.hybrid_data_types.all; -use work.hybrid_config.all; -use work.hybrid_data_formats.all; - -entity emp_payload is - port ( - clk : in std_logic; --unused - rst : in std_logic; - ipb_in : in ipb_wbus; --unused - clk40 : in std_logic; --unused - clk_payload : in std_logic_vector(2 downto 0); - rst_payload : in std_logic_vector(2 downto 0); --unused - clk_p : in std_logic; - rst_loc : in std_logic_vector(N_REGION - 1 downto 0); --unused - clken_loc : in std_logic_vector(N_REGION - 1 downto 0); --unused - ctrs : in ttc_stuff_array(N_REGION - 1 downto 0); --in linktosecproc, but unused - d : in ldata(4 * N_REGION - 1 downto 0); - ipb_out : out ipb_rbus; --unused - bc0 : out std_logic; --unused - q : out ldata(4 * N_REGION - 1 downto 0); - gpio : out std_logic_vector(29 downto 0); --unused - gpio_en : out std_logic_vector(29 downto 0); --unused - slink_q : out slink_input_data_quad_array(SLINK_MAX_QUADS - 1 downto 0); --unused - backpressure : in std_logic_vector(SLINK_MAX_QUADS - 1 downto 0) --unused - ); -end; - -architecture rtl of emp_payload is - - signal s_IR_data : t_arr_DL_39_DATA; - signal s_ir_start : std_logic; - signal s_bx : std_logic_vector(2 downto 0); - signal s_TW_104_stream_data : t_arr_TW_104_DATA; - signal s_TW_104_stream_valid : t_arr_TW_104_1b; - signal s_BW_46_stream_data : t_arr_BW_46_DATA; - signal s_BW_46_stream_valid : t_arr_BW_46_1b; - signal s_FT_bx_out_vld : std_logic; - signal s_tftokf : t_channlesTB(numTW_104 - 1 downto 0); - signal s_kfout : t_frames(numLinksTFP - 1 downto 0); - signal s_tfout : ldata(numLinksTFP - 1 downto 0); - -begin -- architecture rtl - - ----------------------------------------------------------------------------- - -- EMP ports - ----------------------------------------------------------------------------- - slink_q <= (others => SLINK_INPUT_DATA_ARRAY_NULL); - gpio <= (others => '0'); - gpio_en <= (others => '0'); - ipb_out <= IPB_RBUS_NULL; - bc0 <= '0'; - - ----------------------------------------------------------------------------- - -- Link to Sector Processor formatter - ----------------------------------------------------------------------------- - linktosecproc_1 : entity work.linktosecproc - port map ( - clk_i => clk_p, - rst_i => rst, - ttc_i => ctrs, - din_i => d, - ir_start_o => s_ir_start, - bx_o => s_bx, - DL_39_link_AV_dout => s_IR_data, - DL_39_link_empty_neg => open, - DL_39_link_read => (others => '0') - ); - - ----------------------------------------------------------------------------- - -- Sector Processor - ----------------------------------------------------------------------------- - tf_wrapper_1 : entity work.tf_wrapper - port map ( - clk => clk_p, - reset => rst, - IR_start => s_ir_start, - IR_bx_in => s_bx, - FT_bx_out => open, - FT_bx_out_vld => s_FT_bx_out_vld, - FT_done => open, - DL_39_link_AV_dout => s_IR_data, - DL_39_link_empty_neg => (others => '1'), - DL_39_link_read => open, - TW_104_stream_AV_din => s_TW_104_stream_data, - TW_104_stream_A_full_neg => (others => '1'), - TW_104_stream_A_write => s_TW_104_stream_valid, - BW_46_stream_AV_din => s_BW_46_stream_data, - BW_46_stream_A_full_neg => (others => '1'), - BW_46_stream_A_write => s_BW_46_stream_valid - ); - - ----------------------------------------------------------------------------- - -- Sector Processor to Link formatter - ----------------------------------------------------------------------------- - -- secproctolink_1 : entity work.secproctolink - -- port map ( - -- clk_i => clk_p, - -- TW_104_stream_data_i => s_TW_104_stream_data, - -- TW_104_stream_write_i => s_TW_104_stream_valid, - -- TW_104_stream_full_neg_o => open, - -- BW_46_stream_data_i => s_BW_46_stream_data, - -- BW_46_stream_write_i => s_BW_46_stream_valid, - -- BW_46_stream_full_neg_i => open, - -- dout_o => q - -- ); - - ----------------------------------------------------------------------------- - -- Sector Processor to KF formatter - ----------------------------------------------------------------------------- - tf_to_kf_1 : entity work.tf_to_kf - port map ( - clk_i => clk_p, - TW_104_data_i => s_TW_104_stream_data, - TW_104_valid_i => s_TW_104_stream_valid, - BW_46_data_i => s_BW_46_stream_data, - BW_46_valid_i => s_BW_46_stream_valid, - kf_reset_i => s_FT_bx_out_vld, - tftokf_o => s_tftokf - ); - - ----------------------------------------------------------------------------- - -- KF - ----------------------------------------------------------------------------- - kf_wrapper_1 : entity work.kf_wrapper - port map ( - clk_i => clk_p, - kfin_i => s_tftokf, - kfout_o => s_kfout - ); - - ----------------------------------------------------------------------------- - -- Output step - ----------------------------------------------------------------------------- - kfout_isolation_out_1 : entity work.kfout_isolation_out - port map ( - clk => clk_p, - out_packet => conv(d), - out_din => s_kfout, - out_dout => s_tfout - ); - - q(108) <= s_tfout(0); - q(109) <= s_tfout(1); - --q(120).strobe <= '1'; - --q(121).strobe <= '1'; - -end architecture rtl; diff --git a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/hdl/tf_wrapper.vhd b/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/hdl/tf_wrapper.vhd deleted file mode 100644 index ce1fc1e8f7c..00000000000 --- a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/hdl/tf_wrapper.vhd +++ /dev/null @@ -1,107 +0,0 @@ -------------------------------------------------------------------------------- --- Title : tf wrapper --- Project : -------------------------------------------------------------------------------- --- File : tf_wrapper.vhd --- Author : Michael Oshiro --- Company : Cornell University --- Created : 2024-01-19 --- Last update: 2024-01-19 --- Platform : --- Standard : VHDL'93/02 -------------------------------------------------------------------------------- --- Description: Simple module to pack/unpack SectorProcessor inputs into vectors -------------------------------------------------------------------------------- --- Copyright (c) 2024 Cornell University -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2022-01-19 1.0 oshiro Created -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; - -use work.memUtil_pkg.all; -use work.memUtil_aux_pkg.all; - -entity tf_wrapper is - port ( - clk : in std_logic; - reset : in std_logic; - IR_start : in std_logic; - IR_bx_in : in std_logic_vector(2 downto 0); - FT_bx_out : out std_logic_vector(2 downto 0); - FT_bx_out_vld : out std_logic; - FT_done : out std_logic; - DL_39_link_AV_dout : in t_arr_DL_39_DATA; - DL_39_link_empty_neg : in t_arr_DL_39_1b; - DL_39_link_read : out t_arr_DL_39_1b; - TW_104_stream_AV_din : out t_arr_TW_104_DATA; - TW_104_stream_A_full_neg : in t_arr_TW_104_1b; - TW_104_stream_A_write : out t_arr_TW_104_1b; - BW_46_stream_AV_din : out t_arr_BW_46_DATA; - BW_46_stream_A_full_neg : in t_arr_BW_46_1b; - BW_46_stream_A_write : out t_arr_BW_46_1b - ); -end entity tf_wrapper; - -architecture rtl of tf_wrapper is - -begin -- architecture rtl - - SectorProcessor_1 : entity work.SectorProcessor - port map ( - clk => clk, - reset => reset, - IR_start => IR_start, - IR_bx_in => IR_bx_in, - FT_bx_out_0 => FT_bx_out, - FT_bx_out_vld => FT_bx_out_vld, - FT_done => FT_done, - FT_L1L2_last_track => open, - FT_L1L2_last_track_vld => open, - DL_PS10G_1_A_link_AV_dout => DL_39_link_AV_dout(PS10G_1_A), - DL_PS10G_1_A_link_empty_neg => DL_39_link_empty_neg(PS10G_1_A), - DL_PS10G_1_A_link_read => DL_39_link_read(PS10G_1_A), - DL_PS10G_2_A_link_AV_dout => DL_39_link_AV_dout(PS10G_2_A), - DL_PS10G_2_A_link_empty_neg => DL_39_link_empty_neg(PS10G_2_A), - DL_PS10G_2_A_link_read => DL_39_link_read(PS10G_2_A), - DL_PS10G_3_A_link_AV_dout => DL_39_link_AV_dout(PS10G_3_A), - DL_PS10G_3_A_link_empty_neg => DL_39_link_empty_neg(PS10G_3_A), - DL_PS10G_3_A_link_read => DL_39_link_read(PS10G_3_A), - DL_PS_1_A_link_AV_dout => DL_39_link_AV_dout(PS_1_A), - DL_PS_1_A_link_empty_neg => DL_39_link_empty_neg(PS_1_A), - DL_PS_1_A_link_read => DL_39_link_read(PS_1_A), - DL_PS_2_A_link_AV_dout => DL_39_link_AV_dout(PS_2_A), - DL_PS_2_A_link_empty_neg => DL_39_link_empty_neg(PS_2_A), - DL_PS_2_A_link_read => DL_39_link_read(PS_2_A), - DL_twoS_1_A_link_AV_dout => DL_39_link_AV_dout(twoS_1_A), - DL_twoS_1_A_link_empty_neg => DL_39_link_empty_neg(twoS_1_A), - DL_twoS_1_A_link_read => DL_39_link_read(twoS_1_A), - DL_twoS_2_A_link_AV_dout => DL_39_link_AV_dout(twoS_2_A), - DL_twoS_2_A_link_empty_neg => DL_39_link_empty_neg(twoS_2_A), - DL_twoS_2_A_link_read => DL_39_link_read(twoS_2_A), - DL_twoS_3_A_link_AV_dout => DL_39_link_AV_dout(twoS_3_A), - DL_twoS_3_A_link_empty_neg => DL_39_link_empty_neg(twoS_3_A), - DL_twoS_3_A_link_read => DL_39_link_read(twoS_3_A), - DL_twoS_4_A_link_AV_dout => DL_39_link_AV_dout(twoS_4_A), - DL_twoS_4_A_link_empty_neg => DL_39_link_empty_neg(twoS_4_A), - DL_twoS_4_A_link_read => DL_39_link_read(twoS_4_A), - TW_L1L2_stream_AV_din => TW_104_stream_AV_din(L1L2), - TW_L1L2_stream_A_full_neg => TW_104_stream_A_full_neg(L1L2), - TW_L1L2_stream_A_write => TW_104_stream_A_write(L1L2), - BW_L1L2_L3_stream_AV_din => BW_46_stream_AV_din(L1L2_L3), - BW_L1L2_L3_stream_A_full_neg => BW_46_stream_A_full_neg(L1L2_L3), - BW_L1L2_L3_stream_A_write => BW_46_stream_A_write(L1L2_L3), - BW_L1L2_L4_stream_AV_din => BW_46_stream_AV_din(L1L2_L4), - BW_L1L2_L4_stream_A_full_neg => BW_46_stream_A_full_neg(L1L2_L4), - BW_L1L2_L4_stream_A_write => BW_46_stream_A_write(L1L2_L4), - BW_L1L2_L5_stream_AV_din => BW_46_stream_AV_din(L1L2_L5), - BW_L1L2_L5_stream_A_full_neg => BW_46_stream_A_full_neg(L1L2_L5), - BW_L1L2_L5_stream_A_write => BW_46_stream_A_write(L1L2_L5), - BW_L1L2_L6_stream_AV_din => BW_46_stream_AV_din(L1L2_L6), - BW_L1L2_L6_stream_A_full_neg => BW_46_stream_A_full_neg(L1L2_L6), - BW_L1L2_L6_stream_A_write => BW_46_stream_A_write(L1L2_L6) - ); - -end architecture rtl; diff --git a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/scripts/convert_emData2EMP_Link.py b/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/scripts/convert_emData2EMP_Link.py deleted file mode 100644 index ec074539a28..00000000000 --- a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/scripts/convert_emData2EMP_Link.py +++ /dev/null @@ -1,108 +0,0 @@ -import argparse -import os - -# Run with python3 in work/proj/ -# Converts InputRouter input data from emData to EMP format - -def parseArguments(): - # Create argument parser - parser = argparse.ArgumentParser(description="Convert an emData/ memory data file into a EMP format file. Link-file mapping is done editing the header of the script.") - - # Optional arguments - parser.add_argument("-d", "--directory", dest="inputDir", help="directory containing input data", type=str, default="emData/MemPrintsReduced/InputStubs/") - parser.add_argument("-o","--outFile", dest="outFile", help="output file name", type=str, default="Link_EMP.txt") - - # Parse arguments - args = parser.parse_args() - - return args - -# Files in order in which they are referred to in memUtil_pkg.vhd. -# with key being channel number. -channel_names = ["PS10G_1_A", "PS10G_2_A", "PS10G_3_A", "PS_1_A", "PS_2_A", "2S_1_A", "2S_2_A", "2S_3_A", "2S_4_A"] -channel_numbers = [68, 69, 70, 71, 72, 73, 74, 75, 76] - -mapping = {} -for ich in range(len(channel_names)): - mapping[channel_numbers[ich]] = "Link_DL_"+channel_names[ich]+"_04.dat" - -#channels = ["q00c0","q00c1","q00c2","q00c3","q01c0","q01c1","q01c2","q01c3","q02c0","q02c1","q02c2","q02c3","q03c0","q03c1","q03c2","q03c3"] - -empWordLen=16 # Hex chars in an EMP data word -clksInTM=108 # Length of TM period in clock cycles -clksInGap=6 # Gap when no valid data sent. - -if __name__ == '__main__': - - args = parseArguments() - - outFile = open(args.outFile, 'w') - - allData = {} - for chan, fileName in mapping.items(): - file = open(args.inputDir + "/" + fileName, 'r') - lines = file.readlines() - for line in lines: - words = line.split() - if len(words) == 6: - eventNumber = int(words[5]) - allData[(eventNumber,chan)] = [] - if len(words) == 3: - addr = words[0] - data = words[2] - empData = data[2:].zfill(empWordLen) - allData[(eventNumber,chan)].append(empData) - - outFile.write("ID: x0\n") - outFile.write("Metadata: (strobe,) start of orbit, start of packet, end of packet, valid\n") - outFile.write("\n") - outFile.write(" Link ") - for chan in mapping: - outFile.write("%s " %(str(chan).zfill(3))) - outFile.write("\n") - - gapData = "0000000000000000" - nullData = "0000000000000000" - md_null = "0000" - md_valid = "0001" - md_soe = "0101" - md_soo = "1101" - md_eoe = "0011" - iClk = 0 - - for event in range(1+eventNumber): - for iFrame in range(0,clksInTM): - iFrameCorr = iFrame - clksInGap - iClk += 1 - outFile.write("Frame %s " %(str(iClk-1).zfill(4))) - for chan in mapping: - theKey = (event,chan) - empDataList = allData[theKey] - if (iFrame < clksInGap): - outFile.write("%s " %md_null) - outFile.write("%s " %gapData) - elif (iFrameCorr < len(empDataList)): - if (event == 0) : - if (iFrameCorr == 0) : - outFile.write("%s " %md_soo) - elif (iFrame == clksInTM - 1) : - outFile.write("%s " %md_eoe) - else : - outFile.write("%s " %md_valid) - else : - if (iFrameCorr == 0) : - outFile.write("%s " %md_soe) - elif (iFrame == clksInTM - 1) : - outFile.write("%s " %md_eoe) - else : - outFile.write("%s " %md_valid) - outFile.write("%s " %empDataList[iFrameCorr]) - else: - if (iFrame == clksInTM - 1) : - outFile.write("%s " %md_eoe) - else : - outFile.write("%s " %md_valid) - outFile.write("%s " %nullData) - outFile.write("\n") - print("Output written to file ",args.outFile) - diff --git a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/ucf/ip.tcl b/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/ucf/ip.tcl deleted file mode 100644 index c0a84b7015f..00000000000 --- a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/ucf/ip.tcl +++ /dev/null @@ -1,4 +0,0 @@ -catch {get_property ip_repo_paths [current_project]} curr_ip_path -set set_ip_path "set_property ip_repo_paths {${curr_ip_path} ../../../src/firmware-hls/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/cgn/} \[\current_project\]" -eval ${set_ip_path} -update_ip_catalog diff --git a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/ucf/vsim.tcl b/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/ucf/vsim.tcl deleted file mode 100644 index 4db8b33251a..00000000000 --- a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/ucf/vsim.tcl +++ /dev/null @@ -1,11 +0,0 @@ -set_property SOURCE_SET sources_1 [get_filesets sim_1] -add_files -fileset sim_1 -norecurse ../../src/firmware-hls/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/mem/in.txt - -# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention. -set_property source_mgmt_mode None [current_project] -set_property top top [get_filesets sim_1] -set_property top_lib xil_defaultlib [get_filesets sim_1] -set_property target_language VHDL [current_project] -set_property simulator_language VHDL [current_project] -# Re-enabling previously disabled source management mode. -set_property source_mgmt_mode All [current_project] diff --git a/IntegrationTests/ReducedCombinedConfig/script/Makefile b/IntegrationTests/ReducedCombinedConfig/script/Makefile deleted file mode 100644 index 23194e2582e..00000000000 --- a/IntegrationTests/ReducedCombinedConfig/script/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# Define base directory of firmware-hls clone. -FIRMWARE=$(shell git rev-parse --show-toplevel) - -# MODIFY THESE LINES WHEN COPYING AND PASTING THIS MAKEFILE -TOP_FUNCS=$(FIRMWARE)/TopFunctions/ReducedCombinedConfig -MODULES=InputRouterTop_IR_DTC_2S_1_A InputRouterTop_IR_DTC_2S_2_A InputRouterTop_IR_DTC_2S_3_A InputRouterTop_IR_DTC_2S_4_A InputRouterTop_IR_DTC_PS10G_1_A InputRouterTop_IR_DTC_PS10G_2_A InputRouterTop_IR_DTC_PS10G_3_A InputRouterTop_IR_DTC_PS_1_A InputRouterTop_IR_DTC_PS_2_A VMRouterCMTop_L1PHIB VMRouterCMTop_L2PHIA VMRouterCMTop_L3PHIA VMRouterCMTop_L4PHIA VMRouterCMTop_L5PHIA VMRouterCMTop_L6PHIA TrackletProcessor_L1L2C MatchProcessor_L3PHIA MatchProcessor_L4PHIA MatchProcessor_L5PHIA MatchProcessor_L6PHIA TrackBuilder_L1L2 - -# Include rules for making the project. -include $(FIRMWARE)/IntegrationTests/common/script/Makefile.mk diff --git a/IntegrationTests/ReducedCombinedConfig/script/makeProject.tcl b/IntegrationTests/ReducedCombinedConfig/script/makeProject.tcl deleted file mode 100644 index dd9dd9323ed..00000000000 --- a/IntegrationTests/ReducedCombinedConfig/script/makeProject.tcl +++ /dev/null @@ -1,67 +0,0 @@ -# Create Vivado project, with user HDL files & IP. -# Run this in IntegrationTests/xyz/script/ - -# Create project -set projName "Work" -source ../../../project/fpga.tcl -create_project -force ${projName} ./${projName} -part $FPGA -set_property target_language VHDL [current_project] - -# Rebuild user HLS IP repos index before adding any source files -set_property ip_repo_paths "./" [get_filesets sources_1] -update_ip_catalog -rebuild - -# Create .xci files for user HLS IP -create_ip -name InputRouterTop_IR_DTC_PS10G_1_A -module_name IR_PS10G_1_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_PS10G_2_A -module_name IR_PS10G_2_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_PS10G_3_A -module_name IR_PS10G_3_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_PS_1_A -module_name IR_PS_1_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_PS_2_A -module_name IR_PS_2_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_2S_1_A -module_name IR_2S_1_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_2S_2_A -module_name IR_2S_2_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_2S_3_A -module_name IR_2S_3_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_2S_4_A -module_name IR_2S_4_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L1PHIB -module_name VMR_L1PHIB -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L2PHIA -module_name VMR_L2PHIA -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L3PHIA -module_name VMR_L3PHIA -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L4PHIA -module_name VMR_L4PHIA -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L5PHIA -module_name VMR_L5PHIA -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L6PHIA -module_name VMR_L6PHIA -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L1L2C -module_name TP_L1L2C -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L3PHIA -module_name MP_L3PHIA -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L4PHIA -module_name MP_L4PHIA -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L5PHIA -module_name MP_L5PHIA -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L6PHIA -module_name MP_L6PHIA -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackBuilder_L1L2 -module_name FT_L1L2 -vendor xilinx.com -library hls -version 1.0 - - -# Provide name of top-level HDL (without .vhd extension). -#set topLevelHDL "SectorProcessor" -set topLevelHDL "SectorProcessorFull" - -# Add HDL for algo -add_files -fileset sources_1 [glob ../hdl/SectorProcessor.vhd] -add_files -fileset sources_1 [glob ../hdl/SectorProcessorFull.vhd] -add_files -fileset sources_1 [glob ../hdl/memUtil_pkg.vhd] -add_files -fileset sources_1 [glob common/hdl/*.vhd] -remove_files -fileset sources_1 [glob common/hdl/latency_monitor.vhd] -remove_files -fileset sources_1 [glob common/hdl/tf_mem_new.vhd] - -# Add HDL for TB -add_files -fileset sim_1 [glob ../tb/tb_tf_top.vhd] - -# Add constraints (clock etc.) -add_files -fileset constrs_1 [glob common/hdl/constraints.xdc] - -# Set 'sim_1' fileset properties -set_property file_type {VHDL 2008} [get_files -filter {FILE_TYPE == VHDL}] -set_property top -value ${topLevelHDL} -objects [get_filesets sim_1] -set_property top -value "tb_tf_top" -objects [get_filesets sim_1] -set_property xsim.simulate.runtime -value "0us" -objects [get_filesets sim_1] -set_property simulator_language VHDL [current_project] - -update_compile_order -fileset sources_1 - -puts "INFO: Project created: ${projName}" - -exit diff --git a/IntegrationTests/ReducedCombinedConfig/script/runSim.tcl b/IntegrationTests/ReducedCombinedConfig/script/runSim.tcl deleted file mode 100644 index 46a65cbef11..00000000000 --- a/IntegrationTests/ReducedCombinedConfig/script/runSim.tcl +++ /dev/null @@ -1,23 +0,0 @@ -# Open project -set projName "Work" -open_project $projName/$projName.xpr - -reset_simulation sim_1 - -# Create directory for output .txt file -file delete -force dataOut/ -file mkdir dataOut/ - -# Launch Simulation -launch_simulation - -# Set default wave viewer cfg -#open_wave_config {../tb/prmemc.wcfg} -open_wave_config {../tb/start_bx.wcfg} -#open_wave_config {../tb/tf_top.wcfg} -#open_wave_config {../tb/mem_tf.wcfg} -#open_wave_config {../tb/mem_tf_wea.wcfg} - -restart -# Need 4us + 0.45us per event (50us for 100 events, but 10us for quick test). -run 50 us diff --git a/IntegrationTests/ReducedCombinedConfig/tb/start_bx.wcfg b/IntegrationTests/ReducedCombinedConfig/tb/start_bx.wcfg deleted file mode 100644 index 92b530a8d90..00000000000 --- a/IntegrationTests/ReducedCombinedConfig/tb/start_bx.wcfg +++ /dev/null @@ -1,92 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - clk - clk - - - addr_nentA[4:0] - addr_nentA[4:0] - - - sa_RAM_nentA0[0:31][3:0] - sa_RAM_nentA0[0:31][3:0] - - - sa_RAM_nentA1[0:31][3:0] - sa_RAM_nentA1[0:31][3:0] - - - sa_RAM_nentA2[0:31][3:0] - sa_RAM_nentA2[0:31][3:0] - - - sa_RAM_nentA3[0:31][3:0] - sa_RAM_nentA3[0:31][3:0] - - - sa_RAM_nentA4[0:31][3:0] - sa_RAM_nentA4[0:31][3:0] - - - sa_RAM_nentA5[0:31][3:0] - sa_RAM_nentA5[0:31][3:0] - - - sa_RAM_nentA6[0:31][3:0] - sa_RAM_nentA6[0:31][3:0] - - - sa_RAM_nentA7[0:31][3:0] - sa_RAM_nentA7[0:31][3:0] - - - addr_nentA[4:0] - addr_nentA[4:0] - - - addr_nentB[4:0] - addr_nentB[4:0] - - - dout_nentA[31:0] - dout_nentA[31:0] - - - ap_done - ap_done - - - ap_start - ap_start - - - ap_done - ap_done - - - ap_done - ap_done - - diff --git a/IntegrationTests/ReducedCombinedConfig2/script/Makefile b/IntegrationTests/ReducedCombinedConfig2/script/Makefile deleted file mode 100644 index a84c6a49a70..00000000000 --- a/IntegrationTests/ReducedCombinedConfig2/script/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# Define base directory of firmware-hls clone. -FIRMWARE=$(shell git rev-parse --show-toplevel) - -# MODIFY THESE LINES WHEN COPYING AND PASTING THIS MAKEFILE -TOP_FUNCS=$(FIRMWARE)/TopFunctions/ReducedCombinedConfig2 -MODULES= InputRouterTop_IR_DTC_PS10G_1_A InputRouterTop_IR_DTC_PS10G_1_B InputRouterTop_IR_DTC_PS10G_2_A InputRouterTop_IR_DTC_PS10G_2_B InputRouterTop_IR_DTC_PS10G_3_A InputRouterTop_IR_DTC_PS10G_3_B InputRouterTop_IR_DTC_PS_1_A InputRouterTop_IR_DTC_PS_1_B InputRouterTop_IR_DTC_PS_2_A InputRouterTop_IR_DTC_PS_2_B InputRouterTop_IR_DTC_2S_1_A InputRouterTop_IR_DTC_2S_1_B InputRouterTop_IR_DTC_2S_2_A InputRouterTop_IR_DTC_2S_2_B InputRouterTop_IR_DTC_2S_3_A InputRouterTop_IR_DTC_2S_3_B InputRouterTop_IR_DTC_2S_4_A InputRouterTop_IR_DTC_2S_4_B VMRouterCMTop_L1PHIA VMRouterCMTop_L1PHIB VMRouterCMTop_L1PHIC VMRouterCMTop_L1PHID VMRouterCMTop_L1PHIE VMRouterCMTop_L1PHIF VMRouterCMTop_L1PHIG VMRouterCMTop_L1PHIH VMRouterCMTop_L2PHIA VMRouterCMTop_L2PHIB VMRouterCMTop_L2PHIC VMRouterCMTop_L2PHID VMRouterCMTop_L3PHIA VMRouterCMTop_L3PHIB VMRouterCMTop_L3PHIC VMRouterCMTop_L3PHID VMRouterCMTop_L4PHIA VMRouterCMTop_L4PHIB VMRouterCMTop_L4PHIC VMRouterCMTop_L4PHID VMRouterCMTop_L5PHIA VMRouterCMTop_L5PHIB VMRouterCMTop_L5PHIC VMRouterCMTop_L5PHID VMRouterCMTop_L6PHIA VMRouterCMTop_L6PHIB VMRouterCMTop_L6PHIC VMRouterCMTop_L6PHID TrackletProcessor_L1L2A TrackletProcessor_L1L2B TrackletProcessor_L1L2C TrackletProcessor_L1L2D TrackletProcessor_L1L2E TrackletProcessor_L1L2F TrackletProcessor_L1L2G TrackletProcessor_L1L2H TrackletProcessor_L1L2I TrackletProcessor_L1L2J TrackletProcessor_L1L2K TrackletProcessor_L1L2L MatchProcessor_L3PHIA MatchProcessor_L3PHIB MatchProcessor_L3PHIC MatchProcessor_L3PHID MatchProcessor_L4PHIA MatchProcessor_L4PHIB MatchProcessor_L4PHIC MatchProcessor_L4PHID MatchProcessor_L5PHIA MatchProcessor_L5PHIB MatchProcessor_L5PHIC MatchProcessor_L5PHID MatchProcessor_L6PHIA MatchProcessor_L6PHIB MatchProcessor_L6PHIC MatchProcessor_L6PHID TrackBuilder_L1L2 -# Include rules for making the project. -include $(FIRMWARE)/IntegrationTests/common/script/Makefile.mk diff --git a/IntegrationTests/ReducedCombinedConfig2/script/makeProject.tcl b/IntegrationTests/ReducedCombinedConfig2/script/makeProject.tcl deleted file mode 100644 index d1c6e69e845..00000000000 --- a/IntegrationTests/ReducedCombinedConfig2/script/makeProject.tcl +++ /dev/null @@ -1,120 +0,0 @@ -# Create Vivado project, with user HDL files & IP. -# Run this in IntegrationTests/xyz/script/ - -# Create project -set projName "Work" -source ../../../project/fpga.tcl -create_project -force ${projName} ./${projName} -part $FPGA -set_property target_language VHDL [current_project] - -# Rebuild user HLS IP repos index before adding any source files -set_property ip_repo_paths "./" [get_filesets sources_1] -update_ip_catalog -rebuild - -# Create .xci files for user HLS IP -create_ip -name InputRouterTop_IR_DTC_PS10G_1_A -module_name IR_PS10G_1_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_PS10G_1_B -module_name IR_PS10G_1_B -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_PS10G_2_A -module_name IR_PS10G_2_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_PS10G_2_B -module_name IR_PS10G_2_B -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_PS10G_3_A -module_name IR_PS10G_3_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_PS10G_3_B -module_name IR_PS10G_3_B -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_PS_1_A -module_name IR_PS_1_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_PS_1_B -module_name IR_PS_1_B -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_PS_2_A -module_name IR_PS_2_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_PS_2_B -module_name IR_PS_2_B -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_2S_1_A -module_name IR_2S_1_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_2S_1_B -module_name IR_2S_1_B -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_2S_2_A -module_name IR_2S_2_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_2S_2_B -module_name IR_2S_2_B -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_2S_3_A -module_name IR_2S_3_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_2S_3_B -module_name IR_2S_3_B -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_2S_4_A -module_name IR_2S_4_A -vendor xilinx.com -library hls -version 1.0 -create_ip -name InputRouterTop_IR_DTC_2S_4_B -module_name IR_2S_4_B -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L1PHIA -module_name VMR_L1PHIA -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L1PHIB -module_name VMR_L1PHIB -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L1PHIC -module_name VMR_L1PHIC -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L1PHID -module_name VMR_L1PHID -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L1PHIE -module_name VMR_L1PHIE -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L1PHIF -module_name VMR_L1PHIF -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L1PHIG -module_name VMR_L1PHIG -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L1PHIH -module_name VMR_L1PHIH -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L2PHIA -module_name VMR_L2PHIA -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L2PHIB -module_name VMR_L2PHIB -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L2PHIC -module_name VMR_L2PHIC -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L2PHID -module_name VMR_L2PHID -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L3PHIA -module_name VMR_L3PHIA -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L3PHIB -module_name VMR_L3PHIB -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L3PHIC -module_name VMR_L3PHIC -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L3PHID -module_name VMR_L3PHID -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L4PHIA -module_name VMR_L4PHIA -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L4PHIB -module_name VMR_L4PHIB -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L4PHIC -module_name VMR_L4PHIC -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L4PHID -module_name VMR_L4PHID -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L5PHIA -module_name VMR_L5PHIA -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L5PHIB -module_name VMR_L5PHIB -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L5PHIC -module_name VMR_L5PHIC -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L5PHID -module_name VMR_L5PHID -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L6PHIA -module_name VMR_L6PHIA -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L6PHIB -module_name VMR_L6PHIB -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L6PHIC -module_name VMR_L6PHIC -vendor xilinx.com -library hls -version 1.0 -create_ip -name VMRouterCMTop_L6PHID -module_name VMR_L6PHID -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L1L2A -module_name TP_L1L2A -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L1L2B -module_name TP_L1L2B -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L1L2C -module_name TP_L1L2C -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L1L2D -module_name TP_L1L2D -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L1L2E -module_name TP_L1L2E -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L1L2F -module_name TP_L1L2F -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L1L2G -module_name TP_L1L2G -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L1L2H -module_name TP_L1L2H -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L1L2I -module_name TP_L1L2I -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L1L2J -module_name TP_L1L2J -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L1L2K -module_name TP_L1L2K -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackletProcessor_L1L2L -module_name TP_L1L2L -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L3PHIA -module_name MP_L3PHIA -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L3PHIB -module_name MP_L3PHIB -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L3PHIC -module_name MP_L3PHIC -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L3PHID -module_name MP_L3PHID -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L4PHIA -module_name MP_L4PHIA -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L4PHIB -module_name MP_L4PHIB -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L4PHIC -module_name MP_L4PHIC -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L4PHID -module_name MP_L4PHID -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L5PHIA -module_name MP_L5PHIA -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L5PHIB -module_name MP_L5PHIB -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L5PHIC -module_name MP_L5PHIC -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L5PHID -module_name MP_L5PHID -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L6PHIA -module_name MP_L6PHIA -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L6PHIB -module_name MP_L6PHIB -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L6PHIC -module_name MP_L6PHIC -vendor xilinx.com -library hls -version 1.0 -create_ip -name MatchProcessor_L6PHID -module_name MP_L6PHID -vendor xilinx.com -library hls -version 1.0 -create_ip -name TrackBuilder_L1L2 -module_name FT_L1L2 -vendor xilinx.com -library hls -version 1.0 - - -# Provide name of top-level HDL (without .vhd extension). -#set topLevelHDL "SectorProcessor" -set topLevelHDL "SectorProcessorFull" - -# Add HDL for algo -add_files -fileset sources_1 [glob ../hdl/SectorProcessor.vhd] -add_files -fileset sources_1 [glob ../hdl/SectorProcessorFull.vhd] -add_files -fileset sources_1 [glob ../hdl/memUtil_pkg.vhd] -add_files -fileset sources_1 [glob common/hdl/*.vhd] -remove_files -fileset sources_1 [glob common/hdl/latency_monitor.vhd] - -# Add HDL for TB -add_files -fileset sim_1 [glob ../tb/tb_tf_top.vhd] - -# Add constraints (clock etc.) -add_files -fileset constrs_1 [glob common/hdl/constraints.xdc] - -# Set 'sim_1' fileset properties -set_property file_type {VHDL 2008} [get_files -filter {FILE_TYPE == VHDL}] -set_property top -value ${topLevelHDL} -objects [get_filesets sim_1] -set_property top -value "tb_tf_top" -objects [get_filesets sim_1] -set_property xsim.simulate.runtime -value "0us" -objects [get_filesets sim_1] -set_property simulator_language VHDL [current_project] - -update_compile_order -fileset sources_1 - -puts "INFO: Project created: ${projName}" - -exit diff --git a/IntegrationTests/ReducedCombinedConfig2/script/runSim.tcl b/IntegrationTests/ReducedCombinedConfig2/script/runSim.tcl deleted file mode 100644 index e7c2f3c9493..00000000000 --- a/IntegrationTests/ReducedCombinedConfig2/script/runSim.tcl +++ /dev/null @@ -1,23 +0,0 @@ -# Open project -set projName "Work" -open_project $projName/$projName.xpr - -reset_simulation sim_1 - -# Create directory for output .txt file -file delete -force dataOut/ -file mkdir dataOut/ - -# Launch Simulation -launch_simulation - -# Set default wave viewer cfg -#open_wave_config {../tb/prmemc.wcfg} -#open_wave_config {../tb/start_bx.wcfg} -#open_wave_config {../tb/tf_top.wcfg} -#open_wave_config {../tb/mem_tf.wcfg} -#open_wave_config {../tb/mem_tf_wea.wcfg} - -restart -# Need 4us + 0.45us per event (50us for 100 events, but 10us for quick test). -run 50 us diff --git a/IntegrationTests/ReducedCombinedConfig_FPGA2/script/Makefile b/IntegrationTests/ReducedCombinedConfig_FPGA2/script/Makefile new file mode 100644 index 00000000000..1c8725b10e3 --- /dev/null +++ b/IntegrationTests/ReducedCombinedConfig_FPGA2/script/Makefile @@ -0,0 +1,9 @@ +# Define base directory of firmware-hls clone. +FIRMWARE=$(shell git rev-parse --show-toplevel) + +# MODIFY THESE LINES WHEN COPYING AND PASTING THIS MAKEFILE +TOP_FUNCS=$(FIRMWARE)/TopFunctions/ReducedCombinedConfig +MODULES=ProjectionCalculator_L5L6ABCD MatchProcessor_L1PHIA MatchProcessor_L1PHIB MatchProcessor_L1PHIC MatchProcessor_L1PHID MatchProcessor_L1PHIE MatchProcessor_L1PHIF MatchProcessor_L1PHIG MatchProcessor_L1PHIH MatchProcessor_L2PHIA MatchProcessor_L2PHIB MatchProcessor_L2PHIC MatchProcessor_L2PHID MatchProcessor_L3PHIA MatchProcessor_L3PHIB MatchProcessor_L3PHIC MatchProcessor_L3PHID MatchProcessor_L4PHIA MatchProcessor_L4PHIB MatchProcessor_L4PHIC MatchProcessor_L4PHID TrackBuilder_AAAA VMStubMERouterTop_L1PHIA VMStubMERouterTop_L1PHIB VMStubMERouterTop_L1PHIC VMStubMERouterTop_L1PHID VMStubMERouterTop_L1PHIE VMStubMERouterTop_L1PHIF VMStubMERouterTop_L1PHIG VMStubMERouterTop_L1PHIH VMStubMERouterTop_L2PHIA VMStubMERouterTop_L2PHIB VMStubMERouterTop_L2PHIC VMStubMERouterTop_L2PHID VMStubMERouterTop_L3PHIA VMStubMERouterTop_L3PHIB VMStubMERouterTop_L3PHIC VMStubMERouterTop_L3PHID VMStubMERouterTop_L4PHIA VMStubMERouterTop_L4PHIB VMStubMERouterTop_L4PHIC VMStubMERouterTop_L4PHID + +# Include rules for making the project. +include $(FIRMWARE)/IntegrationTests/common/script/Makefile.mk diff --git a/IntegrationTests/ReducedCombinedConfig_FPGA2/script/floorplan.xdc b/IntegrationTests/ReducedCombinedConfig_FPGA2/script/floorplan.xdc new file mode 100644 index 00000000000..f87c34267f7 --- /dev/null +++ b/IntegrationTests/ReducedCombinedConfig_FPGA2/script/floorplan.xdc @@ -0,0 +1,1414 @@ +#this XDC contains physical constraints for the out-of-context second FPGA project +create_pblock pblock_PCVMSMERs +add_cells_to_pblock [get_pblocks pblock_PCVMSMERs] [get_cells -quiet [list \ + PC_L1L2ABC \ + PC_L1L2DE \ + PC_L1L2F \ + PC_L1L2G \ + PC_L1L2HI \ + PC_L1L2JKL \ + PC_L2L3ABCD \ + PC_L3L4AB \ + PC_L3L4CD \ + PC_L5L6ABCD \ + PC_D1D2ABCD \ + PC_D3D4ABCD \ + PC_L1D1ABCD \ + PC_L1D1EFGH \ + PC_L2D1ABCD \ + VMSMER_L1PHIA \ + VMSMER_L1PHIB \ + VMSMER_L1PHIC \ + VMSMER_L1PHID \ + VMSMER_L1PHIE \ + VMSMER_L1PHIF \ + VMSMER_L1PHIG \ + VMSMER_L1PHIH \ + VMSMER_L2PHIA \ + VMSMER_L2PHIB \ + VMSMER_L2PHIC \ + VMSMER_L2PHID \ + VMSMER_L3PHIA \ + VMSMER_L3PHIB \ + VMSMER_L3PHIC \ + VMSMER_L3PHID \ + VMSMER_L4PHIA \ + VMSMER_L4PHIB \ + VMSMER_L4PHIC \ + VMSMER_L4PHID \ + VMSMER_L5PHIA \ + VMSMER_L5PHIB \ + VMSMER_L5PHIC \ + VMSMER_L5PHID \ + VMSMER_L6PHIA \ + VMSMER_L6PHIB \ + VMSMER_L6PHID \ + VMSMER_L6PHIC \ + VMSMER_D1PHIA \ + VMSMER_D1PHIB \ + VMSMER_D1PHIC \ + VMSMER_D1PHID \ + VMSMER_D2PHIA \ + VMSMER_D2PHIB \ + VMSMER_D2PHIC \ + VMSMER_D2PHID \ + VMSMER_D3PHIA \ + VMSMER_D3PHIB \ + VMSMER_D3PHIC \ + VMSMER_D3PHID \ + VMSMER_D4PHIA \ + VMSMER_D4PHIB \ + VMSMER_D4PHIC \ + VMSMER_D4PHID \ + VMSMER_D5PHIA \ + VMSMER_D5PHIB \ + VMSMER_D5PHIC \ + VMSMER_D5PHID \ + MPROJ_*_DELAY0 \ + ]] +resize_pblock [get_pblocks pblock_PCVMSMERs] -add {CLOCKREGION_X6Y0:CLOCKREGION_X6Y7} + +create_pblock pblock_MPL1A +add_cells_to_pblock [get_pblocks pblock_MPL1A] [get_cells -quiet [list \ + MP_L1PHIA \ + AS_L1PHIAn2_DELAY \ + AS_L1PHIAn2 \ + VMSME_L1PHIAn2_DELAY \ + VMSME_L1PHIAn2 \ + MPROJ_L2L3ABCD_L1PHIA_DELAY \ + MPROJ_L2L3ABCD_L1PHIA \ + MPROJ_L3L4AB_L1PHIA_DELAY \ + MPROJ_L3L4AB_L1PHIA \ + MPROJ_L5L6ABCD_L1PHIA_DELAY \ + MPROJ_L5L6ABCD_L1PHIA \ + MPROJ_D1D2ABCD_L1PHIA_DELAY \ + MPROJ_D1D2ABCD_L1PHIA \ + MPROJ_D3D4ABCD_L1PHIA_DELAY \ + MPROJ_D3D4ABCD_L1PHIA \ + MPROJ_L2D1ABCD_L1PHIA_DELAY \ + MPROJ_L2D1ABCD_L1PHIA \ + ]] + +create_pblock pblock_MPL1B +add_cells_to_pblock [get_pblocks pblock_MPL1B] [get_cells -quiet [list \ + MP_L1PHIB \ + AS_L1PHIBn2_DELAY \ + AS_L1PHIBn2 \ + VMSME_L1PHIBn2_DELAY \ + VMSME_L1PHIBn2 \ + MPROJ_L2L3ABCD_L1PHIB_DELAY \ + MPROJ_L2L3ABCD_L1PHIB \ + MPROJ_L3L4AB_L1PHIB_DELAY \ + MPROJ_L3L4AB_L1PHIB \ + MPROJ_L5L6ABCD_L1PHIB_DELAY \ + MPROJ_L5L6ABCD_L1PHIB \ + MPROJ_D1D2ABCD_L1PHIB_DELAY \ + MPROJ_D1D2ABCD_L1PHIB \ + MPROJ_D3D4ABCD_L1PHIB_DELAY \ + MPROJ_D3D4ABCD_L1PHIB \ + MPROJ_L2D1ABCD_L1PHIB_DELAY \ + MPROJ_L2D1ABCD_L1PHIB \ + ]] + +create_pblock pblock_MPL1C +add_cells_to_pblock [get_pblocks pblock_MPL1C] [get_cells -quiet [list \ + MP_L1PHIC \ + AS_L1PHICn2_DELAY \ + AS_L1PHICn2 \ + VMSME_L1PHICn2_DELAY \ + VMSME_L1PHICn2 \ + MPROJ_L2L3ABCD_L1PHIC_DELAY \ + MPROJ_L2L3ABCD_L1PHIC \ + MPROJ_L3L4AB_L1PHIC_DELAY \ + MPROJ_L3L4AB_L1PHIC \ + MPROJ_L5L6ABCD_L1PHIC_DELAY \ + MPROJ_L5L6ABCD_L1PHIC \ + MPROJ_D1D2ABCD_L1PHIC_DELAY \ + MPROJ_D1D2ABCD_L1PHIC \ + MPROJ_D3D4ABCD_L1PHIC_DELAY \ + MPROJ_D3D4ABCD_L1PHIC \ + MPROJ_L2D1ABCD_L1PHIC_DELAY \ + MPROJ_L2D1ABCD_L1PHIC \ + ]] + +create_pblock pblock_MPL1D +add_cells_to_pblock [get_pblocks pblock_MPL1D] [get_cells -quiet [list \ + MP_L1PHID \ + AS_L1PHIDn2_DELAY \ + AS_L1PHIDn2 \ + VMSME_L1PHIDn2_DELAY \ + VMSME_L1PHIDn2 \ + MPROJ_L2L3ABCD_L1PHID_DELAY \ + MPROJ_L2L3ABCD_L1PHID \ + MPROJ_L3L4AB_L1PHID_DELAY \ + MPROJ_L3L4AB_L1PHID \ + MPROJ_L3L4CD_L1PHID_DELAY \ + MPROJ_L3L4CD_L1PHID \ + MPROJ_L5L6ABCD_L1PHID_DELAY \ + MPROJ_L5L6ABCD_L1PHID \ + MPROJ_D1D2ABCD_L1PHID_DELAY \ + MPROJ_D1D2ABCD_L1PHID \ + MPROJ_D3D4ABCD_L1PHID_DELAY \ + MPROJ_D3D4ABCD_L1PHID \ + MPROJ_L2D1ABCD_L1PHID_DELAY \ + MPROJ_L2D1ABCD_L1PHID \ + ]] + +create_pblock pblock_MPL1E +add_cells_to_pblock [get_pblocks pblock_MPL1E] [get_cells -quiet [list \ + MP_L1PHIE \ + AS_L1PHIEn2_DELAY \ + AS_L1PHIEn2 \ + VMSME_L1PHIEn2_DELAY \ + VMSME_L1PHIEn2 \ + MPROJ_L2L3ABCD_L1PHIE_DELAY \ + MPROJ_L2L3ABCD_L1PHIE \ + MPROJ_L3L4AB_L1PHIE_DELAY \ + MPROJ_L3L4AB_L1PHIE \ + MPROJ_L3L4CD_L1PHIE_DELAY \ + MPROJ_L3L4CD_L1PHIE \ + MPROJ_L5L6ABCD_L1PHIE_DELAY \ + MPROJ_L5L6ABCD_L1PHIE \ + MPROJ_D1D2ABCD_L1PHIE_DELAY \ + MPROJ_D1D2ABCD_L1PHIE \ + MPROJ_D3D4ABCD_L1PHIE_DELAY \ + MPROJ_D3D4ABCD_L1PHIE \ + MPROJ_L2D1ABCD_L1PHIE_DELAY \ + MPROJ_L2D1ABCD_L1PHIE \ + ]] + +create_pblock pblock_MPL1F +add_cells_to_pblock [get_pblocks pblock_MPL1F] [get_cells -quiet [list \ + MP_L1PHIF \ + AS_L1PHIFn2_DELAY \ + AS_L1PHIFn2 \ + VMSME_L1PHIFn2_DELAY \ + VMSME_L1PHIFn2 \ + MPROJ_L2L3ABCD_L1PHIF_DELAY \ + MPROJ_L2L3ABCD_L1PHIF \ + MPROJ_L3L4AB_L1PHIF_DELAY \ + MPROJ_L3L4AB_L1PHIF \ + MPROJ_L3L4CD_L1PHIF_DELAY \ + MPROJ_L3L4CD_L1PHIF \ + MPROJ_L5L6ABCD_L1PHIF_DELAY \ + MPROJ_L5L6ABCD_L1PHIF \ + MPROJ_D1D2ABCD_L1PHIF_DELAY \ + MPROJ_D1D2ABCD_L1PHIF \ + MPROJ_D3D4ABCD_L1PHIF_DELAY \ + MPROJ_D3D4ABCD_L1PHIF \ + MPROJ_L2D1ABCD_L1PHIF_DELAY \ + MPROJ_L2D1ABCD_L1PHIF \ + ]] + +create_pblock pblock_MPL1G +add_cells_to_pblock [get_pblocks pblock_MPL1G] [get_cells -quiet [list \ + MP_L1PHIG \ + AS_L1PHIGn2_DELAY \ + AS_L1PHIGn2 \ + VMSME_L1PHIGn2_DELAY \ + VMSME_L1PHIGn2 \ + MPROJ_L2L3ABCD_L1PHIG_DELAY \ + MPROJ_L2L3ABCD_L1PHIG \ + MPROJ_L3L4CD_L1PHIG_DELAY \ + MPROJ_L3L4CD_L1PHIG \ + MPROJ_L5L6ABCD_L1PHIG_DELAY \ + MPROJ_L5L6ABCD_L1PHIG \ + MPROJ_D1D2ABCD_L1PHIG_DELAY \ + MPROJ_D1D2ABCD_L1PHIG \ + MPROJ_D3D4ABCD_L1PHIG_DELAY \ + MPROJ_D3D4ABCD_L1PHIG \ + MPROJ_L2D1ABCD_L1PHIG_DELAY \ + MPROJ_L2D1ABCD_L1PHIG \ + ]] + +create_pblock pblock_MPL1H +add_cells_to_pblock [get_pblocks pblock_MPL1H] [get_cells -quiet [list \ + MP_L1PHIH \ + AS_L1PHIHn2_DELAY \ + AS_L1PHIHn2 \ + VMSME_L1PHIHn2_DELAY \ + VMSME_L1PHIHn2 \ + MPROJ_L2L3ABCD_L1PHIH_DELAY \ + MPROJ_L2L3ABCD_L1PHIH \ + MPROJ_L3L4CD_L1PHIH_DELAY \ + MPROJ_L3L4CD_L1PHIH \ + MPROJ_L5L6ABCD_L1PHIH_DELAY \ + MPROJ_L5L6ABCD_L1PHIH \ + MPROJ_D1D2ABCD_L1PHIH_DELAY \ + MPROJ_D1D2ABCD_L1PHIH \ + MPROJ_D3D4ABCD_L1PHIH_DELAY \ + MPROJ_D3D4ABCD_L1PHIH \ + MPROJ_L2D1ABCD_L1PHIH_DELAY \ + MPROJ_L2D1ABCD_L1PHIH \ + ]] + +create_pblock pblock_MPL2A +add_cells_to_pblock [get_pblocks pblock_MPL2A] [get_cells -quiet [list \ + MP_L2PHIA \ + AS_L2PHIAn2_DELAY \ + AS_L2PHIAn2 \ + VMSME_L2PHIAn2_DELAY \ + VMSME_L2PHIAn2 \ + MPROJ_L3L4AB_L2PHIA_DELAY \ + MPROJ_L3L4AB_L2PHIA \ + MPROJ_L5L6ABCD_L2PHIA_DELAY \ + MPROJ_L5L6ABCD_L2PHIA \ + MPROJ_D1D2ABCD_L2PHIA_DELAY \ + MPROJ_D1D2ABCD_L2PHIA \ + ]] + +create_pblock pblock_MPL2B +add_cells_to_pblock [get_pblocks pblock_MPL2B] [get_cells -quiet [list \ + MP_L2PHIB \ + AS_L2PHIBn2_DELAY \ + AS_L2PHIBn2 \ + VMSME_L2PHIBn2_DELAY \ + VMSME_L2PHIBn2 \ + MPROJ_L3L4AB_L2PHIB_DELAY \ + MPROJ_L3L4AB_L2PHIB \ + MPROJ_L3L4CD_L2PHIB_DELAY \ + MPROJ_L3L4CD_L2PHIB \ + MPROJ_L5L6ABCD_L2PHIB_DELAY \ + MPROJ_L5L6ABCD_L2PHIB \ + MPROJ_D1D2ABCD_L2PHIB_DELAY \ + MPROJ_D1D2ABCD_L2PHIB \ + ]] + +create_pblock pblock_MPL2C +add_cells_to_pblock [get_pblocks pblock_MPL2C] [get_cells -quiet [list \ + MP_L2PHIC \ + AS_L2PHICn2_DELAY \ + AS_L2PHICn2 \ + VMSME_L2PHICn2_DELAY \ + VMSME_L2PHICn2 \ + MPROJ_L3L4AB_L2PHIC_DELAY \ + MPROJ_L3L4AB_L2PHIC \ + MPROJ_L3L4CD_L2PHIC_DELAY \ + MPROJ_L3L4CD_L2PHIC \ + MPROJ_L5L6ABCD_L2PHIC_DELAY \ + MPROJ_L5L6ABCD_L2PHIC \ + MPROJ_D1D2ABCD_L2PHIC_DELAY \ + MPROJ_D1D2ABCD_L2PHIC \ + ]] + +create_pblock pblock_MPL2D +add_cells_to_pblock [get_pblocks pblock_MPL2D] [get_cells -quiet [list \ + MP_L2PHID \ + AS_L2PHIDn2_DELAY \ + AS_L2PHIDn2 \ + VMSME_L2PHIDn2_DELAY \ + VMSME_L2PHIDn2 \ + MPROJ_L3L4CD_L2PHID_DELAY \ + MPROJ_L3L4CD_L2PHID \ + MPROJ_L5L6ABCD_L2PHID_DELAY \ + MPROJ_L5L6ABCD_L2PHID \ + MPROJ_D1D2ABCD_L2PHID_DELAY \ + MPROJ_D1D2ABCD_L2PHID \ + ]] + +create_pblock pblock_MPL3A +add_cells_to_pblock [get_pblocks pblock_MPL3A] [get_cells -quiet [list \ + MP_L3PHIA \ + AS_L3PHIAn2_DELAY \ + AS_L3PHIAn2 \ + VMSME_L3PHIAn2_DELAY \ + VMSME_L3PHIAn2 \ + MPROJ_L1L2ABC_L3PHIA_DELAY \ + MPROJ_L1L2ABC_L3PHIA \ + MPROJ_L1L2DE_L3PHIA_DELAY \ + MPROJ_L1L2DE_L3PHIA \ + MPROJ_L5L6ABCD_L3PHIA_DELAY \ + MPROJ_L5L6ABCD_L3PHIA \ + ]] + +create_pblock pblock_MPL3B +add_cells_to_pblock [get_pblocks pblock_MPL3B] [get_cells -quiet [list \ + MP_L3PHIB \ + AS_L3PHIBn2_DELAY \ + AS_L3PHIBn2 \ + VMSME_L3PHIBn2_DELAY \ + VMSME_L3PHIBn2 \ + MPROJ_L1L2ABC_L3PHIB_DELAY \ + MPROJ_L1L2ABC_L3PHIB \ + MPROJ_L1L2DE_L3PHIB_DELAY \ + MPROJ_L1L2DE_L3PHIB \ + MPROJ_L1L2F_L3PHIB_DELAY \ + MPROJ_L1L2F_L3PHIB \ + MPROJ_L1L2G_L3PHIB_DELAY \ + MPROJ_L1L2G_L3PHIB \ + MPROJ_L1L2HI_L3PHIB_DELAY \ + MPROJ_L1L2HI_L3PHIB \ + MPROJ_L5L6ABCD_L3PHIB_DELAY \ + MPROJ_L5L6ABCD_L3PHIB \ + ]] + +create_pblock pblock_MPL3C +add_cells_to_pblock [get_pblocks pblock_MPL3C] [get_cells -quiet [list \ + MP_L3PHIC \ + AS_L3PHICn2_DELAY \ + AS_L3PHICn2 \ + VMSME_L3PHICn2_DELAY \ + VMSME_L3PHICn2 \ + MPROJ_L1L2DE_L3PHIC_DELAY \ + MPROJ_L1L2DE_L3PHIC \ + MPROJ_L1L2F_L3PHIC_DELAY \ + MPROJ_L1L2F_L3PHIC \ + MPROJ_L1L2G_L3PHIC_DELAY \ + MPROJ_L1L2G_L3PHIC \ + MPROJ_L1L2HI_L3PHIC_DELAY \ + MPROJ_L1L2HI_L3PHIC \ + MPROJ_L1L2JKL_L3PHIC_DELAY \ + MPROJ_L1L2JKL_L3PHIC \ + MPROJ_L5L6ABCD_L3PHIC_DELAY \ + MPROJ_L5L6ABCD_L3PHIC \ + ]] + +create_pblock pblock_MPL3D +add_cells_to_pblock [get_pblocks pblock_MPL3D] [get_cells -quiet [list \ + MP_L3PHID \ + AS_L3PHIDn2_DELAY \ + AS_L3PHIDn2 \ + VMSME_L3PHIDn2_DELAY \ + VMSME_L3PHIDn2 \ + MPROJ_L1L2HI_L3PHID_DELAY \ + MPROJ_L1L2HI_L3PHID \ + MPROJ_L1L2JKL_L3PHID_DELAY \ + MPROJ_L1L2JKL_L3PHID \ + MPROJ_L5L6ABCD_L3PHID_DELAY \ + MPROJ_L5L6ABCD_L3PHID \ + ]] + +create_pblock pblock_MPL4A +add_cells_to_pblock [get_pblocks pblock_MPL4A] [get_cells -quiet [list \ + MP_L4PHIA \ + AS_L4PHIAn2_DELAY \ + AS_L4PHIAn2 \ + VMSME_L4PHIAn2_DELAY \ + VMSME_L4PHIAn2 \ + MPROJ_L1L2ABC_L4PHIA_DELAY \ + MPROJ_L1L2ABC_L4PHIA \ + MPROJ_L1L2DE_L4PHIA_DELAY \ + MPROJ_L1L2DE_L4PHIA \ + MPROJ_L1L2F_L4PHIA_DELAY \ + MPROJ_L1L2F_L4PHIA \ + MPROJ_L2L3ABCD_L4PHIA_DELAY \ + MPROJ_L2L3ABCD_L4PHIA \ + MPROJ_L5L6ABCD_L4PHIA_DELAY \ + MPROJ_L5L6ABCD_L4PHIA \ + ]] + +create_pblock pblock_MPL4B +add_cells_to_pblock [get_pblocks pblock_MPL4B] [get_cells -quiet [list \ + MP_L4PHIB \ + AS_L4PHIBn2_DELAY \ + AS_L4PHIBn2 \ + VMSME_L4PHIBn2_DELAY \ + VMSME_L4PHIBn2 \ + MPROJ_L1L2ABC_L4PHIB_DELAY \ + MPROJ_L1L2ABC_L4PHIB \ + MPROJ_L1L2DE_L4PHIB_DELAY \ + MPROJ_L1L2DE_L4PHIB \ + MPROJ_L1L2F_L4PHIB_DELAY \ + MPROJ_L1L2F_L4PHIB \ + MPROJ_L1L2G_L4PHIB_DELAY \ + MPROJ_L1L2G_L4PHIB \ + MPROJ_L1L2HI_L4PHIB_DELAY \ + MPROJ_L1L2HI_L4PHIB \ + MPROJ_L2L3ABCD_L4PHIB_DELAY \ + MPROJ_L2L3ABCD_L4PHIB \ + MPROJ_L5L6ABCD_L4PHIB_DELAY \ + MPROJ_L5L6ABCD_L4PHIB \ + ]] + +create_pblock pblock_MPL4C +add_cells_to_pblock [get_pblocks pblock_MPL4C] [get_cells -quiet [list \ + MP_L4PHIC \ + AS_L4PHICn2_DELAY \ + AS_L4PHICn2 \ + VMSME_L4PHICn2_DELAY \ + VMSME_L4PHICn2 \ + MPROJ_L1L2DE_L4PHIC_DELAY \ + MPROJ_L1L2DE_L4PHIC \ + MPROJ_L1L2F_L4PHIC_DELAY \ + MPROJ_L1L2F_L4PHIC \ + MPROJ_L1L2G_L4PHIC_DELAY \ + MPROJ_L1L2G_L4PHIC \ + MPROJ_L1L2HI_L4PHIC_DELAY \ + MPROJ_L1L2HI_L4PHIC \ + MPROJ_L1L2JKL_L4PHIC_DELAY \ + MPROJ_L1L2JKL_L4PHIC \ + MPROJ_L2L3ABCD_L4PHIC_DELAY \ + MPROJ_L2L3ABCD_L4PHIC \ + MPROJ_L5L6ABCD_L4PHIC_DELAY \ + MPROJ_L5L6ABCD_L4PHIC \ + ]] + +create_pblock pblock_MPL4D +add_cells_to_pblock [get_pblocks pblock_MPL4D] [get_cells -quiet [list \ + MP_L4PHID \ + AS_L4PHIDn2_DELAY \ + AS_L4PHIDn2 \ + VMSME_L4PHIDn2_DELAY \ + VMSME_L4PHIDn2 \ + MPROJ_L1L2HI_L4PHID_DELAY \ + MPROJ_L1L2HI_L4PHID \ + MPROJ_L1L2JKL_L4PHID_DELAY \ + MPROJ_L1L2JKL_L4PHID \ + MPROJ_L2L3ABCD_L4PHID_DELAY \ + MPROJ_L2L3ABCD_L4PHID \ + MPROJ_L5L6ABCD_L4PHID_DELAY \ + MPROJ_L5L6ABCD_L4PHID \ + ]] + +create_pblock pblock_MPL5A +add_cells_to_pblock [get_pblocks pblock_MPL5A] [get_cells -quiet [list \ + MP_L5PHIA \ + AS_L5PHIAn2_DELAY \ + AS_L5PHIAn2 \ + VMSME_L5PHIAn2_DELAY \ + VMSME_L5PHIAn2 \ + MPROJ_L1L2ABC_L5PHIA_DELAY \ + MPROJ_L1L2ABC_L5PHIA \ + MPROJ_L1L2DE_L5PHIA_DELAY \ + MPROJ_L1L2DE_L5PHIA \ + MPROJ_L1L2F_L5PHIA_DELAY \ + MPROJ_L1L2F_L5PHIA \ + MPROJ_L2L3ABCD_L5PHIA_DELAY \ + MPROJ_L2L3ABCD_L5PHIA \ + MPROJ_L3L4AB_L5PHIA_DELAY \ + MPROJ_L3L4AB_L5PHIA \ + ]] + +create_pblock pblock_MPL5B +add_cells_to_pblock [get_pblocks pblock_MPL5B] [get_cells -quiet [list \ + MP_L5PHIB \ + AS_L5PHIBn2_DELAY \ + AS_L5PHIBn2 \ + VMSME_L5PHIBn2_DELAY \ + VMSME_L5PHIBn2 \ + MPROJ_L1L2ABC_L5PHIB_DELAY \ + MPROJ_L1L2ABC_L5PHIB \ + MPROJ_L1L2DE_L5PHIB_DELAY \ + MPROJ_L1L2DE_L5PHIB \ + MPROJ_L1L2F_L5PHIB_DELAY \ + MPROJ_L1L2F_L5PHIB \ + MPROJ_L1L2G_L5PHIB_DELAY \ + MPROJ_L1L2G_L5PHIB \ + MPROJ_L1L2HI_L5PHIB_DELAY \ + MPROJ_L1L2HI_L5PHIB \ + MPROJ_L2L3ABCD_L5PHIB_DELAY \ + MPROJ_L2L3ABCD_L5PHIB \ + MPROJ_L3L4AB_L5PHIB_DELAY \ + MPROJ_L3L4AB_L5PHIB \ + MPROJ_L3L4CD_L5PHIB_DELAY \ + MPROJ_L3L4CD_L5PHIB \ + ]] + +create_pblock pblock_MPL5C +add_cells_to_pblock [get_pblocks pblock_MPL5C] [get_cells -quiet [list \ + MP_L5PHIC \ + AS_L5PHICn2_DELAY \ + AS_L5PHICn2 \ + VMSME_L5PHICn2_DELAY \ + VMSME_L5PHICn2 \ + MPROJ_L1L2DE_L5PHIC_DELAY \ + MPROJ_L1L2DE_L5PHIC \ + MPROJ_L1L2F_L5PHIC_DELAY \ + MPROJ_L1L2F_L5PHIC \ + MPROJ_L1L2G_L5PHIC_DELAY \ + MPROJ_L1L2G_L5PHIC \ + MPROJ_L1L2HI_L5PHIC_DELAY \ + MPROJ_L1L2HI_L5PHIC \ + MPROJ_L1L2JKL_L5PHIC_DELAY \ + MPROJ_L1L2JKL_L5PHIC \ + MPROJ_L2L3ABCD_L5PHIC_DELAY \ + MPROJ_L2L3ABCD_L5PHIC \ + MPROJ_L3L4AB_L5PHIC_DELAY \ + MPROJ_L3L4AB_L5PHIC \ + MPROJ_L3L4CD_L5PHIC_DELAY \ + MPROJ_L3L4CD_L5PHIC \ + ]] + +create_pblock pblock_MPL5D +add_cells_to_pblock [get_pblocks pblock_MPL5D] [get_cells -quiet [list \ + MP_L5PHID \ + AS_L5PHIDn2_DELAY \ + AS_L5PHIDn2 \ + VMSME_L5PHIDn2_DELAY \ + VMSME_L5PHIDn2 \ + MPROJ_L1L2G_L5PHID_DELAY \ + MPROJ_L1L2G_L5PHID \ + MPROJ_L1L2HI_L5PHID_DELAY \ + MPROJ_L1L2HI_L5PHID \ + MPROJ_L1L2JKL_L5PHID_DELAY \ + MPROJ_L1L2JKL_L5PHID \ + MPROJ_L2L3ABCD_L5PHID_DELAY \ + MPROJ_L2L3ABCD_L5PHID \ + MPROJ_L3L4CD_L5PHID_DELAY \ + MPROJ_L3L4CD_L5PHID \ + ]] + +create_pblock pblock_MPL6A +add_cells_to_pblock [get_pblocks pblock_MPL6A] [get_cells -quiet [list \ + MP_L6PHIA \ + AS_L6PHIAn2_DELAY \ + AS_L6PHIAn2 \ + VMSME_L6PHIAn2_DELAY \ + VMSME_L6PHIAn2 \ + MPROJ_L1L2ABC_L6PHIA_DELAY \ + MPROJ_L1L2ABC_L6PHIA \ + MPROJ_L1L2DE_L6PHIA_DELAY \ + MPROJ_L1L2DE_L6PHIA \ + MPROJ_L1L2F_L6PHIA_DELAY \ + MPROJ_L1L2F_L6PHIA \ + MPROJ_L3L4AB_L6PHIA_DELAY \ + MPROJ_L3L4AB_L6PHIA \ + ]] + +create_pblock pblock_MPL6B +add_cells_to_pblock [get_pblocks pblock_MPL6B] [get_cells -quiet [list \ + MP_L6PHIB \ + AS_L6PHIBn2_DELAY \ + AS_L6PHIBn2 \ + VMSME_L6PHIBn2_DELAY \ + VMSME_L6PHIBn2 \ + MPROJ_L1L2ABC_L6PHIB_DELAY \ + MPROJ_L1L2ABC_L6PHIB \ + MPROJ_L1L2DE_L6PHIB_DELAY \ + MPROJ_L1L2DE_L6PHIB \ + MPROJ_L1L2F_L6PHIB_DELAY \ + MPROJ_L1L2F_L6PHIB \ + MPROJ_L1L2G_L6PHIB_DELAY \ + MPROJ_L1L2G_L6PHIB \ + MPROJ_L1L2HI_L6PHIB_DELAY \ + MPROJ_L1L2HI_L6PHIB \ + MPROJ_L3L4AB_L6PHIB_DELAY \ + MPROJ_L3L4AB_L6PHIB \ + MPROJ_L3L4CD_L6PHIB_DELAY \ + MPROJ_L3L4CD_L6PHIB \ + ]] + +create_pblock pblock_MPL6C +add_cells_to_pblock [get_pblocks pblock_MPL6C] [get_cells -quiet [list \ + MP_L6PHIC \ + AS_L6PHICn2_DELAY \ + AS_L6PHICn2 \ + VMSME_L6PHICn2_DELAY \ + VMSME_L6PHICn2 \ + MPROJ_L1L2DE_L6PHIC_DELAY \ + MPROJ_L1L2DE_L6PHIC \ + MPROJ_L1L2F_L6PHIC_DELAY \ + MPROJ_L1L2F_L6PHIC \ + MPROJ_L1L2G_L6PHIC_DELAY \ + MPROJ_L1L2G_L6PHIC \ + MPROJ_L1L2HI_L6PHIC_DELAY \ + MPROJ_L1L2HI_L6PHIC \ + MPROJ_L1L2JKL_L6PHIC_DELAY \ + MPROJ_L1L2JKL_L6PHIC \ + MPROJ_L3L4AB_L6PHIC_DELAY \ + MPROJ_L3L4AB_L6PHIC \ + MPROJ_L3L4CD_L6PHIC_DELAY \ + MPROJ_L3L4CD_L6PHIC \ + ]] + +create_pblock pblock_MPL6D +add_cells_to_pblock [get_pblocks pblock_MPL6D] [get_cells -quiet [list \ + MP_L6PHID \ + AS_L6PHIDn2_DELAY \ + AS_L6PHIDn2 \ + VMSME_L6PHIDn2_DELAY \ + VMSME_L6PHIDn2 \ + MPROJ_L1L2G_L6PHID_DELAY \ + MPROJ_L1L2G_L6PHID \ + MPROJ_L1L2HI_L6PHID_DELAY \ + MPROJ_L1L2HI_L6PHID \ + MPROJ_L1L2JKL_L6PHID_DELAY \ + MPROJ_L1L2JKL_L6PHID \ + MPROJ_L3L4CD_L6PHID_DELAY \ + MPROJ_L3L4CD_L6PHID \ + ]] + +resize_pblock [get_pblocks pblock_MPL1A] -add {CLOCKREGION_X2Y0:CLOCKREGION_X6Y3} +resize_pblock [get_pblocks pblock_MPL1B] -add {CLOCKREGION_X2Y0:CLOCKREGION_X6Y3} +resize_pblock [get_pblocks pblock_MPL1C] -add {CLOCKREGION_X2Y0:CLOCKREGION_X6Y3} +resize_pblock [get_pblocks pblock_MPL1D] -add {CLOCKREGION_X2Y0:CLOCKREGION_X6Y3} + +resize_pblock [get_pblocks pblock_MPL1E] -add {CLOCKREGION_X2Y0:CLOCKREGION_X6Y3} +resize_pblock [get_pblocks pblock_MPL1F] -add {CLOCKREGION_X2Y0:CLOCKREGION_X6Y3} +resize_pblock [get_pblocks pblock_MPL1G] -add {CLOCKREGION_X2Y0:CLOCKREGION_X6Y3} +resize_pblock [get_pblocks pblock_MPL1H] -add {CLOCKREGION_X2Y0:CLOCKREGION_X6Y3} + +resize_pblock [get_pblocks pblock_MPL2A] -add {CLOCKREGION_X2Y0:CLOCKREGION_X6Y3} +resize_pblock [get_pblocks pblock_MPL2B] -add {CLOCKREGION_X2Y0:CLOCKREGION_X6Y3} +resize_pblock [get_pblocks pblock_MPL2C] -add {CLOCKREGION_X2Y0:CLOCKREGION_X6Y3} +resize_pblock [get_pblocks pblock_MPL2D] -add {CLOCKREGION_X2Y0:CLOCKREGION_X6Y3} + +resize_pblock [get_pblocks pblock_MPL3A] -add {CLOCKREGION_X2Y0:CLOCKREGION_X6Y3} +resize_pblock [get_pblocks pblock_MPL3B] -add {CLOCKREGION_X2Y0:CLOCKREGION_X6Y3} +resize_pblock [get_pblocks pblock_MPL3C] -add {CLOCKREGION_X2Y0:CLOCKREGION_X6Y3} +resize_pblock [get_pblocks pblock_MPL3D] -add {CLOCKREGION_X2Y0:CLOCKREGION_X6Y3} + +resize_pblock [get_pblocks pblock_MPL4A] -add {CLOCKREGION_X2Y0:CLOCKREGION_X6Y3} +resize_pblock [get_pblocks pblock_MPL4B] -add {CLOCKREGION_X2Y0:CLOCKREGION_X6Y3} +resize_pblock [get_pblocks pblock_MPL4C] -add {CLOCKREGION_X2Y0:CLOCKREGION_X6Y3} +resize_pblock [get_pblocks pblock_MPL4D] -add {CLOCKREGION_X2Y0:CLOCKREGION_X6Y3} + +resize_pblock [get_pblocks pblock_MPL5A] -add {CLOCKREGION_X2Y0:CLOCKREGION_X6Y3} +resize_pblock [get_pblocks pblock_MPL5B] -add {CLOCKREGION_X2Y0:CLOCKREGION_X6Y3} +resize_pblock [get_pblocks pblock_MPL5C] -add {CLOCKREGION_X2Y0:CLOCKREGION_X6Y3} +resize_pblock [get_pblocks pblock_MPL5D] -add {CLOCKREGION_X2Y0:CLOCKREGION_X6Y3} + +resize_pblock [get_pblocks pblock_MPL6A] -add {CLOCKREGION_X2Y0:CLOCKREGION_X6Y3} +resize_pblock [get_pblocks pblock_MPL6B] -add {CLOCKREGION_X2Y0:CLOCKREGION_X6Y3} +resize_pblock [get_pblocks pblock_MPL6C] -add {CLOCKREGION_X2Y0:CLOCKREGION_X6Y3} +resize_pblock [get_pblocks pblock_MPL6D] -add {CLOCKREGION_X2Y0:CLOCKREGION_X6Y3} + + +create_pblock pblock_MPD1A +add_cells_to_pblock [get_pblocks pblock_MPD1A] [get_cells -quiet [list \ + MP_D1PHIA \ + AS_D1PHIAn2_DELAY \ + AS_D1PHIAn2 \ + VMSME_D1PHIAn2_DELAY \ + VMSME_D1PHIAn2 \ + MPROJ_L1L2ABC_D1PHIA_DELAY \ + MPROJ_L1L2ABC_D1PHIA \ + MPROJ_L1L2DE_D1PHIA_DELAY \ + MPROJ_L1L2DE_D1PHIA \ + MPROJ_L1L2F_D1PHIA_DELAY \ + MPROJ_L1L2F_D1PHIA \ + MPROJ_L2L3ABCD_D1PHIA_DELAY \ + MPROJ_L2L3ABCD_D1PHIA \ + MPROJ_L3L4AB_D1PHIA_DELAY \ + MPROJ_L3L4AB_D1PHIA \ + MPROJ_D3D4ABCD_D1PHIA_DELAY \ + MPROJ_D3D4ABCD_D1PHIA \ + ]] + +create_pblock pblock_MPD1B +add_cells_to_pblock [get_pblocks pblock_MPD1B] [get_cells -quiet [list \ + MP_D1PHIB \ + AS_D1PHIBn2_DELAY \ + AS_D1PHIBn2 \ + VMSME_D1PHIBn2_DELAY \ + VMSME_D1PHIBn2 \ + MPROJ_L1L2ABC_D1PHIB_DELAY \ + MPROJ_L1L2ABC_D1PHIB \ + MPROJ_L1L2DE_D1PHIB_DELAY \ + MPROJ_L1L2DE_D1PHIB \ + MPROJ_L1L2F_D1PHIB_DELAY \ + MPROJ_L1L2F_D1PHIB \ + MPROJ_L1L2G_D1PHIB_DELAY \ + MPROJ_L1L2G_D1PHIB \ + MPROJ_L1L2HI_D1PHIB_DELAY \ + MPROJ_L1L2HI_D1PHIB \ + MPROJ_L2L3ABCD_D1PHIB_DELAY \ + MPROJ_L2L3ABCD_D1PHIB \ + MPROJ_L3L4AB_D1PHIB_DELAY \ + MPROJ_L3L4AB_D1PHIB \ + MPROJ_L3L4CD_D1PHIB_DELAY \ + MPROJ_L3L4CD_D1PHIB \ + MPROJ_D3D4ABCD_D1PHIB_DELAY \ + MPROJ_D3D4ABCD_D1PHIB \ + ]] + +create_pblock pblock_MPD1C +add_cells_to_pblock [get_pblocks pblock_MPD1C] [get_cells -quiet [list \ + MP_D1PHIC \ + AS_D1PHICn2_DELAY \ + AS_D1PHICn2 \ + VMSME_D1PHICn2_DELAY \ + VMSME_D1PHICn2 \ + MPROJ_L1L2DE_D1PHIC_DELAY \ + MPROJ_L1L2DE_D1PHIC \ + MPROJ_L1L2F_D1PHIC_DELAY \ + MPROJ_L1L2F_D1PHIC \ + MPROJ_L1L2G_D1PHIC_DELAY \ + MPROJ_L1L2G_D1PHIC \ + MPROJ_L1L2HI_D1PHIC_DELAY \ + MPROJ_L1L2HI_D1PHIC \ + MPROJ_L1L2JKL_D1PHIC_DELAY \ + MPROJ_L1L2JKL_D1PHIC \ + MPROJ_L2L3ABCD_D1PHIC_DELAY \ + MPROJ_L2L3ABCD_D1PHIC \ + MPROJ_L3L4AB_D1PHIC_DELAY \ + MPROJ_L3L4AB_D1PHIC \ + MPROJ_L3L4CD_D1PHIC_DELAY \ + MPROJ_L3L4CD_D1PHIC \ + MPROJ_D3D4ABCD_D1PHIC_DELAY \ + MPROJ_D3D4ABCD_D1PHIC \ + ]] + +create_pblock pblock_MPD1D +add_cells_to_pblock [get_pblocks pblock_MPD1D] [get_cells -quiet [list \ + MP_D1PHID \ + AS_D1PHIDn2_DELAY \ + AS_D1PHIDn2 \ + VMSME_D1PHIDn2_DELAY \ + VMSME_D1PHIDn2 \ + MPROJ_L1L2G_D1PHID_DELAY \ + MPROJ_L1L2G_D1PHID \ + MPROJ_L1L2HI_D1PHID_DELAY \ + MPROJ_L1L2HI_D1PHID \ + MPROJ_L1L2JKL_D1PHID_DELAY \ + MPROJ_L1L2JKL_D1PHID \ + MPROJ_L2L3ABCD_D1PHID_DELAY \ + MPROJ_L2L3ABCD_D1PHID \ + MPROJ_L3L4CD_D1PHID_DELAY \ + MPROJ_L3L4CD_D1PHID \ + MPROJ_D3D4ABCD_D1PHID_DELAY \ + MPROJ_D3D4ABCD_D1PHID \ + ]] + +create_pblock pblock_MPD2A +add_cells_to_pblock [get_pblocks pblock_MPD2A] [get_cells -quiet [list \ + MP_D2PHIA \ + AS_D2PHIAn2_DELAY \ + AS_D2PHIAn2 \ + VMSME_D2PHIAn2_DELAY \ + VMSME_D2PHIAn2 \ + MPROJ_L1L2ABC_D2PHIA_DELAY \ + MPROJ_L1L2ABC_D2PHIA \ + MPROJ_L1L2DE_D2PHIA_DELAY \ + MPROJ_L1L2DE_D2PHIA \ + MPROJ_L1L2F_D2PHIA_DELAY \ + MPROJ_L1L2F_D2PHIA \ + MPROJ_L2L3ABCD_D2PHIA_DELAY \ + MPROJ_L2L3ABCD_D2PHIA \ + MPROJ_L3L4AB_D2PHIA_DELAY \ + MPROJ_L3L4AB_D2PHIA \ + MPROJ_D3D4ABCD_D2PHIA_DELAY \ + MPROJ_D3D4ABCD_D2PHIA \ + MPROJ_L1D1ABCD_D2PHIA_DELAY \ + MPROJ_L1D1ABCD_D2PHIA \ + MPROJ_L2D1ABCD_D2PHIA_DELAY \ + MPROJ_L2D1ABCD_D2PHIA \ + ]] + +create_pblock pblock_MPD2B +add_cells_to_pblock [get_pblocks pblock_MPD2B] [get_cells -quiet [list \ + MP_D2PHIB \ + AS_D2PHIBn2_DELAY \ + AS_D2PHIBn2 \ + VMSME_D2PHIBn2_DELAY \ + VMSME_D2PHIBn2 \ + MPROJ_L1L2ABC_D2PHIB_DELAY \ + MPROJ_L1L2ABC_D2PHIB \ + MPROJ_L1L2DE_D2PHIB_DELAY \ + MPROJ_L1L2DE_D2PHIB \ + MPROJ_L1L2F_D2PHIB_DELAY \ + MPROJ_L1L2F_D2PHIB \ + MPROJ_L1L2G_D2PHIB_DELAY \ + MPROJ_L1L2G_D2PHIB \ + MPROJ_L1L2HI_D2PHIB_DELAY \ + MPROJ_L1L2HI_D2PHIB \ + MPROJ_L2L3ABCD_D2PHIB_DELAY \ + MPROJ_L2L3ABCD_D2PHIB \ + MPROJ_L3L4AB_D2PHIB_DELAY \ + MPROJ_L3L4AB_D2PHIB \ + MPROJ_L3L4CD_D2PHIB_DELAY \ + MPROJ_L3L4CD_D2PHIB \ + MPROJ_D3D4ABCD_D2PHIB_DELAY \ + MPROJ_D3D4ABCD_D2PHIB \ + MPROJ_L1D1ABCD_D2PHIB_DELAY \ + MPROJ_L1D1ABCD_D2PHIB \ + MPROJ_L1D1EFGH_D2PHIB_DELAY \ + MPROJ_L1D1EFGH_D2PHIB \ + MPROJ_L2D1ABCD_D2PHIB_DELAY \ + MPROJ_L2D1ABCD_D2PHIB \ + ]] + +create_pblock pblock_MPD2C +add_cells_to_pblock [get_pblocks pblock_MPD2C] [get_cells -quiet [list \ + MP_D2PHIC \ + AS_D2PHICn2_DELAY \ + AS_D2PHICn2 \ + VMSME_D2PHICn2_DELAY \ + VMSME_D2PHICn2 \ + MPROJ_L1L2DE_D2PHIC_DELAY \ + MPROJ_L1L2DE_D2PHIC \ + MPROJ_L1L2F_D2PHIC_DELAY \ + MPROJ_L1L2F_D2PHIC \ + MPROJ_L1L2G_D2PHIC_DELAY \ + MPROJ_L1L2G_D2PHIC \ + MPROJ_L1L2HI_D2PHIC_DELAY \ + MPROJ_L1L2HI_D2PHIC \ + MPROJ_L1L2JKL_D2PHIC_DELAY \ + MPROJ_L1L2JKL_D2PHIC \ + MPROJ_L2L3ABCD_D2PHIC_DELAY \ + MPROJ_L2L3ABCD_D2PHIC \ + MPROJ_L3L4AB_D2PHIC_DELAY \ + MPROJ_L3L4AB_D2PHIC \ + MPROJ_L3L4CD_D2PHIC_DELAY \ + MPROJ_L3L4CD_D2PHIC \ + MPROJ_D3D4ABCD_D2PHIC_DELAY \ + MPROJ_D3D4ABCD_D2PHIC \ + MPROJ_L1D1ABCD_D2PHIC_DELAY \ + MPROJ_L1D1ABCD_D2PHIC \ + MPROJ_L1D1EFGH_D2PHIC_DELAY \ + MPROJ_L1D1EFGH_D2PHIC \ + MPROJ_L2D1ABCD_D2PHIC_DELAY \ + MPROJ_L2D1ABCD_D2PHIC \ + ]] + +create_pblock pblock_MPD2D +add_cells_to_pblock [get_pblocks pblock_MPD2D] [get_cells -quiet [list \ + MP_D2PHID \ + AS_D2PHIDn2_DELAY \ + AS_D2PHIDn2 \ + VMSME_D2PHIDn2_DELAY \ + VMSME_D2PHIDn2 \ + MPROJ_L1L2G_D2PHID_DELAY \ + MPROJ_L1L2G_D2PHID \ + MPROJ_L1L2HI_D2PHID_DELAY \ + MPROJ_L1L2HI_D2PHID \ + MPROJ_L1L2JKL_D2PHID_DELAY \ + MPROJ_L1L2JKL_D2PHID \ + MPROJ_L2L3ABCD_D2PHID_DELAY \ + MPROJ_L2L3ABCD_D2PHID \ + MPROJ_L3L4CD_D2PHID_DELAY \ + MPROJ_L3L4CD_D2PHID \ + MPROJ_D3D4ABCD_D2PHID_DELAY \ + MPROJ_D3D4ABCD_D2PHID \ + MPROJ_L1D1EFGH_D2PHID_DELAY \ + MPROJ_L1D1EFGH_D2PHID \ + MPROJ_L2D1ABCD_D2PHID_DELAY \ + MPROJ_L2D1ABCD_D2PHID \ + ]] + +create_pblock pblock_MPD3A +add_cells_to_pblock [get_pblocks pblock_MPD3A] [get_cells -quiet [list \ + MP_D3PHIA \ + AS_D3PHIAn2_DELAY \ + AS_D3PHIAn2 \ + VMSME_D3PHIAn2_DELAY \ + VMSME_D3PHIAn2 \ + MPROJ_L1L2ABC_D3PHIA_DELAY \ + MPROJ_L1L2ABC_D3PHIA \ + MPROJ_L1L2DE_D3PHIA_DELAY \ + MPROJ_L1L2DE_D3PHIA \ + MPROJ_L1L2F_D3PHIA_DELAY \ + MPROJ_L1L2F_D3PHIA \ + MPROJ_L2L3ABCD_D3PHIA_DELAY \ + MPROJ_L2L3ABCD_D3PHIA \ + MPROJ_D1D2ABCD_D3PHIA_DELAY \ + MPROJ_D1D2ABCD_D3PHIA \ + MPROJ_L1D1ABCD_D3PHIA_DELAY \ + MPROJ_L1D1ABCD_D3PHIA \ + MPROJ_L2D1ABCD_D3PHIA_DELAY \ + MPROJ_L2D1ABCD_D3PHIA \ + ]] + +create_pblock pblock_MPD3B +add_cells_to_pblock [get_pblocks pblock_MPD3B] [get_cells -quiet [list \ + MP_D3PHIB \ + AS_D3PHIBn2_DELAY \ + AS_D3PHIBn2 \ + VMSME_D3PHIBn2_DELAY \ + VMSME_D3PHIBn2 \ + MPROJ_L1L2ABC_D3PHIB_DELAY \ + MPROJ_L1L2ABC_D3PHIB \ + MPROJ_L1L2DE_D3PHIB_DELAY \ + MPROJ_L1L2DE_D3PHIB \ + MPROJ_L1L2F_D3PHIB_DELAY \ + MPROJ_L1L2F_D3PHIB \ + MPROJ_L1L2G_D3PHIB_DELAY \ + MPROJ_L1L2G_D3PHIB \ + MPROJ_L1L2HI_D3PHIB_DELAY \ + MPROJ_L1L2HI_D3PHIB \ + MPROJ_L2L3ABCD_D3PHIB_DELAY \ + MPROJ_L2L3ABCD_D3PHIB \ + MPROJ_D1D2ABCD_D3PHIB_DELAY \ + MPROJ_D1D2ABCD_D3PHIB \ + MPROJ_L1D1ABCD_D3PHIB_DELAY \ + MPROJ_L1D1ABCD_D3PHIB \ + MPROJ_L1D1EFGH_D3PHIB_DELAY \ + MPROJ_L1D1EFGH_D3PHIB \ + MPROJ_L2D1ABCD_D3PHIB_DELAY \ + MPROJ_L2D1ABCD_D3PHIB \ + ]] + +create_pblock pblock_MPD3C +add_cells_to_pblock [get_pblocks pblock_MPD3C] [get_cells -quiet [list \ + MP_D3PHIC \ + AS_D3PHICn2_DELAY \ + AS_D3PHICn2 \ + VMSME_D3PHICn2_DELAY \ + VMSME_D3PHICn2 \ + MPROJ_L1L2DE_D3PHIC_DELAY \ + MPROJ_L1L2DE_D3PHIC \ + MPROJ_L1L2F_D3PHIC_DELAY \ + MPROJ_L1L2F_D3PHIC \ + MPROJ_L1L2G_D3PHIC_DELAY \ + MPROJ_L1L2G_D3PHIC \ + MPROJ_L1L2HI_D3PHIC_DELAY \ + MPROJ_L1L2HI_D3PHIC \ + MPROJ_L1L2JKL_D3PHIC_DELAY \ + MPROJ_L1L2JKL_D3PHIC \ + MPROJ_L2L3ABCD_D3PHIC_DELAY \ + MPROJ_L2L3ABCD_D3PHIC \ + MPROJ_D1D2ABCD_D3PHIC_DELAY \ + MPROJ_D1D2ABCD_D3PHIC \ + MPROJ_L1D1ABCD_D3PHIC_DELAY \ + MPROJ_L1D1ABCD_D3PHIC \ + MPROJ_L1D1EFGH_D3PHIC_DELAY \ + MPROJ_L1D1EFGH_D3PHIC \ + MPROJ_L2D1ABCD_D3PHIC_DELAY \ + MPROJ_L2D1ABCD_D3PHIC \ + ]] + +create_pblock pblock_MPD3D +add_cells_to_pblock [get_pblocks pblock_MPD3D] [get_cells -quiet [list \ + MP_D3PHID \ + AS_D3PHIDn2_DELAY \ + AS_D3PHIDn2 \ + VMSME_D3PHIDn2_DELAY \ + VMSME_D3PHIDn2 \ + MPROJ_L1L2G_D3PHID_DELAY \ + MPROJ_L1L2G_D3PHID \ + MPROJ_L1L2HI_D3PHID_DELAY \ + MPROJ_L1L2HI_D3PHID \ + MPROJ_L1L2JKL_D3PHID_DELAY \ + MPROJ_L1L2JKL_D3PHID \ + MPROJ_L2L3ABCD_D3PHID_DELAY \ + MPROJ_L2L3ABCD_D3PHID \ + MPROJ_D1D2ABCD_D3PHID_DELAY \ + MPROJ_D1D2ABCD_D3PHID \ + MPROJ_L1D1EFGH_D3PHID_DELAY \ + MPROJ_L1D1EFGH_D3PHID \ + MPROJ_L2D1ABCD_D3PHID_DELAY \ + MPROJ_L2D1ABCD_D3PHID \ + ]] + +create_pblock pblock_MPD4A +add_cells_to_pblock [get_pblocks pblock_MPD4A] [get_cells -quiet [list \ + MP_D4PHIA \ + AS_D4PHIAn2_DELAY \ + AS_D4PHIAn2 \ + VMSME_D4PHIAn2_DELAY \ + VMSME_D4PHIAn2 \ + MPROJ_L1L2ABC_D4PHIA_DELAY \ + MPROJ_L1L2ABC_D4PHIA \ + MPROJ_L1L2DE_D4PHIA_DELAY \ + MPROJ_L1L2DE_D4PHIA \ + MPROJ_L1L2F_D4PHIA_DELAY \ + MPROJ_L1L2F_D4PHIA \ + MPROJ_L2L3ABCD_D4PHIA_DELAY \ + MPROJ_L2L3ABCD_D4PHIA \ + MPROJ_D1D2ABCD_D4PHIA_DELAY \ + MPROJ_D1D2ABCD_D4PHIA \ + MPROJ_L1D1ABCD_D4PHIA_DELAY \ + MPROJ_L1D1ABCD_D4PHIA \ + MPROJ_L2D1ABCD_D4PHIA_DELAY \ + MPROJ_L2D1ABCD_D4PHIA \ + ]] + +create_pblock pblock_MPD4B +add_cells_to_pblock [get_pblocks pblock_MPD4B] [get_cells -quiet [list \ + MP_D4PHIB \ + AS_D4PHIBn2_DELAY \ + AS_D4PHIBn2 \ + VMSME_D4PHIBn2_DELAY \ + VMSME_D4PHIBn2 \ + MPROJ_L1L2ABC_D4PHIB_DELAY \ + MPROJ_L1L2ABC_D4PHIB \ + MPROJ_L1L2DE_D4PHIB_DELAY \ + MPROJ_L1L2DE_D4PHIB \ + MPROJ_L1L2F_D4PHIB_DELAY \ + MPROJ_L1L2F_D4PHIB \ + MPROJ_L1L2G_D4PHIB_DELAY \ + MPROJ_L1L2G_D4PHIB \ + MPROJ_L1L2HI_D4PHIB_DELAY \ + MPROJ_L1L2HI_D4PHIB \ + MPROJ_L2L3ABCD_D4PHIB_DELAY \ + MPROJ_L2L3ABCD_D4PHIB \ + MPROJ_D1D2ABCD_D4PHIB_DELAY \ + MPROJ_D1D2ABCD_D4PHIB \ + MPROJ_L1D1ABCD_D4PHIB_DELAY \ + MPROJ_L1D1ABCD_D4PHIB \ + MPROJ_L1D1EFGH_D4PHIB_DELAY \ + MPROJ_L1D1EFGH_D4PHIB \ + MPROJ_L2D1ABCD_D4PHIB_DELAY \ + MPROJ_L2D1ABCD_D4PHIB \ + ]] + +create_pblock pblock_MPD4C +add_cells_to_pblock [get_pblocks pblock_MPD4C] [get_cells -quiet [list \ + MP_D4PHIC \ + AS_D4PHICn2_DELAY \ + AS_D4PHICn2 \ + VMSME_D4PHICn2_DELAY \ + VMSME_D4PHICn2 \ + MPROJ_L1L2DE_D4PHIC_DELAY \ + MPROJ_L1L2DE_D4PHIC \ + MPROJ_L1L2F_D4PHIC_DELAY \ + MPROJ_L1L2F_D4PHIC \ + MPROJ_L1L2G_D4PHIC_DELAY \ + MPROJ_L1L2G_D4PHIC \ + MPROJ_L1L2HI_D4PHIC_DELAY \ + MPROJ_L1L2HI_D4PHIC \ + MPROJ_L1L2JKL_D4PHIC_DELAY \ + MPROJ_L1L2JKL_D4PHIC \ + MPROJ_L2L3ABCD_D4PHIC_DELAY \ + MPROJ_L2L3ABCD_D4PHIC \ + MPROJ_D1D2ABCD_D4PHIC_DELAY \ + MPROJ_D1D2ABCD_D4PHIC \ + MPROJ_L1D1ABCD_D4PHIC_DELAY \ + MPROJ_L1D1ABCD_D4PHIC \ + MPROJ_L1D1EFGH_D4PHIC_DELAY \ + MPROJ_L1D1EFGH_D4PHIC \ + MPROJ_L2D1ABCD_D4PHIC_DELAY \ + MPROJ_L2D1ABCD_D4PHIC \ + ]] + +create_pblock pblock_MPD4D +add_cells_to_pblock [get_pblocks pblock_MPD4D] [get_cells -quiet [list \ + MP_D4PHID \ + AS_D4PHIDn2_DELAY \ + AS_D4PHIDn2 \ + VMSME_D4PHIDn2_DELAY \ + VMSME_D4PHIDn2 \ + MPROJ_L1L2G_D4PHID_DELAY \ + MPROJ_L1L2G_D4PHID \ + MPROJ_L1L2HI_D4PHID_DELAY \ + MPROJ_L1L2HI_D4PHID \ + MPROJ_L1L2JKL_D4PHID_DELAY \ + MPROJ_L1L2JKL_D4PHID \ + MPROJ_L2L3ABCD_D4PHID_DELAY \ + MPROJ_L2L3ABCD_D4PHID \ + MPROJ_D1D2ABCD_D4PHID_DELAY \ + MPROJ_D1D2ABCD_D4PHID \ + MPROJ_L1D1EFGH_D4PHID_DELAY \ + MPROJ_L1D1EFGH_D4PHID \ + MPROJ_L2D1ABCD_D4PHID_DELAY \ + MPROJ_L2D1ABCD_D4PHID \ + ]] + +create_pblock pblock_MPD5A +add_cells_to_pblock [get_pblocks pblock_MPD5A] [get_cells -quiet [list \ + MP_D5PHIA \ + AS_D5PHIAn2_DELAY \ + AS_D5PHIAn2 \ + VMSME_D5PHIAn2_DELAY \ + VMSME_D5PHIAn2 \ + MPROJ_D1D2ABCD_D5PHIA_DELAY \ + MPROJ_D1D2ABCD_D5PHIA \ + MPROJ_D3D4ABCD_D5PHIA_DELAY \ + MPROJ_D3D4ABCD_D5PHIA \ + MPROJ_L1D1ABCD_D5PHIA_DELAY \ + MPROJ_L1D1ABCD_D5PHIA \ + ]] + +create_pblock pblock_MPD5B +add_cells_to_pblock [get_pblocks pblock_MPD5B] [get_cells -quiet [list \ + MP_D5PHIB \ + AS_D5PHIBn2_DELAY \ + AS_D5PHIBn2 \ + VMSME_D5PHIBn2_DELAY \ + VMSME_D5PHIBn2 \ + MPROJ_D1D2ABCD_D5PHIB_DELAY \ + MPROJ_D1D2ABCD_D5PHIB \ + MPROJ_D3D4ABCD_D5PHIB_DELAY \ + MPROJ_D3D4ABCD_D5PHIB \ + MPROJ_L1D1ABCD_D5PHIB_DELAY \ + MPROJ_L1D1ABCD_D5PHIB \ + MPROJ_L1D1EFGH_D5PHIB_DELAY \ + MPROJ_L1D1EFGH_D5PHIB \ + ]] + +create_pblock pblock_MPD5C +add_cells_to_pblock [get_pblocks pblock_MPD5C] [get_cells -quiet [list \ + MP_D5PHIC \ + AS_D5PHICn2_DELAY \ + AS_D5PHICn2 \ + VMSME_D5PHICn2_DELAY \ + VMSME_D5PHICn2 \ + MPROJ_D1D2ABCD_D5PHIC_DELAY \ + MPROJ_D1D2ABCD_D5PHIC \ + MPROJ_D3D4ABCD_D5PHIC_DELAY \ + MPROJ_D3D4ABCD_D5PHIC \ + MPROJ_L1D1ABCD_D5PHIC_DELAY \ + MPROJ_L1D1ABCD_D5PHIC \ + MPROJ_L1D1EFGH_D5PHIC_DELAY \ + MPROJ_L1D1EFGH_D5PHIC \ + ]] + +create_pblock pblock_MPD5D +add_cells_to_pblock [get_pblocks pblock_MPD5D] [get_cells -quiet [list \ + MP_D5PHID \ + AS_D5PHIDn2_DELAY \ + AS_D5PHIDn2 \ + VMSME_D5PHIDn2_DELAY \ + VMSME_D5PHIDn2 \ + MPROJ_D1D2ABCD_D5PHID_DELAY \ + MPROJ_D1D2ABCD_D5PHID \ + MPROJ_D3D4ABCD_D5PHID_DELAY \ + MPROJ_D3D4ABCD_D5PHID \ + MPROJ_L1D1EFGH_D5PHID_DELAY \ + MPROJ_L1D1EFGH_D5PHID \ + ]] + +resize_pblock [get_pblocks pblock_MPD1A] -add {CLOCKREGION_X2Y4:CLOCKREGION_X6Y7} +resize_pblock [get_pblocks pblock_MPD1B] -add {CLOCKREGION_X2Y4:CLOCKREGION_X6Y7} +resize_pblock [get_pblocks pblock_MPD1C] -add {CLOCKREGION_X2Y4:CLOCKREGION_X6Y7} +resize_pblock [get_pblocks pblock_MPD1D] -add {CLOCKREGION_X2Y4:CLOCKREGION_X6Y7} + +resize_pblock [get_pblocks pblock_MPD2A] -add {CLOCKREGION_X2Y4:CLOCKREGION_X6Y7} +resize_pblock [get_pblocks pblock_MPD2B] -add {CLOCKREGION_X2Y4:CLOCKREGION_X6Y7} +resize_pblock [get_pblocks pblock_MPD2C] -add {CLOCKREGION_X2Y4:CLOCKREGION_X6Y7} +resize_pblock [get_pblocks pblock_MPD2D] -add {CLOCKREGION_X2Y4:CLOCKREGION_X6Y7} + +resize_pblock [get_pblocks pblock_MPD3A] -add {CLOCKREGION_X2Y4:CLOCKREGION_X6Y7} +resize_pblock [get_pblocks pblock_MPD3B] -add {CLOCKREGION_X2Y4:CLOCKREGION_X6Y7} +resize_pblock [get_pblocks pblock_MPD3C] -add {CLOCKREGION_X2Y4:CLOCKREGION_X6Y7} +resize_pblock [get_pblocks pblock_MPD3D] -add {CLOCKREGION_X2Y4:CLOCKREGION_X6Y7} + +resize_pblock [get_pblocks pblock_MPD4A] -add {CLOCKREGION_X2Y4:CLOCKREGION_X6Y7} +resize_pblock [get_pblocks pblock_MPD4B] -add {CLOCKREGION_X2Y4:CLOCKREGION_X6Y7} +resize_pblock [get_pblocks pblock_MPD4C] -add {CLOCKREGION_X2Y4:CLOCKREGION_X6Y7} +resize_pblock [get_pblocks pblock_MPD4D] -add {CLOCKREGION_X2Y4:CLOCKREGION_X6Y7} + +resize_pblock [get_pblocks pblock_MPD5A] -add {CLOCKREGION_X2Y4:CLOCKREGION_X6Y7} +resize_pblock [get_pblocks pblock_MPD5B] -add {CLOCKREGION_X2Y4:CLOCKREGION_X6Y7} +resize_pblock [get_pblocks pblock_MPD5C] -add {CLOCKREGION_X2Y4:CLOCKREGION_X6Y7} +resize_pblock [get_pblocks pblock_MPD5D] -add {CLOCKREGION_X2Y4:CLOCKREGION_X6Y7} + +create_pblock pblock_TBAAAA +add_cells_to_pblock [get_pblocks pblock_TBAAAA] [get_cells -quiet [list \ + TB_AAAA \ + FM_AAAA_L1PHIA_DELAY \ + FM_AAAA_L1PHIA \ + FM_AAAA_L1PHIB_DELAY \ + FM_AAAA_L1PHIB \ + FM_AAAA_L1PHIC_DELAY \ + FM_AAAA_L1PHIC \ + FM_AAAA_L1PHID_DELAY \ + FM_AAAA_L1PHID \ + FM_AAAA_L1PHIE_DELAY \ + FM_AAAA_L1PHIE \ + FM_AAAA_L1PHIF_DELAY \ + FM_AAAA_L1PHIF \ + FM_AAAA_L1PHIG_DELAY \ + FM_AAAA_L1PHIG \ + FM_AAAA_L1PHIH_DELAY \ + FM_AAAA_L1PHIH \ + FM_AAAA_L2PHIA_DELAY \ + FM_AAAA_L2PHIA \ + FM_AAAA_L2PHIB_DELAY \ + FM_AAAA_L2PHIB \ + FM_AAAA_L2PHIC_DELAY \ + FM_AAAA_L2PHIC \ + FM_AAAA_L2PHID_DELAY \ + FM_AAAA_L2PHID \ + FM_AAAA_L3PHIA_DELAY \ + FM_AAAA_L3PHIA \ + FM_AAAA_L3PHIB_DELAY \ + FM_AAAA_L3PHIB \ + FM_AAAA_L3PHIC_DELAY \ + FM_AAAA_L3PHIC \ + FM_AAAA_L3PHID_DELAY \ + FM_AAAA_L3PHID \ + FM_AAAA_L4PHIA_DELAY \ + FM_AAAA_L4PHIA \ + FM_AAAA_L4PHIB_DELAY \ + FM_AAAA_L4PHIB \ + FM_AAAA_L4PHIC_DELAY \ + FM_AAAA_L4PHIC \ + FM_AAAA_L4PHID_DELAY \ + FM_AAAA_L4PHID \ + FM_AAAA_L5PHIA_DELAY \ + FM_AAAA_L5PHIA \ + FM_AAAA_L5PHIB_DELAY \ + FM_AAAA_L5PHIB \ + FM_AAAA_L5PHIC_DELAY \ + FM_AAAA_L5PHIC \ + FM_AAAA_L5PHID_DELAY \ + FM_AAAA_L5PHID \ + FM_AAAA_L6PHIA_DELAY \ + FM_AAAA_L6PHIA \ + FM_AAAA_L6PHIB_DELAY \ + FM_AAAA_L6PHIB \ + FM_AAAA_L6PHIC_DELAY \ + FM_AAAA_L6PHIC \ + FM_AAAA_L6PHID_DELAY \ + FM_AAAA_L6PHID \ + FM_AAAA_D1PHIA_DELAY \ + FM_AAAA_D1PHIA \ + FM_AAAA_D1PHIB_DELAY \ + FM_AAAA_D1PHIB \ + FM_AAAA_D1PHIC_DELAY \ + FM_AAAA_D1PHIC \ + FM_AAAA_D1PHID_DELAY \ + FM_AAAA_D1PHID \ + FM_AAAA_D2PHIA_DELAY \ + FM_AAAA_D2PHIA \ + FM_AAAA_D2PHIB_DELAY \ + FM_AAAA_D2PHIB \ + FM_AAAA_D2PHIC_DELAY \ + FM_AAAA_D2PHIC \ + FM_AAAA_D2PHID_DELAY \ + FM_AAAA_D2PHID \ + FM_AAAA_D3PHIA_DELAY \ + FM_AAAA_D3PHIA \ + FM_AAAA_D3PHIB_DELAY \ + FM_AAAA_D3PHIB \ + FM_AAAA_D3PHIC_DELAY \ + FM_AAAA_D3PHIC \ + FM_AAAA_D3PHID_DELAY \ + FM_AAAA_D3PHID \ + FM_AAAA_D4PHIA_DELAY \ + FM_AAAA_D4PHIA \ + FM_AAAA_D4PHIB_DELAY \ + FM_AAAA_D4PHIB \ + FM_AAAA_D4PHIC_DELAY \ + FM_AAAA_D4PHIC \ + FM_AAAA_D4PHID_DELAY \ + FM_AAAA_D4PHID \ + FM_AAAA_D5PHIA_DELAY \ + FM_AAAA_D5PHIA \ + FM_AAAA_D5PHIB_DELAY \ + FM_AAAA_D5PHIB \ + FM_AAAA_D5PHIC_DELAY \ + FM_AAAA_D5PHIC \ + FM_AAAA_D5PHID_DELAY \ + FM_AAAA_D5PHID \ + MPAR_L1L2ABC_DELAY \ + MPAR_L1L2ABC \ + MPAR_L1L2DE_DELAY \ + MPAR_L1L2DE \ + MPAR_L1L2F_DELAY \ + MPAR_L1L2F \ + MPAR_L1L2G_DELAY \ + MPAR_L1L2G \ + MPAR_L1L2HI_DELAY \ + MPAR_L1L2HI \ + MPAR_L1L2JKL_DELAY \ + MPAR_L1L2JKL \ + MPAR_L2L3ABCD_DELAY \ + MPAR_L2L3ABCD \ + MPAR_L5L6ABCD_DELAY \ + MPAR_L5L6ABCD \ + MPAR_L2D1ABCD_DELAY \ + MPAR_L2D1ABCD \ + ]] + +create_pblock pblock_TBBBBB +add_cells_to_pblock [get_pblocks pblock_TBBBBB] [get_cells -quiet [list \ + TB_BBBB \ + FM_BBBB_L1PHIA_DELAY \ + FM_BBBB_L1PHIA \ + FM_BBBB_L1PHIB_DELAY \ + FM_BBBB_L1PHIB \ + FM_BBBB_L1PHIC_DELAY \ + FM_BBBB_L1PHIC \ + FM_BBBB_L1PHID_DELAY \ + FM_BBBB_L1PHID \ + FM_BBBB_L1PHIE_DELAY \ + FM_BBBB_L1PHIE \ + FM_BBBB_L1PHIF_DELAY \ + FM_BBBB_L1PHIF \ + FM_BBBB_L1PHIG_DELAY \ + FM_BBBB_L1PHIG \ + FM_BBBB_L1PHIH_DELAY \ + FM_BBBB_L1PHIH \ + FM_BBBB_L2PHIA_DELAY \ + FM_BBBB_L2PHIA \ + FM_BBBB_L2PHIB_DELAY \ + FM_BBBB_L2PHIB \ + FM_BBBB_L2PHIC_DELAY \ + FM_BBBB_L2PHIC \ + FM_BBBB_L2PHID_DELAY \ + FM_BBBB_L2PHID \ + FM_BBBB_L3PHIA_DELAY \ + FM_BBBB_L3PHIA \ + FM_BBBB_L3PHIB_DELAY \ + FM_BBBB_L3PHIB \ + FM_BBBB_L3PHIC_DELAY \ + FM_BBBB_L3PHIC \ + FM_BBBB_L3PHID_DELAY \ + FM_BBBB_L3PHID \ + FM_BBBB_L4PHIA_DELAY \ + FM_BBBB_L4PHIA \ + FM_BBBB_L4PHIB_DELAY \ + FM_BBBB_L4PHIB \ + FM_BBBB_L4PHIC_DELAY \ + FM_BBBB_L4PHIC \ + FM_BBBB_L4PHID_DELAY \ + FM_BBBB_L4PHID \ + FM_BBBB_L5PHIA_DELAY \ + FM_BBBB_L5PHIA \ + FM_BBBB_L5PHIB_DELAY \ + FM_BBBB_L5PHIB \ + FM_BBBB_L5PHIC_DELAY \ + FM_BBBB_L5PHIC \ + FM_BBBB_L5PHID_DELAY \ + FM_BBBB_L5PHID \ + FM_BBBB_L6PHIA_DELAY \ + FM_BBBB_L6PHIA \ + FM_BBBB_L6PHIB_DELAY \ + FM_BBBB_L6PHIB \ + FM_BBBB_L6PHIC_DELAY \ + FM_BBBB_L6PHIC \ + FM_BBBB_L6PHID_DELAY \ + FM_BBBB_L6PHID \ + FM_BBBB_D1PHIA_DELAY \ + FM_BBBB_D1PHIA \ + FM_BBBB_D1PHIB_DELAY \ + FM_BBBB_D1PHIB \ + FM_BBBB_D1PHIC_DELAY \ + FM_BBBB_D1PHIC \ + FM_BBBB_D1PHID_DELAY \ + FM_BBBB_D1PHID \ + FM_BBBB_D2PHIA_DELAY \ + FM_BBBB_D2PHIA \ + FM_BBBB_D2PHIB_DELAY \ + FM_BBBB_D2PHIB \ + FM_BBBB_D2PHIC_DELAY \ + FM_BBBB_D2PHIC \ + FM_BBBB_D2PHID_DELAY \ + FM_BBBB_D2PHID \ + FM_BBBB_D3PHIA_DELAY \ + FM_BBBB_D3PHIA \ + FM_BBBB_D3PHIB_DELAY \ + FM_BBBB_D3PHIB \ + FM_BBBB_D3PHIC_DELAY \ + FM_BBBB_D3PHIC \ + FM_BBBB_D3PHID_DELAY \ + FM_BBBB_D3PHID \ + FM_BBBB_D4PHIA_DELAY \ + FM_BBBB_D4PHIA \ + FM_BBBB_D4PHIB_DELAY \ + FM_BBBB_D4PHIB \ + FM_BBBB_D4PHIC_DELAY \ + FM_BBBB_D4PHIC \ + FM_BBBB_D4PHID_DELAY \ + FM_BBBB_D4PHID \ + FM_BBBB_D5PHIA_DELAY \ + FM_BBBB_D5PHIA \ + FM_BBBB_D5PHIB_DELAY \ + FM_BBBB_D5PHIB \ + FM_BBBB_D5PHIC_DELAY \ + FM_BBBB_D5PHIC \ + FM_BBBB_D5PHID_DELAY \ + FM_BBBB_D5PHID \ + MPAR_L3L4AB_DELAY \ + MPAR_L3L4AB \ + MPAR_L3L4CD_DELAY \ + MPAR_L3L4CD \ + MPAR_D1D2ABCD_DELAY \ + MPAR_D1D2ABCD \ + MPAR_D3D4ABCD_DELAY \ + MPAR_D3D4ABCD \ + MPAR_L1D1AB_DELAY \ + MPAR_L1D1AB \ + MPAR_L1D1CD_DELAY \ + MPAR_L1D1CD \ + ]] + + +resize_pblock [get_pblocks pblock_TBAAAA] -add {CLOCKREGION_X1Y0:CLOCKREGION_X2Y7} +resize_pblock [get_pblocks pblock_TBBBBB] -add {CLOCKREGION_X1Y0:CLOCKREGION_X2Y7} + +set_property IS_SOFT FALSE [get_pblocks pblock_*] + + diff --git a/IntegrationTests/ReducedCombinedConfig_FPGA2/script/makeProject.tcl b/IntegrationTests/ReducedCombinedConfig_FPGA2/script/makeProject.tcl new file mode 100644 index 00000000000..e21741c72f3 --- /dev/null +++ b/IntegrationTests/ReducedCombinedConfig_FPGA2/script/makeProject.tcl @@ -0,0 +1,89 @@ +# Create Vivado project, with user HDL files & IP. +# Run this in IntegrationTests/xyz/script/ + +# Create project +set projName "Work" +set FPGA "xcvu13p-flga2577-2-e" +create_project -force ${projName} ./${projName} -part $FPGA +set_property target_language VHDL [current_project] + +# Rebuild user HLS IP repos index before adding any source files +set_property ip_repo_paths "./" [get_filesets sources_1] +update_ip_catalog -rebuild + +# Create .xci files for user HLS IP + +create_ip -name ProjectionCalculator_L5L6ABCD -module_name PC_L5L6ABCD -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMStubMERouterTop_L1PHIA -module_name VMSMER_L1PHIA -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMStubMERouterTop_L1PHIB -module_name VMSMER_L1PHIB -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMStubMERouterTop_L1PHIC -module_name VMSMER_L1PHIC -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMStubMERouterTop_L1PHID -module_name VMSMER_L1PHID -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMStubMERouterTop_L1PHIE -module_name VMSMER_L1PHIE -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMStubMERouterTop_L1PHIF -module_name VMSMER_L1PHIF -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMStubMERouterTop_L1PHIG -module_name VMSMER_L1PHIG -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMStubMERouterTop_L1PHIH -module_name VMSMER_L1PHIH -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMStubMERouterTop_L2PHIA -module_name VMSMER_L2PHIA -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMStubMERouterTop_L2PHIB -module_name VMSMER_L2PHIB -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMStubMERouterTop_L2PHIC -module_name VMSMER_L2PHIC -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMStubMERouterTop_L2PHID -module_name VMSMER_L2PHID -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMStubMERouterTop_L3PHIA -module_name VMSMER_L3PHIA -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMStubMERouterTop_L3PHIB -module_name VMSMER_L3PHIB -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMStubMERouterTop_L3PHIC -module_name VMSMER_L3PHIC -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMStubMERouterTop_L3PHID -module_name VMSMER_L3PHID -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMStubMERouterTop_L4PHIA -module_name VMSMER_L4PHIA -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMStubMERouterTop_L4PHIB -module_name VMSMER_L4PHIB -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMStubMERouterTop_L4PHIC -module_name VMSMER_L4PHIC -vendor xilinx.com -library hls -version 1.0 +create_ip -name VMStubMERouterTop_L4PHID -module_name VMSMER_L4PHID -vendor xilinx.com -library hls -version 1.0 +create_ip -name MatchProcessor_L1PHIA -module_name MP_L1PHIA -vendor xilinx.com -library hls -version 1.0 +create_ip -name MatchProcessor_L1PHIB -module_name MP_L1PHIB -vendor xilinx.com -library hls -version 1.0 +create_ip -name MatchProcessor_L1PHIC -module_name MP_L1PHIC -vendor xilinx.com -library hls -version 1.0 +create_ip -name MatchProcessor_L1PHID -module_name MP_L1PHID -vendor xilinx.com -library hls -version 1.0 +create_ip -name MatchProcessor_L1PHIE -module_name MP_L1PHIE -vendor xilinx.com -library hls -version 1.0 +create_ip -name MatchProcessor_L1PHIF -module_name MP_L1PHIF -vendor xilinx.com -library hls -version 1.0 +create_ip -name MatchProcessor_L1PHIG -module_name MP_L1PHIG -vendor xilinx.com -library hls -version 1.0 +create_ip -name MatchProcessor_L1PHIH -module_name MP_L1PHIH -vendor xilinx.com -library hls -version 1.0 +create_ip -name MatchProcessor_L2PHIA -module_name MP_L2PHIA -vendor xilinx.com -library hls -version 1.0 +create_ip -name MatchProcessor_L2PHIB -module_name MP_L2PHIB -vendor xilinx.com -library hls -version 1.0 +create_ip -name MatchProcessor_L2PHIC -module_name MP_L2PHIC -vendor xilinx.com -library hls -version 1.0 +create_ip -name MatchProcessor_L2PHID -module_name MP_L2PHID -vendor xilinx.com -library hls -version 1.0 +create_ip -name MatchProcessor_L3PHIA -module_name MP_L3PHIA -vendor xilinx.com -library hls -version 1.0 +create_ip -name MatchProcessor_L3PHIB -module_name MP_L3PHIB -vendor xilinx.com -library hls -version 1.0 +create_ip -name MatchProcessor_L3PHIC -module_name MP_L3PHIC -vendor xilinx.com -library hls -version 1.0 +create_ip -name MatchProcessor_L3PHID -module_name MP_L3PHID -vendor xilinx.com -library hls -version 1.0 +create_ip -name MatchProcessor_L4PHIA -module_name MP_L4PHIA -vendor xilinx.com -library hls -version 1.0 +create_ip -name MatchProcessor_L4PHIB -module_name MP_L4PHIB -vendor xilinx.com -library hls -version 1.0 +create_ip -name MatchProcessor_L4PHIC -module_name MP_L4PHIC -vendor xilinx.com -library hls -version 1.0 +create_ip -name MatchProcessor_L4PHID -module_name MP_L4PHID -vendor xilinx.com -library hls -version 1.0 +create_ip -name TrackBuilder_AAAA -module_name TB_AAAA -vendor xilinx.com -library hls -version 1.0 + +# Provide name of top-level HDL (without .vhd extension). +#set topLevelHDL "SectorProcessor" +set topLevelHDL "SectorProcessorFull" + +# Add HDL for algo +add_files -fileset sources_1 [glob ../hdl/SectorProcessor.vhd] +add_files -fileset sources_1 [glob ../hdl/SectorProcessorFull.vhd] +add_files -fileset sources_1 [glob ../hdl/memUtil_pkg.vhd] +add_files -fileset sources_1 [glob common/hdl/*.vhd] +remove_files -fileset sources_1 [glob common/hdl/latency_monitor.vhd] +remove_files -fileset sources_1 [glob common/hdl/tf_mem_new.vhd] + + +# Add HDL for TB +add_files -fileset sim_1 [glob ../tb/tb_tf_top.vhd] + +# Add constraints (clock etc.) +add_files -fileset constrs_1 [glob common/hdl/constraints.xdc] +add_files -fileset constrs_1 [glob floorplan.xdc] + +# Set 'sim_1' fileset properties +set_property file_type {VHDL 2008} [get_files -filter {FILE_TYPE == VHDL}] +set_property top -value ${topLevelHDL} -objects [get_filesets sim_1] +set_property top -value "tb_tf_top" -objects [get_filesets sim_1] +set_property xsim.simulate.runtime -value "0us" -objects [get_filesets sim_1] + +update_compile_order -fileset sources_1 + +puts "INFO: Project created: ${projName}" + +exit diff --git a/IntegrationTests/CombinedBarrelConfig/script/runSim.tcl b/IntegrationTests/ReducedCombinedConfig_FPGA2/script/runSim.tcl similarity index 96% rename from IntegrationTests/CombinedBarrelConfig/script/runSim.tcl rename to IntegrationTests/ReducedCombinedConfig_FPGA2/script/runSim.tcl index d63c52f28ff..a6329aeba73 100644 --- a/IntegrationTests/CombinedBarrelConfig/script/runSim.tcl +++ b/IntegrationTests/ReducedCombinedConfig_FPGA2/script/runSim.tcl @@ -16,4 +16,4 @@ open_wave_config {../tb/start_bx.wcfg} restart # Need 4us + 0.45us per event (50us for 100 events, but 10us for quick test). -run 50 us +run 50.0 us diff --git a/IntegrationTests/ReducedCombinedConfig_FPGA2/tb/start_bx.wcfg b/IntegrationTests/ReducedCombinedConfig_FPGA2/tb/start_bx.wcfg new file mode 100644 index 00000000000..2d693edb473 --- /dev/null +++ b/IntegrationTests/ReducedCombinedConfig_FPGA2/tb/start_bx.wcfg @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + clk + clk + + + MP_done + MP_done + + + ap_start + ap_start + + + ap_done + ap_done + + + instubdata_dataarray_0_data_V_address0[10:0] + instubdata_dataarray_0_data_V_address0[10:0] + + + projin_0_dataarray_data_V_address0[9:0] + projin_0_dataarray_data_V_address0[9:0] + + + ap_start + ap_start + + + ap_start + ap_start + + + PC_start + PC_start + + + MP_start + MP_start + + + PC_bx_out[2:0] + PC_bx_out[2:0] + + + bx_V[2:0] + bx_V[2:0] + + diff --git a/IntegrationTests/common/hdl/FileReader.vhd b/IntegrationTests/common/hdl/FileReader.vhd index a556d1dbaed..65331da0435 100644 --- a/IntegrationTests/common/hdl/FileReader.vhd +++ b/IntegrationTests/common/hdl/FileReader.vhd @@ -24,18 +24,19 @@ use work.tf_pkg.all; entity FileReader is generic ( - FILE_NAME : string; --! Name of .txt file corresponding to memory content - DELAY : natural := 0; --! Delay output signals by this many clocks. - RAM_WIDTH : natural := 18; --! RAM data width - NUM_PAGES : natural := 2; --! Number of pages in RAM memory - NUM_TPAGES : natural := 1; --! Number of bins in RAM memory (1 if unbinned) - NUM_BINS : natural := 1; --! Number of bins in RAM memory (1 if unbinned) - DEBUG : boolean := false; --! Debug printout + FILE_NAME : string; --! Name of .txt file corresponding to memory content + PAGE_LENGTH : natural := PAGE_LENGTH; --! Page size + DELAY : natural := 0; --! Delay output signals by this many clocks. + RAM_WIDTH : natural := 18; --! RAM data width + NUM_PAGES : natural := 2; --! Number of pages in RAM memory + NUM_TPAGES : natural := 1; --! Number of bins in RAM memory (1 if unbinned) + NUM_BINS : natural := 1; --! Number of bins in RAM memory (1 if unbinned) + DEBUG : boolean := false; --! Debug printout FILE_NAME_DEBUG : string := ""; --! Name of .txt file for debug printout. -- Leave following parameters at their default values. - RAM_DEPTH : natural := NUM_PAGES*NUM_TPAGES*PAGE_LENGTH; --! RAM depth (no. of entries) - ADDR_WIDTH : natural := clogb2(RAM_DEPTH); --! RAM address - BIN_SIZE : natural := NUM_TPAGES*PAGE_LENGTH/NUM_BINS --! Max. entries per RAM bin + RAM_DEPTH : natural := NUM_PAGES*NUM_TPAGES*PAGE_LENGTH; --! RAM depth (no. of entries) + ADDR_WIDTH : natural := clogb2(RAM_DEPTH); --! RAM address + BIN_SIZE : natural := NUM_TPAGES*PAGE_LENGTH/NUM_BINS --! Max. entries per RAM bin ); port ( CLK : in std_logic; @@ -192,10 +193,7 @@ begin DATA <= emDATA(RAM_WIDTH-1 downto 0); if (NUM_BINS > 1) then -- Binned memory - ADDR <= std_logic_vector(to_unsigned(POS_IN_MEM_BIN + BIN_SIZE*MEM_BIN + PAGE_LENGTH*PAGE, ADDR_WIDTH)); - else - -- Unbinned memory - ADDR <= std_logic_vector(to_unsigned(DATA_CNT + PAGE_LENGTH*PAGE, ADDR_WIDTH)); + ADDR <= std_logic_vector(to_unsigned(MEM_BIN, ADDR_WIDTH)); end if; WRITE_EN <= '1'; DATA_CNT := DATA_CNT + 1; diff --git a/IntegrationTests/common/hdl/FileWriter.vhd b/IntegrationTests/common/hdl/FileWriter.vhd index 092051dc2a5..1c21fe941be 100644 --- a/IntegrationTests/common/hdl/FileWriter.vhd +++ b/IntegrationTests/common/hdl/FileWriter.vhd @@ -26,6 +26,8 @@ entity FileWriter is PAGE_LENGTH : natural := PAGE_LENGTH; --! Page length -- Leave following parameters at their default values. RAM_DEPTH : natural := NUM_TPAGES*NUM_PAGES*PAGE_LENGTH; --! RAM depth (no. of entries) + CLK_CNT_INIT : integer := 0; --! allows to set offset to allign with BX + --change ADDR_WIDTH : natural := clogb2(RAM_DEPTH) --! RAM address ); port ( @@ -50,6 +52,7 @@ procFile : process(CLK) file FILE_OUT : text; variable LINE_OUT : line; variable BX_CNT : natural := 0; --! Event counter + variable CLK_CNT : integer := CLK_CNT_INIT; --! Clock counter constant TXT_WIDTH : natural := 11; --! Column width in output .txt file function to_hexstring ( VAR : std_logic_vector) return string is @@ -97,14 +100,17 @@ begin writeline(FILE_OUT, LINE_OUT); end if; - if (DONE = '1') then + if (CLK_CNT = MAX_ENTRIES - 1) then -- Module has finished event, so increment event counter. BX_CNT := BX_CNT + 1; + CLK_CNT := 0; if (BX_CNT = MAX_EVENTS) then -- All events processed, so close file. file_close(FILE_OUT); end if; + else + CLK_CNT := CLK_CNT + 1; end if; end if; end if; diff --git a/IntegrationTests/common/hdl/FileWriterFIFO.vhd b/IntegrationTests/common/hdl/FileWriterFIFO.vhd index 9c9ba87a2c5..ee71df3de90 100644 --- a/IntegrationTests/common/hdl/FileWriterFIFO.vhd +++ b/IntegrationTests/common/hdl/FileWriterFIFO.vhd @@ -65,7 +65,7 @@ begin write(LINE_OUT, string'("TIME (ns)"), right, TXT_WIDTH); write(LINE_OUT, string'("BX") , right, TXT_WIDTH); write(LINE_OUT, string'("ADDR") , right, TXT_WIDTH); - write(LINE_OUT, string'("DATA") , right, 11*TXT_WIDTH); + write(LINE_OUT, string'("DATA") , right, TXT_WIDTH); writeline(FILE_OUT, LINE_OUT); end if; @@ -75,8 +75,8 @@ begin -- Valid data, so write it to file. write(LINE_OUT, NOW , right, TXT_WIDTH); write(LINE_OUT, BX_CNT, right, TXT_WIDTH); - write(LINE_OUT, to_hexstring(ADDR), right, TXT_WIDTH); - write(LINE_OUT, to_hexstring(DATA), right, 11*TXT_WIDTH); + write(LINE_OUT, to_hexstring(ADDR)&" ", right, TXT_WIDTH); + write(LINE_OUT, to_hexstring(DATA), right, 1+to_hexstring(DATA)'length); writeline(FILE_OUT, LINE_OUT); ADDR := std_logic_vector(unsigned(ADDR) + "1"); end if; diff --git a/IntegrationTests/common/hdl/mem_reader.vhd b/IntegrationTests/common/hdl/mem_reader.vhd index 50a21754f45..4e4e5a5914b 100644 --- a/IntegrationTests/common/hdl/mem_reader.vhd +++ b/IntegrationTests/common/hdl/mem_reader.vhd @@ -28,6 +28,8 @@ use work.tf_pkg.all; entity mem_reader is generic ( + PAGE_LENGTH : natural := PAGE_LENGTH; --! 64 for paged MPROJ memories, + --! otherwise 128 RAM_WIDTH : natural := 36; --! Specify RAM data width NUM_PAGES : natural := 8; --! Specify no. Pages in RAM --memory --FIXME should be 2 @@ -45,8 +47,9 @@ entity mem_reader is din : in std_logic_vector(RAM_WIDTH-1 downto 0); --! RAM input data dout : out std_logic_vector(RAM_WIDTH-1 downto 0); --! output data valid : out std_logic; --! data valid - index : out std_logic_vector(6+clogb2(NUM_TPAGES) downto 0); --!index - nent : in t_arr_7b(0 to NUM_PAGES*NUM_TPAGES-1) + index : out std_logic_vector(clogb2(NUM_TPAGES*PAGE_LENGTH)-1 downto 0); --!index + nent : in t_arr_7b(0 to NUM_PAGES*NUM_TPAGES-1); + mask : in t_arr_4b(0 to NUM_PAGES-1) ); end mem_reader; @@ -84,6 +87,12 @@ begin if (start='1') then + --report "mem_reader: "&time'image(now)&" "&NAME&" start bx="&to_bstring(bx); + if (NUM_TPAGES = 1) then + --report "mem_reader: "&time'image(now)&" "&NAME&" start bx="&to_bstring(bx)&" nent=" + -- &to_bstring(nent(0))&" " + -- &to_bstring(nent(1)); + end if; if (NUM_TPAGES = 4) then --report "mem_reader: "&time'image(now)&" "&NAME&" start bx="&to_bstring(bx)&" nent=" -- &to_bstring(nent(0))&" " @@ -141,29 +150,29 @@ begin valid2 <= valid1; - if (addrP1var < nent(to_integer(unsigned(bx))*NUM_TPAGES) and addrP1var < maxval) then + if (addrP1var < nent(to_integer(unsigned(bx))*NUM_TPAGES) and (mask(to_integer(unsigned(bx)))(0)='1') and addrP1var < maxval) then if (NUM_TPAGES>1) then - addr_counter <= std_logic_vector(to_unsigned(0,2))&addrP1var(6 downto 0); - addra <= bx&std_logic_vector(to_unsigned(0,2))&addrP1var(6 downto 0); + addr_counter <= std_logic_vector(to_unsigned(0,2))&addrP1var; + addra <= bx&std_logic_vector(to_unsigned(0,2))&addrP1var; else addr_counter <= addrP1var(6 downto 0); addra <= bx&addrP1var(6 downto 0); end if; addrP1var := std_logic_vector(to_unsigned(to_integer(unsigned(addrP1var)) + 1, addrP1var'length)); valid1 <= '1'; - elsif ((addrP2var < nent(to_integer(unsigned(bx))*NUM_TPAGES+1)) and (NUM_TPAGES > 1) and addrP2var < maxval) then - addr_counter <= std_logic_vector(to_unsigned(1,2))&addrP2var(6 downto 0); - addra <= bx&std_logic_vector(to_unsigned(1,2))&addrP2var(6 downto 0); + elsif ((addrP2var < nent(to_integer(unsigned(bx))*NUM_TPAGES+1)) and (mask(to_integer(unsigned(bx)))(1)='1') and (NUM_TPAGES > 1) and addrP2var < maxval) then + addr_counter <= std_logic_vector(to_unsigned(1,2))&addrP2var; + addra <= bx&std_logic_vector(to_unsigned(1,2))&addrP2var; addrP2var := std_logic_vector(to_unsigned(to_integer(unsigned(addrP2var)) + 1, addrP2var'length)); valid1 <= '1'; - elsif ((addrP3var < nent(to_integer(unsigned(bx))*NUM_TPAGES+2)) and (NUM_TPAGES > 2) and addrP3var < maxval) then - addr_counter <= std_logic_vector(to_unsigned(2,2))&addrP3var(6 downto 0); - addra <= bx&std_logic_vector(to_unsigned(2,2))&addrP3var(6 downto 0); + elsif ((addrP3var < nent(to_integer(unsigned(bx))*NUM_TPAGES+2)) and (mask(to_integer(unsigned(bx)))(2)='1') and (NUM_TPAGES > 2) and addrP3var < maxval) then + addr_counter <= std_logic_vector(to_unsigned(2,2))&addrP3var; + addra <= bx&std_logic_vector(to_unsigned(2,2))&addrP3var; addrP3var := std_logic_vector(to_unsigned(to_integer(unsigned(addrP3var)) + 1, addrP3var'length)); valid1 <= '1'; - elsif ((addrP4var < nent(to_integer(unsigned(bx))*NUM_TPAGES+3)) and (NUM_TPAGES > 3) and addrP4var < maxval) then - addr_counter <= std_logic_vector(to_unsigned(3,2))&addrP4var(6 downto 0); - addra <= bx&std_logic_vector(to_unsigned(3,2))&addrP4var(6 downto 0); + elsif ((addrP4var < nent(to_integer(unsigned(bx))*NUM_TPAGES+3)) and (mask(to_integer(unsigned(bx)))(3)='1') and (NUM_TPAGES > 3) and addrP4var < maxval) then + addr_counter <= std_logic_vector(to_unsigned(3,2))&addrP4var; + addra <= bx&std_logic_vector(to_unsigned(3,2))&addrP4var; addrP4var := std_logic_vector(to_unsigned(to_integer(unsigned(addrP4var)) + 1, addrP4var'length)); valid1 <= '1'; else diff --git a/IntegrationTests/common/hdl/tf_mem.vhd b/IntegrationTests/common/hdl/tf_mem.vhd index 78bde75c1db..b7bb0aec2d7 100644 --- a/IntegrationTests/common/hdl/tf_mem.vhd +++ b/IntegrationTests/common/hdl/tf_mem.vhd @@ -118,6 +118,7 @@ process(clka) variable page : integer := 0; variable addr_in_page : integer := 0; variable address : std_logic_vector(clogb2(RAM_DEPTH)-1 downto 0); + variable overwrite : std_logic := '1'; begin if rising_edge(clka) then -- ######################################### Start counter initially if DEBUG then @@ -129,12 +130,6 @@ begin end if; end if; slv_page_cnt_save := slv_page_cnt; - if (sync_nent='1') and (init='1') then - --report time'image(now)&" tf_mem "&NAME&" sync_nent"; - init := '0'; - slv_clk_cnt := (others => '0'); - slv_page_cnt := (0 => '1', others => '0'); - end if; if (init = '0' and to_integer(unsigned(slv_clk_cnt)) < MAX_ENTRIES-1) then -- ####### Counter nent slv_clk_cnt := std_logic_vector(unsigned(slv_clk_cnt)+1); --report time'image(now)&" tf_mem "&NAME&" increment vi_clk_cnt:"&integer'image(vi_clk_cnt); @@ -152,12 +147,25 @@ begin --report time'image(now)&" tf_mem "&NAME&" will zero nent"; nent_o(to_integer(unsigned(slv_page_cnt))) <= (others => '0'); end if; + if (sync_nent='1') and (init='1') then + --report time'image(now)&" tf_mem "&NAME&" sync_nent"; + init := '0'; + slv_clk_cnt := (others => '0'); + slv_page_cnt := (0 => '1', others => '0'); + end if; if (wea='1') then + overwrite := addra(0); --vi_page_cnt_slv := std_logic_vector(to_unsigned(vi_page_cnt_save,vi_page_cnt_slv'length)); - address := slv_page_cnt_save&nent_o(to_integer(unsigned(slv_page_cnt_save))); - --report "tf_mem "&time'image(now)&" "&NAME&" page writeaddr "&" "&to_bstring(vi_page_cnt_slv)&" "&to_bstring(address)&" "&to_bstring(dina); + if (overwrite = '0') then + address := slv_page_cnt_save&nent_o(to_integer(unsigned(slv_page_cnt_save))); + else + address := slv_page_cnt_save&std_logic_vector(to_unsigned(to_integer(unsigned(nent_o(to_integer(unsigned(slv_page_cnt_save)))))-1,nent_o(to_integer(unsigned(slv_page_cnt_save)))'length)); + end if; + --report "tf_mem "&time'image(now)&" "&NAME&" page writeaddr "&" "&to_bstring(slv_page_cnt_save)&" "&to_bstring(address)&" "&to_bstring(overwrite)&" "&to_bstring(dina)&" addra "&to_bstring(addra); sa_RAM_data(to_integer(unsigned(address))) <= dina; -- Write data - nent_o(to_integer(unsigned(slv_page_cnt_save))) <= std_logic_vector(to_unsigned(to_integer(unsigned(nent_o(to_integer(unsigned(slv_page_cnt_save))))) + 1, nent_o(to_integer(unsigned(slv_page_cnt_save)))'length)); -- + 1 (slv) + if (overwrite = '0') then + nent_o(to_integer(unsigned(slv_page_cnt_save))) <= std_logic_vector(to_unsigned(to_integer(unsigned(nent_o(to_integer(unsigned(slv_page_cnt_save))))) + 1, nent_o(to_integer(unsigned(slv_page_cnt_save)))'length)); -- + 1 (slv) + end if; end if; end if; end process; diff --git a/IntegrationTests/common/hdl/tf_mem_bin.vhd b/IntegrationTests/common/hdl/tf_mem_bin.vhd index 63ac17c67b8..4602e9435ae 100644 --- a/IntegrationTests/common/hdl/tf_mem_bin.vhd +++ b/IntegrationTests/common/hdl/tf_mem_bin.vhd @@ -14,6 +14,16 @@ --! PAGE_LENGTH = BIN_DEPTH * NBIN total memory depth --! --! This memory inplements the binned, VMStubs, memories +--! +--! This memory stores VMStubs in bins of phi and r/z. When writing to +--! a memory the counter of the number of entries in each bin is incremented +--! and the bit mask for occupacy in the bin is set true. Note that when we +--! start writing to a new BX the number of entries are not reset to zero - +--! this can not be done in one clock as this is implemented as DRAM. The values +--! in the number of entries are only correct if the bin mask indicates that +--! there are stubs in a bin. Furthermore, the bin mask is also implemented +--! as a DRAM - we do have an array of registers for each r/z bin that is reset +--! when a new BX is processed. --! --! @author anders.ryd@cornell.edu (based on code from robert.glein@colorado.edu) --! @date 2023-02-02 (Groundhog day!) @@ -119,8 +129,17 @@ entity tf_mem_bin is dout_nent : out std_logic_vector(2*NUM_PHI_BINS*ADDR_WIDTH-1 downto 0); - --! mask(page)(bin) - mask_o : out std_logic_vector(NUM_BINS * NUM_PAGES-1 downto 0) := (others => '0') + enb_binmaskA : in std_logic; + enb_binmaskB : in std_logic; + + --! Address for bin mask as fcn of r/z bin and page + addr_binmaskA : in std_logic_vector(NUM_RZ_BITS+NUM_PAGES_BITS-1 downto 0); + addr_binmaskB : in std_logic_vector(NUM_RZ_BITS+NUM_PAGES_BITS-1 downto 0); + + --! binmask + binmaskA_o : out std_logic_vector(NUM_PHI_BINS - 1 downto 0); + binmaskB_o : out std_logic_vector(NUM_PHI_BINS - 1 downto 0) + ); end tf_mem_bin; @@ -139,7 +158,11 @@ architecture rtl of tf_mem_bin is type t_arr_1d_slv_mem_nent is array(0 to NUM_RZ_BINS*NUM_PAGES-1) of std_logic_vector(ADDR_WIDTH-1 downto 0); - type t_arr_2d_slv_mem_nent is array(0 to 2*NUM_PHI_BINS-1) of t_arr_1d_slv_mem_nent; --! 2D array of slv + --type t_arr_2d_slv_mem_nent is array(0 to 2*NUM_PHI_BINS-1) of t_arr_1d_slv_mem_nent; --! 2D array of slv + +--! Memory for the bin mask + type t_binmask is array(0 to NUM_RZ_BINS*NUM_PAGES - 1) of std_logic_vector(NUM_PHI_BINS - 1 downto 0); + type t_binmask_tmp is array(0 to NUM_RZ_BINS - 1) of std_logic_vector(NUM_PHI_BINS - 1 downto 0); -- ########################### Function ########################## --! @brief TextIO function to read memory data to initialize tf_mem_bin. Needed here because of variable slv width! @@ -198,33 +221,77 @@ signal sa_RAM_data : t_mem_2d_array := read_tf_mem_data_2d(INIT_FILE, INIT_HEX); signal sv_RAM_row : t_data_array := (others => (others =>'0')); --! RAM for the number of entries -signal sa_RAM_nent : t_arr_2d_slv_mem_nent := (others => (others => (others => '0'))); +signal sa_RAM_numentriesA0 : t_arr_1d_slv_mem_nent := (others => (others => '0')); +signal sa_RAM_numentriesA1 : t_arr_1d_slv_mem_nent := (others => (others => '0')); +signal sa_RAM_numentriesA2 : t_arr_1d_slv_mem_nent := (others => (others => '0')); +signal sa_RAM_numentriesA3 : t_arr_1d_slv_mem_nent := (others => (others => '0')); +signal sa_RAM_numentriesA4 : t_arr_1d_slv_mem_nent := (others => (others => '0')); +signal sa_RAM_numentriesA5 : t_arr_1d_slv_mem_nent := (others => (others => '0')); +signal sa_RAM_numentriesA6 : t_arr_1d_slv_mem_nent := (others => (others => '0')); +signal sa_RAM_numentriesA7 : t_arr_1d_slv_mem_nent := (others => (others => '0')); + +signal sa_RAM_numentriesB0 : t_arr_1d_slv_mem_nent := (others => (others => '0')); +signal sa_RAM_numentriesB1 : t_arr_1d_slv_mem_nent := (others => (others => '0')); +signal sa_RAM_numentriesB2 : t_arr_1d_slv_mem_nent := (others => (others => '0')); +signal sa_RAM_numentriesB3 : t_arr_1d_slv_mem_nent := (others => (others => '0')); +signal sa_RAM_numentriesB4 : t_arr_1d_slv_mem_nent := (others => (others => '0')); +signal sa_RAM_numentriesB5 : t_arr_1d_slv_mem_nent := (others => (others => '0')); +signal sa_RAM_numentriesB6 : t_arr_1d_slv_mem_nent := (others => (others => '0')); +signal sa_RAM_numentriesB7 : t_arr_1d_slv_mem_nent := (others => (others => '0')); signal nentry_tmp : t_arr_1d_mem_nent_tmp := (others => (others =>'0')); signal nentry_mask_tmp : std_logic_vector(NUM_BINS-1 downto 0) := (others => '0'); +--! RAM for the bin masks + +signal validbinmask : std_logic_vector(NUM_RZ_BINS*NUM_PAGES - 1 downto 0) := (others => '0'); +signal binmaskA : t_binmask := (others => (others =>'0')); +signal binmaskB : t_binmask := (others => (others =>'0')); + +signal validbinmasktmp : std_logic_vector(NUM_RZ_BINS - 1 downto 0) := (others => '0'); +signal binmasktmp : t_binmask_tmp := (others => (others =>'0')); + -- ########################### Attributes ########################### attribute ram_style : string; attribute ram_style of sa_RAM_data : signal is MEM_TYPE; -attribute ram_style of sa_RAM_nent : signal is "distributed"; +attribute ram_style of sa_RAM_numentriesA0 : signal is "distributed"; +attribute ram_style of sa_RAM_numentriesA1 : signal is "distributed"; +attribute ram_style of sa_RAM_numentriesA2 : signal is "distributed"; +attribute ram_style of sa_RAM_numentriesA3 : signal is "distributed"; +attribute ram_style of sa_RAM_numentriesA4 : signal is "distributed"; +attribute ram_style of sa_RAM_numentriesA5 : signal is "distributed"; +attribute ram_style of sa_RAM_numentriesA6 : signal is "distributed"; +attribute ram_style of sa_RAM_numentriesA7 : signal is "distributed"; +attribute ram_style of sa_RAM_numentriesB0 : signal is "distributed"; +attribute ram_style of sa_RAM_numentriesB1 : signal is "distributed"; +attribute ram_style of sa_RAM_numentriesB2 : signal is "distributed"; +attribute ram_style of sa_RAM_numentriesB3 : signal is "distributed"; +attribute ram_style of sa_RAM_numentriesB4 : signal is "distributed"; +attribute ram_style of sa_RAM_numentriesB5 : signal is "distributed"; +attribute ram_style of sa_RAM_numentriesB6 : signal is "distributed"; +attribute ram_style of sa_RAM_numentriesB7 : signal is "distributed"; attribute ram_style of nentry_tmp : signal is "distributed"; +attribute ram_style of binmaskA : signal is "distributed"; +attribute ram_style of binmaskB : signal is "distributed"; +attribute ram_style of binmasktmp : signal is "distributed"; + begin -- Check user didn't change values of derived generics. assert (RAM_DEPTH = NUM_PAGES*PAGE_LENGTH) report "User changed RAM_DEPTH" severity FAILURE; process(clka) - variable init : std_logic := '1'; -- Clock counter + variable init : std_logic := '1'; --FIXME hardcoded number variable slv_clk_cnt : std_logic_vector(6 downto 0) := (others => '0'); -- Clock counter variable slv_page_cnt : std_logic_vector(NUM_PAGES_BITS-1 downto 0) := (others => '0'); -- Page counter variable slv_page_cnt_save : std_logic_vector(NUM_PAGES_BITS-1 downto 0) := (others => '0'); -- Page counter --! Extract phi and rz bin address - alias vi_nent_idx : std_logic_vector(NUM_PHI_BITS+NUM_RZ_BITS-1 downto 0) is addra(ADDR_WIDTH + NUM_PHI_BITS + NUM_RZ_BITS - 1 downto ADDR_WIDTH); + alias vi_nent_idx : std_logic_vector(NUM_PHI_BITS+NUM_RZ_BITS-1 downto 0) is addra(NUM_PHI_BITS + NUM_RZ_BITS - 1 downto 0); --! Extract phi bin from bin address alias phibits: std_logic_vector(NUM_PHI_BITS-1 downto 0) is vi_nent_idx(NUM_PHI_BITS - 1 downto 0); @@ -232,25 +299,25 @@ process(clka) --! Extract rz bin from binaddress alias rzbits: std_logic_vector(NUM_RZ_BITS-1 downto 0) is vi_nent_idx(NUM_PHI_BITS + NUM_RZ_BITS-1 downto NUM_PHI_BITS); --rz position + variable page_rzbits: std_logic_vector(NUM_PAGES_BITS + NUM_RZ_BITS -1 downto 0); + variable binaddr : unsigned(ADDR_WIDTH-1 downto 0) := (others => '0'); variable nentry : unsigned(ADDR_WIDTH-1 downto 0) := (others => '0'); variable writeaddr : std_logic_vector(RAM_DEPTH_BITS-1 downto 0); + + variable phimask : std_logic_vector(NUM_PHI_BINS -1 downto 0) := ( 0 => '1', others => '0'); + + variable binmaskvalue : std_logic_vector(NUM_PHI_BINS -1 downto 0); begin if rising_edge(clka) then slv_page_cnt_save := slv_page_cnt; - if (sync_nent='1') and init='1' then - init := '0'; - slv_clk_cnt := (others => '0'); - slv_page_cnt := (0 => '1', others => '0'); - nentry_mask_tmp <= (others => '0'); -- Do we need this??? FIXME - --report "tf_mem_bin "&time'image(now)&" "&NAME&" sync_nent set"; - end if; if (init = '0' and to_integer(unsigned(slv_clk_cnt)) < MAX_ENTRIES-1) then -- ####### Counter nent slv_clk_cnt := std_logic_vector(unsigned(slv_clk_cnt)+1); elsif (to_integer(unsigned(slv_clk_cnt)) >= MAX_ENTRIES-1) then -- -1 not included slv_clk_cnt := (others => '0'); + validbinmasktmp <= (others => '0'); nentry_mask_tmp <= (others => '0'); -- Do we need this??? FIXME --report "tf_mem_bin "&time'image(now)&" "&NAME&" setting nentry_mask_tmp to zero"; if (to_integer(unsigned(slv_page_cnt)) < NUM_PAGES-1) then @@ -258,7 +325,17 @@ begin else slv_page_cnt := (others => '0'); end if; - mask_o(NUM_BINS*(to_integer(unsigned(slv_page_cnt))+1)-1 downto NUM_BINS*to_integer(unsigned(slv_page_cnt))) <= (others => '0'); + --report "tf_mem_bin "&time'image(now)&" "&NAME&" validbinmask: "&to_bstring(slv_page_cnt); + validbinmask(NUM_RZ_BINS*(to_integer(unsigned(slv_page_cnt))+1)-1 downto NUM_RZ_BINS*(to_integer(unsigned(slv_page_cnt)))) <= (others => '0'); + end if; + if (sync_nent='1') and init='1' then + --report time'image(now)&" tf_mem_bin "&NAME&" sync_nent"; + init := '0'; + slv_clk_cnt := (others => '0'); + slv_page_cnt := (0 => '1', others => '0'); + validbinmasktmp <= (others => '0'); + nentry_mask_tmp <= (others => '0'); -- Do we need this??? FIXME + --report "tf_mem_bin "&time'image(now)&" "&NAME&" sync_nent set"; end if; if (wea='1') then @@ -276,25 +353,88 @@ begin binaddr := "0000"; end if; - nentry_tmp(to_integer(unsigned(vi_nent_idx))) <= std_logic_vector(nentry); - nentry_mask_tmp(to_integer(unsigned(vi_nent_idx))) <= '1'; + if (binaddr /= "1111") then + + nentry_tmp(to_integer(unsigned(vi_nent_idx))) <= std_logic_vector(nentry); + nentry_mask_tmp(to_integer(unsigned(vi_nent_idx))) <= '1'; + + phimask := ( 0 => '1', others => '0'); + phimask := std_logic_vector(shift_left(unsigned(phimask), to_integer(unsigned(phibits)))); - writeaddr := slv_page_cnt_save & vi_nent_idx & std_logic_vector(binaddr); - --report "tf_mem_bin writeaddr data: " & NAME & " " & to_bstring(writeaddr) & " " & to_bstring(dina); - for icopy in 0 to NUM_COPY-1 loop - sa_RAM_data(icopy)(to_integer(unsigned(writeaddr))) <= dina; - end loop; + binmaskvalue := (binmasktmp(to_integer(unsigned(rzbits))) and validbinmasktmp(to_integer(unsigned(rzbits)))) or phimask; + + binmasktmp(to_integer(unsigned(rzbits))) <= binmaskvalue; + + page_rzbits := slv_page_cnt_save & rzbits; - --assert (page < NUM_PAGES) report "page out of range" severity error; - mask_o(to_integer(unsigned(slv_page_cnt_save))*NUM_BINS+to_integer(unsigned(vi_nent_idx))) <= '1'; -- <= 1 (slv) + binmaskA(to_integer(unsigned(page_rzbits))) <= binmaskvalue; + binmaskB(to_integer(unsigned(page_rzbits))) <= binmaskvalue; - --report "tf_mem_bin write nent :"&time'image(now)&" "&NAME&" phi:"&to_bstring(phibits)&" rz:"&to_bstring(rzbits)&" "&to_bstring(nentry)&" "&to_bstring(writeaddr); + validbinmasktmp(to_integer(unsigned(rzbits))) <= '1'; + validbinmask(to_integer(unsigned(page_rzbits))) <= '1'; + + + writeaddr := slv_page_cnt_save & vi_nent_idx & std_logic_vector(binaddr); + --report time'image(now)&" tf_mem_bin: " & NAME & " writeaddr: " & to_bstring(writeaddr) & " data: " & to_bstring(dina); + for icopy in 0 to NUM_COPY-1 loop + sa_RAM_data(icopy)(to_integer(unsigned(writeaddr))) <= dina; + end loop; + + --report "tf_mem_bin write nent :"&time'image(now)&" "&NAME&" phi:"&to_bstring(phibits)&" rz:"&to_bstring(rzbits)&" "&to_bstring(nentry)&" "&to_bstring(writeaddr); - sa_RAM_nent(to_integer(unsigned(phibits)))(to_integer(unsigned(slv_page_cnt_save))*NUM_RZ_BINS+to_integer(unsigned(rzbits))) <= std_logic_vector(nentry); -- <= address - if (unsigned(rzbits) /= 0) then - --report "tf_mem_bin write nent :"&time'image(now)&" "&NAME&" phi:"&to_bstring(phibits)&" rz:"&to_bstring(rzbits) - -- &" "&to_bstring(nentry_in_bin)&" "&to_bstring(addra); - sa_RAM_nent(to_integer(unsigned(phibits))+NUM_PHI_BINS)(to_integer(unsigned(slv_page_cnt_save))*NUM_RZ_BINS+(to_integer(unsigned(rzbits))-1)) <= std_logic_vector(nentry); -- <= address + if (to_integer(unsigned(phibits)) = 0) then + sa_RAM_numentriesA0(to_integer(unsigned(slv_page_cnt_save))*NUM_RZ_BINS+to_integer(unsigned(rzbits))) <= std_logic_vector(nentry); -- <= address + end if; + if (to_integer(unsigned(phibits)) = 1) then + sa_RAM_numentriesA1(to_integer(unsigned(slv_page_cnt_save))*NUM_RZ_BINS+to_integer(unsigned(rzbits))) <= std_logic_vector(nentry); -- <= address + end if; + if (to_integer(unsigned(phibits)) = 2) then + sa_RAM_numentriesA2(to_integer(unsigned(slv_page_cnt_save))*NUM_RZ_BINS+to_integer(unsigned(rzbits))) <= std_logic_vector(nentry); -- <= address + end if; + if (to_integer(unsigned(phibits)) = 3) then + sa_RAM_numentriesA3(to_integer(unsigned(slv_page_cnt_save))*NUM_RZ_BINS+to_integer(unsigned(rzbits))) <= std_logic_vector(nentry); -- <= address + end if; + if (to_integer(unsigned(phibits)) = 4) then + sa_RAM_numentriesA4(to_integer(unsigned(slv_page_cnt_save))*NUM_RZ_BINS+to_integer(unsigned(rzbits))) <= std_logic_vector(nentry); -- <= address + end if; + if (to_integer(unsigned(phibits)) = 5) then + sa_RAM_numentriesA5(to_integer(unsigned(slv_page_cnt_save))*NUM_RZ_BINS+to_integer(unsigned(rzbits))) <= std_logic_vector(nentry); -- <= address + end if; + if (to_integer(unsigned(phibits)) = 6) then + sa_RAM_numentriesA6(to_integer(unsigned(slv_page_cnt_save))*NUM_RZ_BINS+to_integer(unsigned(rzbits))) <= std_logic_vector(nentry); -- <= address + end if; + if (to_integer(unsigned(phibits)) = 7) then + sa_RAM_numentriesA7(to_integer(unsigned(slv_page_cnt_save))*NUM_RZ_BINS+to_integer(unsigned(rzbits))) <= std_logic_vector(nentry); -- <= address + end if; + if (unsigned(rzbits) /= 0) then + --report "tf_mem_bin write nent :"&time'image(now)&" "&NAME&" phi:"&to_bstring(phibits)&" rz:"&to_bstring(rzbits) + -- &" "&to_bstring(nentry_in_bin)&" "&to_bstring(addra); + if (to_integer(unsigned(phibits)) = 0) then + sa_RAM_numentriesB0(to_integer(unsigned(slv_page_cnt_save))*NUM_RZ_BINS+to_integer(unsigned(rzbits))-1) <= std_logic_vector(nentry); -- <= address + end if; + if (to_integer(unsigned(phibits)) = 1) then + sa_RAM_numentriesB1(to_integer(unsigned(slv_page_cnt_save))*NUM_RZ_BINS+to_integer(unsigned(rzbits))-1) <= std_logic_vector(nentry); -- <= address + end if; + if (to_integer(unsigned(phibits)) = 2) then + sa_RAM_numentriesB2(to_integer(unsigned(slv_page_cnt_save))*NUM_RZ_BINS+to_integer(unsigned(rzbits))-1) <= std_logic_vector(nentry); -- <= address + end if; + if (to_integer(unsigned(phibits)) = 3) then + sa_RAM_numentriesB3(to_integer(unsigned(slv_page_cnt_save))*NUM_RZ_BINS+to_integer(unsigned(rzbits))-1) <= std_logic_vector(nentry); -- <= address + end if; + if (to_integer(unsigned(phibits)) = 4) then + sa_RAM_numentriesB4(to_integer(unsigned(slv_page_cnt_save))*NUM_RZ_BINS+to_integer(unsigned(rzbits))-1) <= std_logic_vector(nentry); -- <= address + end if; + if (to_integer(unsigned(phibits)) = 5) then + sa_RAM_numentriesB5(to_integer(unsigned(slv_page_cnt_save))*NUM_RZ_BINS+to_integer(unsigned(rzbits))-1) <= std_logic_vector(nentry); -- <= address + end if; + if (to_integer(unsigned(phibits)) = 6) then + sa_RAM_numentriesB6(to_integer(unsigned(slv_page_cnt_save))*NUM_RZ_BINS+to_integer(unsigned(rzbits))-1) <= std_logic_vector(nentry); -- <= address + end if; + if (to_integer(unsigned(phibits)) = 7) then + sa_RAM_numentriesB7(to_integer(unsigned(slv_page_cnt_save))*NUM_RZ_BINS+to_integer(unsigned(rzbits))-1) <= std_logic_vector(nentry); -- <= address + end if; + -- sa_RAM_numentriesB(to_integer(unsigned(slv_page_cnt_save))*NUM_RZ_BINS+to_integer(unsigned(rzbits))-1)(4*to_integer(unsigned(phibits))-1 downto (to_integer(unsigned(phibits)))) <= std_logic_vector(nentry); -- <= address + end if; end if; end if; end if; @@ -309,19 +449,20 @@ begin if (enb_nent='1') then --for i in 0 to NUM_PHI_BINS-1 loop -- report "tf_mem_bin read_nent "&NAME&" "&time'image(now)&" "&integer'image(i)&" : " - -- &to_bstring(sa_RAM_nent(i)(8))&" " - -- &to_bstring(sa_RAM_nent(i)(9))&" " - -- &to_bstring(sa_RAM_nent(i)(10))&" " - -- &to_bstring(sa_RAM_nent(i)(11))&" " - -- &to_bstring(sa_RAM_nent(i)(12))&" " - -- &to_bstring(sa_RAM_nent(i)(13))&" " - -- &to_bstring(sa_RAM_nent(i)(14))&" " - -- &to_bstring(sa_RAM_nent(i)(15)); + -- &to_bstring(sa_RAM_numentries(i)(8))&" " + -- &to_bstring(sa_RAM_numentries(i)(9))&" " + -- &to_bstring(sa_RAM_numentries(i)(10))&" " + -- &to_bstring(sa_RAM_numentries(i)(11))&" " + -- &to_bstring(sa_RAM_numentries(i)(12))&" " + -- &to_bstring(sa_RAM_numentries(i)(13))&" " + -- &to_bstring(sa_RAM_numentries(i)(14))&" " + -- &to_bstring(sa_RAM_numentries(i)(15)); --end loop; - for i in 0 to 2*NUM_PHI_BINS-1 loop - --report "tf_mem_bin read nent " & NAME & " " &to_bstring(addr_nent) & " " & to_bstring(sa_RAM_nent(i)(to_integer(unsigned(addr_nent)))); - dout_nent(ADDR_WIDTH*(i+1)-1 downto ADDR_WIDTH*i) <= sa_RAM_nent(i)(to_integer(unsigned(addr_nent))); - end loop; +-- for i in 0 to 2*NUM_PHI_BINS-1 loop + --report "tf_mem_bin read nent " & NAME & " " &to_bstring(addr_nent) & " " & to_bstring(sa_RAM_numentries(i)(to_integer(unsigned(addr_nent)))); + dout_nent(ADDR_WIDTH*NUM_PHI_BINS-1 downto 0) <= sa_RAM_numentriesA7(to_integer(unsigned(addr_nent)))&sa_RAM_numentriesA6(to_integer(unsigned(addr_nent)))&sa_RAM_numentriesA5(to_integer(unsigned(addr_nent)))&sa_RAM_numentriesA4(to_integer(unsigned(addr_nent)))&sa_RAM_numentriesA3(to_integer(unsigned(addr_nent)))&sa_RAM_numentriesA2(to_integer(unsigned(addr_nent)))&sa_RAM_numentriesA1(to_integer(unsigned(addr_nent)))&sa_RAM_numentriesA0(to_integer(unsigned(addr_nent))); + dout_nent(ADDR_WIDTH*2*NUM_PHI_BINS-1 downto ADDR_WIDTH*NUM_PHI_BINS) <= sa_RAM_numentriesB7(to_integer(unsigned(addr_nent)))&sa_RAM_numentriesB6(to_integer(unsigned(addr_nent)))&sa_RAM_numentriesB5(to_integer(unsigned(addr_nent)))&sa_RAM_numentriesB4(to_integer(unsigned(addr_nent)))&sa_RAM_numentriesB3(to_integer(unsigned(addr_nent)))&sa_RAM_numentriesB2(to_integer(unsigned(addr_nent)))&sa_RAM_numentriesB1(to_integer(unsigned(addr_nent)))&sa_RAM_numentriesB0(to_integer(unsigned(addr_nent))); +-- end loop; end if; for i in 0 to NUM_COPY-1 loop @@ -335,6 +476,31 @@ begin end process; +process(clkb) + + variable binmaskvalueA : std_logic_vector(NUM_PHI_BINS - 1 downto 0); + variable binmaskvalueB : std_logic_vector(NUM_PHI_BINS - 1 downto 0); + variable overflowmask : std_logic_vector(NUM_PAGES_BITS + NUM_RZ_BITS -1 downto 0) := (0 => '1', 1 => '1', 2 => '1', others =>'0'); + +begin + + if rising_edge(clkb) then + if (enb_binmaskA = '1') then + binmaskvalueA := binmaskA(to_integer(unsigned(addr_binmaskA))) and validbinmask(to_integer(unsigned(addr_binmaskA))); + --report "tf_mem_bin binmaskvalueA "&time'image(now)&" "& NAME & " " & to_bstring(binmaskvalueA) & " " & to_bstring(binmaskA(to_integer(unsigned(addr_binmaskA)))) & " " & to_bstring(validbinmask(to_integer(unsigned(addr_binmaskA)))) & " " & to_bstring(validbinmask) & " " & to_bstring(addr_binmaskA) & " " & to_bstring(addr_binmaskB); + binmaskA_o <= binmaskvalueA; + end if; + + if (enb_binmaskA = '1') then + binmaskvalueB := binmaskB(to_integer(unsigned(addr_binmaskB))) and validbinmask(to_integer(unsigned(addr_binmaskB))); + binmaskB_o <= binmaskvalueB; + end if; + end if; + + --report "tf_mem_bin addr_binmask "&time'image(now)&" "& NAME & " " & to_bstring(addr_binmaskA) & " " & to_bstring(binmaskvalueA); + +end process; + -- The following code generates HIGH_PERFORMANCE (use output register) or LOW_LATENCY (no output register) MODE : if (RAM_PERFORMANCE = "LOW_LATENCY") generate -- no_output_register; 1 clock cycle read latency at the cost of a longer clock-to-out timing process(clkb) diff --git a/IntegrationTests/common/hdl/tf_mem_tpar.vhd b/IntegrationTests/common/hdl/tf_mem_tpar.vhd index 7f704dabb4f..b26094397a2 100644 --- a/IntegrationTests/common/hdl/tf_mem_tpar.vhd +++ b/IntegrationTests/common/hdl/tf_mem_tpar.vhd @@ -143,11 +143,6 @@ begin --end if; slv_page_cnt_save := slv_page_cnt; - if (sync_nent='1') and (init='1') then - init := '0'; - slv_clk_cnt := (others => '0'); - slv_page_cnt := (0 => '1', others => '0'); - end if; if (init = '0' and to_integer(unsigned(slv_clk_cnt)) < MAX_ENTRIES-1) then slv_clk_cnt := std_logic_vector(unsigned(slv_clk_cnt)+1); elsif (to_integer(unsigned(slv_clk_cnt)) >= MAX_ENTRIES-1) then @@ -161,8 +156,15 @@ begin -- Note that we don't zero the nent_o counters here. When adding entry we -- reset the nent_o counter if the mask is zero end if; + if (sync_nent='1') and (init='1') then + --report time'image(now)&" tf_mem_tpar "&NAME&" sync_nent"; + init := '0'; + slv_clk_cnt := (others => '0'); + slv_page_cnt := (0 => '1', others => '0'); + end if; + if (wea='1') then - tpage := addra(clogb2(PAGE_LENGTH*NUM_TPAGES)-1 downto clogb2(PAGE_LENGTH)); + tpage := addra(clogb2(NUM_TPAGES)-1 downto 0); nentaddress := slv_page_cnt_save&tpage; if (mask_o(to_integer(unsigned(slv_page_cnt_save)))(to_integer(unsigned(tpage)))='1') then address := nentaddress&nent_o(to_integer(unsigned(nentaddress))); @@ -171,7 +173,7 @@ begin address := nentaddress&std_logic_vector(to_unsigned(0, nent_o(to_integer(unsigned(nentaddress)))'length)); nent_o(to_integer(unsigned(nentaddress))) <= std_logic_vector(to_unsigned(1, nent_o(to_integer(unsigned(nentaddress)))'length)); end if; - --report time'image(now)&" tf_mem_tproj "&NAME&" addra:"&to_bstring(addra)&" tpage:"&integer'image(tpage)&" writeaddr "&to_bstring(vi_page_cnt_slv)&" "&to_bstring(address)&" nentaddress nent:"&integer'image(nentaddress)&" "&to_bstring(nent_o(nentaddress))&" "&to_bstring(dina); + --report time'image(now)&" tf_mem_tpar "&NAME&" tpage:"&to_bstring(tpage)&" writeaddr "&to_bstring(slv_page_cnt_save)&" "&to_bstring(address)&" nentaddress nent:"&to_bstring(nentaddress)&" "&to_bstring(nent_o(to_integer(unsigned(nentaddress))))&" "&to_bstring(dina); sa_RAM_data(to_integer(unsigned(address))) <= dina; -- Write data mask_o(to_integer(unsigned(slv_page_cnt_save)))(to_integer(unsigned(tpage))) <= '1'; end if; diff --git a/IntegrationTests/common/hdl/tf_mem_tproj.vhd b/IntegrationTests/common/hdl/tf_mem_tproj.vhd index 79e7202346d..96f42ba32b0 100644 --- a/IntegrationTests/common/hdl/tf_mem_tproj.vhd +++ b/IntegrationTests/common/hdl/tf_mem_tproj.vhd @@ -127,7 +127,7 @@ begin -- report "tf_mem_tproj "&NAME&" nent(0) nent(1) "&to_bstring(nent_o(0))&" "&to_bstring(nent_o(1)); --end if; --if (NUM_PAGES = 8 and NUM_TPAGES = 4) then - -- report "tf_mem_tproj "&time'image(now)&" "&NAME&" nent_0 " + -- report "tf_mem_tproj "&time'image(now)&" "&NAME&" nent_o " -- &to_bstring(nent_o(0))&" " -- &to_bstring(nent_o(1))&" " -- &to_bstring(nent_o(2))&" " @@ -140,11 +140,6 @@ begin --end if; --end if; slv_page_cnt_save := slv_page_cnt; - if (sync_nent='1') and (init='1') then - init := '0'; - slv_clk_cnt := (others => '0'); - slv_page_cnt := (0 => '1', others => '0'); - end if; if (init = '0' and to_integer(unsigned(slv_clk_cnt)) < MAX_ENTRIES-1) then slv_clk_cnt := std_logic_vector(unsigned(slv_clk_cnt)+1); elsif (to_integer(unsigned(slv_clk_cnt)) >= MAX_ENTRIES-1) then @@ -158,19 +153,30 @@ begin -- Note that we don't zero the nent_o counters here. When adding entry we -- reset the nent_o counter if the mask is zero end if; + if (sync_nent='1') and (init='1') then + --report time'image(now)&" tf_mem_tproj "&NAME&" sync_nent"; + init := '0'; + slv_clk_cnt := (others => '0'); + slv_page_cnt := (0 => '1', others => '0'); + end if; + if (wea='1') then - tpage := addra(clogb2(PAGE_LENGTH*NUM_TPAGES)-1 downto clogb2(PAGE_LENGTH)); + tpage := addra(clogb2(NUM_TPAGES)-1 downto 0); nentaddress := slv_page_cnt_save&tpage; if (mask_o(to_integer(unsigned(slv_page_cnt_save)))(to_integer(unsigned(tpage)))='1') then address := nentaddress&nent_o(to_integer(unsigned(nentaddress))); - nent_o(to_integer(unsigned(nentaddress))) <= std_logic_vector(to_unsigned(to_integer(unsigned(nent_o(to_integer(unsigned(nentaddress))))) + 1, nent_o(to_integer(unsigned(nentaddress)))'length)); -- + 1 (slv) + if (to_integer(unsigned(nent_o(to_integer(unsigned(nentaddress))))) /= 63) then + nent_o(to_integer(unsigned(nentaddress))) <= std_logic_vector(to_unsigned(to_integer(unsigned(nent_o(to_integer(unsigned(nentaddress))))) + 1, nent_o(to_integer(unsigned(nentaddress)))'length)); -- + 1 (slv) + end if; else address := nentaddress&std_logic_vector(to_unsigned(0, nent_o(to_integer(unsigned(nentaddress)))'length)); nent_o(to_integer(unsigned(nentaddress))) <= std_logic_vector(to_unsigned(1, nent_o(to_integer(unsigned(nentaddress)))'length)); end if; - --report time'image(now)&" tf_mem_tproj "&NAME&" addra:"&to_bstring(addra)&" tpage:"&integer'image(tpage)&" writeaddr "&to_bstring(vi_page_cnt_slv)&" "&to_bstring(address)&" nentaddress nent:"&integer'image(nentaddress)&" "&to_bstring(nent_o(nentaddress))&" "&to_bstring(dina); - sa_RAM_data(to_integer(unsigned(address))) <= dina; -- Write data - mask_o(to_integer(unsigned(slv_page_cnt_save)))(to_integer(unsigned(tpage))) <= '1'; + --report time'image(now)&" tf_mem_tproj "&NAME&" addra:"&to_bstring(addra)&" tpage:"&to_bstring(tpage)&" writeaddr "&to_bstring(slv_page_cnt_save)&" "&to_bstring(address)&" nentaddress nent:"&to_bstring(nentaddress)&" "&to_bstring(nent_o(to_integer(unsigned(nentaddress))))&" "&to_bstring(dina); + if (to_integer(unsigned(nent_o(to_integer(unsigned(nentaddress))))) /= 63) then + sa_RAM_data(to_integer(unsigned(address))) <= dina; -- Write data + mask_o(to_integer(unsigned(slv_page_cnt_save)))(to_integer(unsigned(tpage))) <= '1'; + end if; end if; end if; end process; @@ -180,8 +186,17 @@ begin if rising_edge(clkb) then if (enb='1') then if DEBUG then - report "tf_mem_tproj "&time'image(now)&" "&NAME&" readaddr "&to_bstring(addrb) - &" "&to_bstring(sa_RAM_data(to_integer(unsigned(addrb)))); + report "tf_mem_tproj "&time'image(now)&" "&NAME&" readaddr "&to_bstring(addrb) + &" "&to_bstring(sa_RAM_data(to_integer(unsigned(addrb)))) & " mask_o " & to_bstring(mask_o(1)) & " " & to_bstring(mask_o(0)) + & " nent_o " + &to_bstring(nent_o(0))&" " + &to_bstring(nent_o(1))&" " + &to_bstring(nent_o(2))&" " + &to_bstring(nent_o(3))&" " + &to_bstring(nent_o(4))&" " + &to_bstring(nent_o(5))&" " + &to_bstring(nent_o(6))&" " + &to_bstring(nent_o(7)); end if; sv_RAM_row <= sa_RAM_data(to_integer(unsigned(addrb))); end if; diff --git a/IntegrationTests/common/script/CompareMemPrintsFW.py b/IntegrationTests/common/script/CompareMemPrintsFW.py index 7f74b55638e..5d33dbc157e 100644 --- a/IntegrationTests/common/script/CompareMemPrintsFW.py +++ b/IntegrationTests/common/script/CompareMemPrintsFW.py @@ -19,11 +19,11 @@ import glob from enum import Enum -# Python 2-3 compatibility -try: - import future, builtins, past, six -except ImportError as error: - raise ImportError("Unable to import the python2/3 compatibility modules (future, builtins, past, six)") +# Python 2-3 compatibility - commented out by Ryd as it did not seem to work? +#try: +# import future, builtins, past, six +#except ImportError as error: +# raise ImportError("Unable to import the python2/3 compatibility modules (future, builtins, past, six)") # Based on: https://stackoverflow.com/questions/14906764/how-to-redirect-stdout-to-both-file-and-console-with-scripting/14906787 class Logger(object): @@ -53,6 +53,7 @@ class ReferenceType(Enum): AS = 'AllStubs' SP = 'StubPairs' TPAR = 'TrackletParameters' + MPROJ = 'TrackletProjections' TPROJ = 'TrackletProjections' VMPROJ = 'VMProjections' AP = 'AllProjections' @@ -132,24 +133,64 @@ def compare(comparison_filename="", fail_on_error=False, file_location='./', pre print("Comparing TB results "+str(comparison_filename)+" to ref. file "+str(reference_filename)+" ... ") - # Read column names from file - column_names = list(pd.read_csv(file_location+"/"+comparison_filename,delim_whitespace=True,nrows=1)) + # Read column names from comparison file + column_names = list(pd.read_csv(file_location+"/"+comparison_filename,sep='\s+',nrows=1)) if verbose: print(column_names) # Check if binned memory - if ('BIN' in column_names): + if ('VMS' in comparison_filename): is_binned = True - column_selections = ['BX','ADDR','BIN','DATA'] else: is_binned = False - column_selections = ['BX','ADDR','DATA'] + + column_selections = ['TIME', 'BX', 'ADDR', 'DATA'] # Open the comparison (= VHDL test-bench output) data - data = pd.read_csv(file_location+"/"+comparison_filename,delim_whitespace=True,header=0,names=column_names,usecols=[i for i in column_names if any(select in i for select in column_selections)]) + data = pd.read_csv(file_location+"/"+comparison_filename,sep='\s+',header=0,names=column_names,usecols=[i for i in column_names if any(select in i for select in column_selections)]) if verbose: print(data) # Can also just do data.head() + #Need to figure out how to handle the memory "overwrite" - this is a bit of a hack... + if (not is_binned) and ("TF_" not in comparison_filename): + rows = [] + for index, row in data.iterrows(): + if row['ADDR'] == "0x01": + rows.append(index-1) # -1 to remove previos entry + data=data.drop(rows) + + #This is a hack to work around over flows in VMStub memories + if is_binned: + rows = [] + count = {} + for index, row in data.iterrows(): + entry = str(row['BX'])+row['ADDR'] + if entry not in count: + count[entry]=1 + else: + count[entry]+=1 + if count[entry]>15: + rows.append(index) + data=data.drop(rows) + + #This is a hack to work around over flows in MPROJ memories + if "MPROJ_" in comparison_filename: + rows = [] + count = {} + for index, row in data.iterrows(): + entry = str(row['BX'])+row['ADDR'] + if entry not in count: + count[entry]=1 + else: + count[entry]+=1 + if count[entry]>63: + rows.append(index) + data=data.drop(rows) + # Sort data by ascending address - data.sort_values(by=['BX','ADDR'], inplace = True) + if is_binned: + data.sort_values(by=['BX','ADDR','DATA'], inplace = True) + else: + data.sort_values(by=['BX','DATA'], inplace = True) + data.reset_index(drop = True, inplace = True) selected_columns = data[column_selections] @@ -158,6 +199,7 @@ def compare(comparison_filename="", fail_on_error=False, file_location='./', pre reference_data = parse_reference_file(file_location+"/"+reference_filename, is_binned) for ievent,event in enumerate(reference_data): + print("Doing event "+str(ievent)+"/"+str(len(reference_data))+" ... ") good = True @@ -190,6 +232,8 @@ def compare(comparison_filename="", fail_on_error=False, file_location='./', pre offset = selected_rows['DATA'].index[0] + event.sort() + for ival,val in enumerate(event): # In case there are fewer entries in the comparison data than in the reference data if offset+ival not in selected_rows['DATA']: continue @@ -211,11 +255,13 @@ def compare(comparison_filename="", fail_on_error=False, file_location='./', pre # Raise exception if the bin number of a given entry don't match elif is_binned: - if selected_rows['BIN'][offset+ival] != int(bin): + ref_add = selected_rows['ADDR'][offset+ival][3:] + data_add = bin.upper() + if ref_add != data_add: good = False number_of_value_mismatches += 1 message = "The bin for event "+str(ievent)+" stub "+str(selected_rows['DATA'][offset+ival])+" do not match!"\ - "\n\treference="+bin+" comparison="+str(selected_rows['BIN'][offset+ival]) + "\n\treference="+bin+" comparison="+str(selected_rows['ADDR'][offset+ival]) if fail_on_error: raise Exception(message) else: print("\t\t"+message.replace("\n","\n\t\t")) @@ -247,7 +293,7 @@ def comparePredefined(args): raise FileNotFoundError(comparison_dir + " is empty. No files to compare.") # Find the lists of filenames - comparison_filename_list = [f for f in glob.glob(comparison_dir+"*.txt") if "debug" not in f and "cmp" not in f and "TW" not in f and "BW" not in f] # Remove debug and comparison files from file list, also also TW/BW output from TB (since TF output used instead). + comparison_filename_list = [f for f in glob.glob(comparison_dir+"*.txt") if "debug" not in f and "cmp" not in f and "TW" not in f and "BW" not in f and "DW" not in f] # Remove debug and comparison files from file list, also also TW/BW output from TB (since TF output used instead). comparison_filename_list.sort() reference_filename_list = [f.split('/')[-1].split('.')[0].replace("TEO", "TE").replace("TEI", "TE") for f in comparison_filename_list] # Remove file extension from comparison_filename_list and replace TEO/TEI with TE try: @@ -264,7 +310,7 @@ def comparePredefined(args): print("Summary of memories with errors") print("=================================") sys.stdout.flush() - os.system('\grep "Bad events: [1-9]" dataOut/*cmp.txt') + os.system('grep "Bad events: [1-9]" dataOut/*cmp.txt') print("\n Accumulated number of errors =",ret_sum) diff --git a/IntegrationTests/common/script/Makefile.mk b/IntegrationTests/common/script/Makefile.mk index 2ac97dd4b9f..de1f1c88e4d 100644 --- a/IntegrationTests/common/script/Makefile.mk +++ b/IntegrationTests/common/script/Makefile.mk @@ -72,7 +72,7 @@ LUTs: # Dependency files are created following the example in the manual for GNU make: # https://www.gnu.org/software/make/manual/html_node/Automatic-Prerequisites.html -$(DEPS)/%.d: $(EMDATA)/MemPrintsCM +$(DEPS)/%.d: $(EMDATA)/MemPrintsSplit @set -e; rm -f $@; mkdir -p $(DEPS); \ TOP_FUNC=`echo $@ | sed 's,.*\/\([^/]*\)\.d,\1,g'`; \ TOP_FILE=`grep -l $${TOP_FUNC} $(TOP_FUNCS)/*.cc`; \ @@ -86,10 +86,10 @@ include $(MODULES:%=$(DEPS)/%.d) ### Run emData/download.sh before anything else ### -$(EMDATA)/MemPrintsCM: $(EMDATA)/download.sh +$(EMDATA)/MemPrintsSplit: $(EMDATA)/download.sh @cd $(EMDATA)/; \ - ./clean.sh; \ - ./download.sh + ./clean.sh; \ + ./download.sh ### Other targets ### diff --git a/TestBenches/FileReadUtility.h b/TestBenches/FileReadUtility.h index a441819b101..cf254a63e95 100644 --- a/TestBenches/FileReadUtility.h +++ b/TestBenches/FileReadUtility.h @@ -105,6 +105,7 @@ void writeMemFromFile(MemType& memory, std::ifstream& fin, int ievt, int base=16 } memory.clear(); + memory.setWriteBX(ievt); while (getline(fin, line)) { @@ -115,12 +116,8 @@ void writeMemFromFile(MemType& memory, std::ifstream& fin, int ievt, int base=16 if (line.find("Event") != std::string::npos) { return; } else { - if (split(line,' ').size()==4) { - memory.write_mem(ievt, line, base); - } else { - const std::string datastr = split(line, ' ').back(); - memory.write_mem(ievt, datastr, base); - } + std::vector split_line = split(line, ' '); + memory.write_mem(split_line, base); } } @@ -611,12 +608,12 @@ unsigned int compareMemWithTwoFiles(const MemType& memory, std::vector 1){ for (int j = 0; j < memory_ref2.getEntries(0); ++j){ auto data_ref2 = memory_ref2.read_mem(0, j); - memory_ref.write_mem(0, data_ref2, j + memory_ref1.getEntries(0)); + memory_ref.write_mem(data_ref2, j + memory_ref1.getEntries(0)); } } diff --git a/TestBenches/InputRouter_test.cpp b/TestBenches/InputRouter_test.cpp index d8d7e4bd01d..db1a08d7e00 100644 --- a/TestBenches/InputRouter_test.cpp +++ b/TestBenches/InputRouter_test.cpp @@ -660,6 +660,7 @@ int main(int argc, char * argv[]) for( unsigned int cIndx=0; cIndx < (unsigned int)hNmemories ; cIndx++) { hMemories[cIndx].clear(); + hMemories[cIndx].setWriteBX(cEvId); } BXType hBx = cEvId&0x7; BXType hBx_o; diff --git a/TestBenches/Macros.h b/TestBenches/Macros.h index afa101da975..fe9cfc69c84 100644 --- a/TestBenches/Macros.h +++ b/TestBenches/Macros.h @@ -35,14 +35,16 @@ X(PC_D3D4ABCD_, "PC_D3D4ABCD") \ X(PC_L1D1ABCD_, "PC_L1D1ABCD") \ X(PC_L1D1EFGH_, "PC_L1D1EFGH") \ X(PC_L2D1ABCD_, "PC_L2D1ABCD") \ -X(FT_D1D2_, "FT_D1D2") \ -X(FT_D3D4_, "FT_D3D4") \ -X(FT_L1D1_, "FT_L1D1") \ -X(FT_L1L2_, "FT_L1L2") \ -X(FT_L2D1_, "FT_L2D1") \ -X(FT_L2L3_, "FT_L2L3") \ -X(FT_L3L4_, "FT_L3L4") \ -X(FT_L5L6_, "FT_L5L6") \ +X(TB_D1D2_, "TB_D1D2") \ +X(TB_D3D4_, "TB_D3D4") \ +X(TB_L1D1_, "TB_L1D1") \ +X(TB_L1L2_, "TB_L1L2") \ +X(TB_L2D1_, "TB_L2D1") \ +X(TB_L2L3_, "TB_L2L3") \ +X(TB_L3L4_, "TB_L3L4") \ +X(TB_L5L6_, "TB_L5L6") \ +X(TB_AAAA_, "TB_AAAA") \ +X(TB_BBBB_, "TB_BBBB") \ X(IR_2S_1_A_, "IR_2S_1_A") \ X(IR_2S_1_B_, "IR_2S_1_B") \ X(IR_2S_2_A_, "IR_2S_2_A") \ @@ -194,11 +196,15 @@ X(MP_D2PHIC_, "MP_D2PHIC") \ X(MP_D2PHID_, "MP_D2PHID") \ X(MP_D3PHIA_, "MP_D3PHIA") \ X(MP_D3PHIB_, "MP_D3PHIB") \ +X(MP_D3PHIB_E_, "MP_D3PHIB_E") \ X(MP_D3PHIC_, "MP_D3PHIC") \ +X(MP_D3PHIC_E_, "MP_D3PHIC_E") \ X(MP_D3PHID_, "MP_D3PHID") \ X(MP_D4PHIA_, "MP_D4PHIA") \ X(MP_D4PHIB_, "MP_D4PHIB") \ +X(MP_D4PHIB_E_, "MP_D4PHIB_E") \ X(MP_D4PHIC_, "MP_D4PHIC") \ +X(MP_D4PHIC_E_, "MP_D4PHIC_E") \ X(MP_D4PHID_, "MP_D4PHID") \ X(MP_D5PHIA_, "MP_D5PHIA") \ X(MP_D5PHIB_, "MP_D5PHIB") \ @@ -218,19 +224,27 @@ X(MP_L2PHIC_, "MP_L2PHIC") \ X(MP_L2PHID_, "MP_L2PHID") \ X(MP_L3PHIA_, "MP_L3PHIA") \ X(MP_L3PHIB_, "MP_L3PHIB") \ +X(MP_L3PHIB_E_, "MP_L3PHIB_E") \ X(MP_L3PHIC_, "MP_L3PHIC") \ +X(MP_L3PHIC_E_, "MP_L3PHIC_E") \ X(MP_L3PHID_, "MP_L3PHID") \ X(MP_L4PHIA_, "MP_L4PHIA") \ X(MP_L4PHIB_, "MP_L4PHIB") \ +X(MP_L4PHIB_E_, "MP_L4PHIB_E") \ X(MP_L4PHIC_, "MP_L4PHIC") \ +X(MP_L4PHIC_E_, "MP_L4PHIC_E") \ X(MP_L4PHID_, "MP_L4PHID") \ X(MP_L5PHIA_, "MP_L5PHIA") \ X(MP_L5PHIB_, "MP_L5PHIB") \ +X(MP_L5PHIB_E_, "MP_L5PHIB_E") \ X(MP_L5PHIC_, "MP_L5PHIC") \ +X(MP_L5PHIC_E_, "MP_L5PHIC_E") \ X(MP_L5PHID_, "MP_L5PHID") \ X(MP_L6PHIA_, "MP_L6PHIA") \ X(MP_L6PHIB_, "MP_L6PHIB") \ +X(MP_L6PHIB_E_, "MP_L6PHIB_E") \ X(MP_L6PHIC_, "MP_L6PHIC") \ +X(MP_L6PHIC_E_, "MP_L6PHIC_E") \ X(MP_L6PHID_, "MP_L6PHID") #define X(module, name) module, diff --git a/TestBenches/MatchProcessor_test.cpp b/TestBenches/MatchProcessor_test.cpp index 6bd1d246a86..945b294d841 100644 --- a/TestBenches/MatchProcessor_test.cpp +++ b/TestBenches/MatchProcessor_test.cpp @@ -45,11 +45,11 @@ int main() // input memories const auto nTrackletProjections = tb.nFiles(trackletProjectionPattern); vector> tprojarray(nTrackletProjections); + const auto nAllStub = tb.nFiles(allStubPatternarray); vector> allstub(nAllStub); const auto nVMStubs = tb.nFiles(vmStubPatternarray); VMStubMemory vmstub; // barrel - // output memories const auto nFullMatches = tb.nFiles(fullMatchPattern); vector > fullmatcharray(nFullMatches); @@ -87,9 +87,11 @@ int main() writeMemFromFile>(vmstub, fin_VMStubs.at(0), ievt); // barrel // clear allarray, output memories before starting - for (unsigned int i = 0; i < nFullMatches; i++) + for (unsigned int i = 0; i < nFullMatches; i++){ fullmatcharray[i].clear(); - + fullmatcharray[i].setWriteBX(ievt); + } + // Unit Under Test TOP_FUNC_(bx, tprojarray.data(), vmstub, allstub.data(), bx_out, fullmatcharray.data()); diff --git a/TestBenches/ProjectionCalculator_test.cpp b/TestBenches/ProjectionCalculator_test.cpp index 15a2ed43446..c2687b88bdf 100644 --- a/TestBenches/ProjectionCalculator_test.cpp +++ b/TestBenches/ProjectionCalculator_test.cpp @@ -72,13 +72,19 @@ int main() writeMemFromFile(trackletParameters, fin_tpar.at(0), ievt); // clear all output memories before starting - for (unsigned i = 0; i < TP::N_PROJOUT_BARRELPS; i++) + for (unsigned i = 0; i < TP::N_PROJOUT_BARRELPS; i++) { tproj_barrel_ps[i].clear(); - for (unsigned i = 0; i < TP::N_PROJOUT_BARREL2S; i++) + tproj_barrel_ps[i].setWriteBX(ievt); + } + for (unsigned i = 0; i < TP::N_PROJOUT_BARREL2S; i++) { tproj_barrel_2s[i].clear(); - for (unsigned i = 0; i < TP::N_PROJOUT_DISK; i++) + tproj_barrel_2s[i].setWriteBX(ievt); + } + for (unsigned i = 0; i < TP::N_PROJOUT_DISK; i++) { tproj_disk[i].clear(); - + tproj_disk[i].setWriteBX(ievt); + } + // bx BXType bx = ievt; BXType bx_o; diff --git a/TestBenches/TrackBuilder_test.cpp b/TestBenches/TrackBuilder_test.cpp index 846e4b24247..87262dd20df 100644 --- a/TestBenches/TrackBuilder_test.cpp +++ b/TestBenches/TrackBuilder_test.cpp @@ -11,45 +11,17 @@ using namespace std; // No macros can be defined from the command line in the case of C/RTL // cosimulation, so we define defaults here. #if !defined SEED_ - #define SEED_ L1L2_ + #define SEED_ AAAA_ #endif #if !defined MODULE_ - #define MODULE_ FT_L1L2_ + #define MODULE_ TB_AAAA_ #endif #if !defined TOP_FUNC_ - #define TOP_FUNC_ TrackBuilder_L1L2 + #define TOP_FUNC_ TrackBuilder_AAAA #endif -#if SEED_ == L1L2_ - constexpr int kNBarrelStubs = 4; - constexpr int kNDiskStubs = 4; -#elif SEED_ == L2L3_ - constexpr int kNBarrelStubs = 3; - constexpr int kNDiskStubs = 4; -#elif SEED_ == L3L4_ - constexpr int kNBarrelStubs = 4; - constexpr int kNDiskStubs = 2; -#elif SEED_ == L5L6_ - constexpr int kNBarrelStubs = 4; - constexpr int kNDiskStubs = 0; -#elif SEED_ == D1D2_ - constexpr int kNBarrelStubs = 2; - constexpr int kNDiskStubs = 3; -#elif SEED_ == D3D4_ - constexpr int kNBarrelStubs = 1; - constexpr int kNDiskStubs = 3; -#elif SEED_ == L1D1_ - constexpr int kNBarrelStubs = 0; - constexpr int kNDiskStubs = 4; -#elif SEED_ == L2D1_ - constexpr int kNBarrelStubs = 1; - constexpr int kNDiskStubs = 3; -#else -# error "Undefined seed" -#endif - -typedef TrackFit TrackFit_t; -typedef TrackFitMemory TrackFitMemory_t; +typedef TrackFit TrackFit_t; +typedef TrackFitMemory TrackFitMemory_t; // Base assumed for input test vector files constexpr int InputBase = 16; @@ -69,7 +41,7 @@ void setBarrelStubs<-1>(TrackFit_t &track, const TrackFit_t::BarrelStubWord stub template void setDiskStubs(TrackFit_t &track, const TrackFit_t::DiskStubWord stubWords[][kMaxProc], const unsigned i) { - track.setDiskStubWord(stubWords[I][i]); + track.setDiskStubWord(stubWords[I][i]); setDiskStubs(track, stubWords, i); } @@ -94,7 +66,7 @@ void compareStubsWithFile<0>(int &err, ifstream &fout, const int pos, const Trac int main() { - TBHelper tb(string("FT/") + module_name[MODULE_]); + TBHelper tb(string("TB/") + module_name[MODULE_]); // error counts int err = 0; @@ -138,8 +110,8 @@ int main() // output memories TrackFit_t::TrackWord trackWord[kMaxProc]; - TrackFit_t::BarrelStubWord barrelStubWords[kNBarrelStubs][kMaxProc]; - TrackFit_t::DiskStubWord diskStubWords[kNDiskStubs][kMaxProc]; + TrackFit_t::BarrelStubWord barrelStubWords[trklet::N_LAYER][kMaxProc]; + TrackFit_t::DiskStubWord diskStubWords[trklet::N_DISK][kMaxProc]; TrackFitMemory_t tracksMem; /////////////////////////// @@ -151,12 +123,13 @@ int main() // Clear all output memories before starting. for (unsigned short i = 0; i < kMaxProc; i++) { trackWord[i] = TrackFit_t::TrackWord(0); - for (short j = 0; j < kNBarrelStubs; j++) + for (short j = 0; j < trklet::N_LAYER; j++) barrelStubWords[j][i] = TrackFit_t::BarrelStubWord(0); - for (short j = 0; j < kNDiskStubs; j++) + for (short j = 0; j < trklet::N_DISK; j++) diskStubWords[j][i] = TrackFit_t::DiskStubWord(0); } tracksMem.clear(); + tracksMem.setWriteBX(ievt); // read event and write to memories for (unsigned i = 0; i < nTPar1Mems; i++) @@ -192,21 +165,20 @@ int main() done ); - unsigned nTracks = 0; for (unsigned short i = 0; i < kMaxProc; i++) { TrackFit_t track; track.setTrackWord(trackWord[i]); - setBarrelStubs(track, barrelStubWords, i); - setDiskStubs(track, diskStubWords, i); + setBarrelStubs(track, barrelStubWords, i); + setDiskStubs(track, diskStubWords, i); if (track.getTrackValid()) - tracksMem.write_mem(bx, track, nTracks++); + tracksMem.write_mem(track); } const auto &pos = fout_tracks.at(0).tellg(); // compare the computed outputs with the expected ones err += compareMemWithFile(tracksMem, fout_tracks.at(0), ievt, "\nTrack word", true); - compareStubsWithFile(err, fout_tracks.at(0), pos, tracksMem, ievt); + compareStubsWithFile(err, fout_tracks.at(0), pos, tracksMem, ievt); cout << endl; } // end of event loop diff --git a/TestBenches/TrackMerger_test.cpp b/TestBenches/TrackMerger_test.cpp index 3c75c32d8a5..47c871de00e 100644 --- a/TestBenches/TrackMerger_test.cpp +++ b/TestBenches/TrackMerger_test.cpp @@ -20,24 +20,24 @@ int main(){ // Input memories TrackFitType::TrackWord trackWord[kMaxTrack]; - TrackFitType::BarrelStubWord barrelStubWords[kMaxTrack][4]; - TrackFitType::DiskStubWord diskStubWords[kMaxTrack][4]; - TrackFitMemory inputTracks; + TrackFitType::BarrelStubWord barrelStubWords[kMaxTrack][trklet::N_LAYER]; + TrackFitType::DiskStubWord diskStubWords[kMaxTrack][trklet::N_DISK]; + TrackFitMemory inputTracks; // Output memories TrackFitType::TrackWord trackWord_o[kMaxTrack]; - TrackFitType::BarrelStubWord barrelStubWords_o[kMaxTrack][4]; - TrackFitType::DiskStubWord diskStubWords_o[kMaxTrack][4]; - TrackFitMemory outputTracks; + TrackFitType::BarrelStubWord barrelStubWords_o[kMaxTrack][trklet::N_LAYER]; + TrackFitType::DiskStubWord diskStubWords_o[kMaxTrack][trklet::N_DISK]; + TrackFitMemory outputTracks; // int outputNumber; TBHelper tb("../../../../../emData/PD/PD/"); // Open input files - auto &fin_inputTracks = tb.files("TrackFit_TF_L1L2*"); + auto &fin_inputTracks = tb.files("TrackFit_TF_AAAA*"); - auto &fout_outputTracks = tb.files("CleanTrack_CT_L1L2*"); + auto &fout_outputTracks = tb.files("CleanTrack_CT_AAAA*"); for (unsigned int ievt = 0; ievt < nevents; ++ievt) { cout << "Event: " << dec << ievt << endl; @@ -45,18 +45,21 @@ int main(){ trackWord[i] = TrackFitType::TrackWord(0); trackWord_o[i] = TrackFitType::TrackWord(0); - for (unsigned short nStub = 0; nStub < 4; nStub++){ + for (unsigned short nStub = 0; nStub < trklet::N_LAYER; nStub++){ barrelStubWords[i][nStub] = TrackFitType::BarrelStubWord(0); - diskStubWords[i][nStub] = TrackFitType::DiskStubWord(0); barrelStubWords_o[i][nStub] = TrackFitType::BarrelStubWord(0); - diskStubWords_o[i][nStub] = TrackFitType::DiskStubWord(0); + if ( nStub != trklet::N_DISK ) { //FIXME this is written in a very confusing way.... + diskStubWords[i][nStub] = TrackFitType::DiskStubWord(0); + diskStubWords_o[i][nStub] = TrackFitType::DiskStubWord(0); + } } } outputTracks.clear(); + outputTracks.setWriteBX(ievt); // Read in next event from input - writeMemFromFile> (inputTracks, fin_inputTracks.at(0), ievt); + writeMemFromFile> (inputTracks, fin_inputTracks.at(0), ievt); // Set bunch crossing BXType bx = ievt; @@ -75,10 +78,13 @@ int main(){ barrelStubWords[i][1] = track.getBarrelStubWord<1>(); barrelStubWords[i][2] = track.getBarrelStubWord<2>(); barrelStubWords[i][3] = track.getBarrelStubWord<3>(); - diskStubWords[i][0] = track.getDiskStubWord<4>(); - diskStubWords[i][1] = track.getDiskStubWord<5>(); - diskStubWords[i][2] = track.getDiskStubWord<6>(); - diskStubWords[i][3] = track.getDiskStubWord<7>(); + barrelStubWords[i][4] = track.getBarrelStubWord<4>(); + barrelStubWords[i][5] = track.getBarrelStubWord<5>(); + diskStubWords[i][0] = track.getDiskStubWord<6>(); + diskStubWords[i][1] = track.getDiskStubWord<7>(); + diskStubWords[i][2] = track.getDiskStubWord<8>(); + diskStubWords[i][3] = track.getDiskStubWord<9>(); + diskStubWords[i][4] = track.getDiskStubWord<10>(); } // Unit under test @@ -95,7 +101,6 @@ int main(){ bool truncation = false; // Filling outputs - unsigned nTracks = 0; for (unsigned short i = 0; i < kMaxTrack; i++){ TrackFitType track; track.setTrackWord(trackWord_o[i]); @@ -103,18 +108,20 @@ int main(){ track.setBarrelStubWord<1>(barrelStubWords_o[i][1]); track.setBarrelStubWord<2>(barrelStubWords_o[i][2]); track.setBarrelStubWord<3>(barrelStubWords_o[i][3]); - track.setDiskStubWord<4>(diskStubWords_o[i][0]); - track.setDiskStubWord<5>(diskStubWords_o[i][1]); - track.setDiskStubWord<6>(diskStubWords_o[i][2]); - track.setDiskStubWord<7>(diskStubWords_o[i][3]); + track.setBarrelStubWord<4>(barrelStubWords_o[i][4]); + track.setBarrelStubWord<5>(barrelStubWords_o[i][5]); + track.setDiskStubWord<6>(diskStubWords_o[i][0]); + track.setDiskStubWord<7>(diskStubWords_o[i][1]); + track.setDiskStubWord<8>(diskStubWords_o[i][2]); + track.setDiskStubWord<9>(diskStubWords_o[i][3]); + track.setDiskStubWord<10>(diskStubWords_o[i][4]); - outputTracks.write_mem(bx, track, nTracks ); - ++nTracks; + outputTracks.write_mem(track); } // Comparing outputs - err_count += compareMemWithFile>(outputTracks, fout_outputTracks.at(0), ievt, "Tracks", truncation); + err_count += compareMemWithFile>(outputTracks, fout_outputTracks.at(0), ievt, "Tracks", truncation); } // Commented as f/w does not match the s/w - implementations are different so test vectors are different, TB fails. @@ -122,4 +129,4 @@ int main(){ // if (err_count > 255) err_count = 255; // return err_count; -} \ No newline at end of file +} diff --git a/TestBenches/TrackletProcessor_test.cpp b/TestBenches/TrackletProcessor_test.cpp index bed3968e8f8..6307aed137c 100644 --- a/TestBenches/TrackletProcessor_test.cpp +++ b/TestBenches/TrackletProcessor_test.cpp @@ -147,12 +147,19 @@ std::cout< memoriesAS; // Output memories - static VMStubMemory memoryME; - static AllStubMemory memoriesASCopy; + static VMStubMemory memoryME[NOutCopy]; + static AllStubMemory memoriesASCopy[NOutCopy]; /////////////////////////// // Loop over events @@ -67,8 +71,12 @@ int main() { cout << "Event: " << dec << ievt << endl; // Clear output memories - memoryME.clear(); - memoriesASCopy.clear(); + for(unsigned int i=0; i>(memoryME, fout_vmstubme[0], ievt, "VMStubME", truncation); + for(unsigned int i=0; i>(memoryME[i], fout_vmstubme[i], ievt, "VMStubME", truncation); + } } // End of event loop diff --git a/TopFunctions/TrackMergerTop.cc b/TopFunctions/TrackMergerTop.cc index c4ad49ae83b..11f1a4950a2 100644 --- a/TopFunctions/TrackMergerTop.cc +++ b/TopFunctions/TrackMergerTop.cc @@ -1,28 +1,28 @@ #include "TrackMergerTop.h" void TrackMergerTop(const BXType bx, - const TrackFitType::TrackWord trackWord[kMaxTrack], - const TrackFitType::BarrelStubWord barrelStubWords[kMaxTrack][NBarrelStub], - const TrackFitType::DiskStubWord diskStubWords[kMaxTrack][NDiskStub], - BXType bx_o, - TrackFitType::TrackWord (&trackWord_o)[kMaxTrack], - TrackFitType::BarrelStubWord (&barrelStubWords_o)[kMaxTrack][NBarrelStub], - TrackFitType::DiskStubWord (&diskStubWords_o)[kMaxTrack][NDiskStub] - ){ - #pragma HLS inline recursive - #pragma HLS stream variable=trackWord - #pragma HLS stream variable=barrelStubWords - #pragma HLS stream variable=diskStubWords - #pragma HLS stream variable=trackWord_o - #pragma HLS stream variable=barrelStubWords_o - #pragma HLS stream variable=diskStubWords_o + const TrackFitType::TrackWord trackWord[kMaxTrack], + const TrackFitType::BarrelStubWord barrelStubWords[kMaxTrack][trklet::N_LAYER], + const TrackFitType::DiskStubWord diskStubWords[kMaxTrack][trklet::N_DISK], + BXType bx_o, + TrackFitType::TrackWord (&trackWord_o)[kMaxTrack], + TrackFitType::BarrelStubWord (&barrelStubWords_o)[kMaxTrack][trklet::N_LAYER], + TrackFitType::DiskStubWord (&diskStubWords_o)[kMaxTrack][trklet::N_DISK] + ){ +#pragma HLS inline recursive +#pragma HLS stream variable=trackWord +#pragma HLS stream variable=barrelStubWords +#pragma HLS stream variable=diskStubWords +#pragma HLS stream variable=trackWord_o +#pragma HLS stream variable=barrelStubWords_o +#pragma HLS stream variable=diskStubWords_o - TrackMerger(bx, - trackWord, - barrelStubWords, - diskStubWords, - bx_o, - trackWord_o, - barrelStubWords_o, - diskStubWords_o); -} \ No newline at end of file + TrackMerger(bx, + trackWord, + barrelStubWords, + diskStubWords, + bx_o, + trackWord_o, + barrelStubWords_o, + diskStubWords_o); +} diff --git a/TopFunctions/TrackMergerTop.h b/TopFunctions/TrackMergerTop.h index 855d3648c99..9aa02582e5c 100644 --- a/TopFunctions/TrackMergerTop.h +++ b/TopFunctions/TrackMergerTop.h @@ -5,13 +5,13 @@ #include "../TrackletAlgorithm/TrackHandler.h" void TrackMergerTop(const BXType bx, - const TrackFitType::TrackWord trackWord[kMaxTrack], - const TrackFitType::BarrelStubWord barrelStubWords[kMaxTrack][NBarrelStub], - const TrackFitType::DiskStubWord diskStubWords[kMaxTrack][NDiskStub], - BXType bx_o, - TrackFitType::TrackWord (&trackWord_o)[kMaxTrack], - TrackFitType::BarrelStubWord (&barrelStubWords_o)[kMaxTrack][NBarrelStub], - TrackFitType::DiskStubWord (&diskStubWords_o)[kMaxTrack][NDiskStub] - ); + const TrackFitType::TrackWord trackWord[kMaxTrack], + const TrackFitType::BarrelStubWord barrelStubWords[kMaxTrack][trklet::N_LAYER], + const TrackFitType::DiskStubWord diskStubWords[kMaxTrack][trklet::N_DISK], + BXType bx_o, + TrackFitType::TrackWord (&trackWord_o)[kMaxTrack], + TrackFitType::BarrelStubWord (&barrelStubWords_o)[kMaxTrack][trklet::N_LAYER], + TrackFitType::DiskStubWord (&diskStubWords_o)[kMaxTrack][trklet::N_DISK] + ); -#endif \ No newline at end of file +#endif diff --git a/TrackletAlgorithm/Constants.h b/TrackletAlgorithm/Constants.h index 6e2661af384..f258cf3fe37 100644 --- a/TrackletAlgorithm/Constants.h +++ b/TrackletAlgorithm/Constants.h @@ -286,7 +286,7 @@ enum regionType {BARRELPS, BARREL2S, BARRELOL, BARREL, DISKPS, DISK2S, DISK, BAR namespace TF { // List of seeds - enum seed {UNDEF_SEED, L1L2 = 0, L2L3 = 1, L3L4 = 2, L5L6 = 3, D1D2 = 4, D3D4 = 5, L1D1 = 6, L2D1 = 7}; + enum seed {UNDEF_SEED, L1L2 = 0, L2L3 = 1, L3L4 = 2, L5L6 = 3, D1D2 = 4, D3D4 = 5, L1D1 = 6, L2D1 = 7, AAAA = 12, BBBB = 13}; // List of layers and disks enum layerDisk {L1 = 0, L2 = 1, L3 = 2, L4 = 3, L5 = 4, L6 = 5, D1 = 6, D2 = 7, D3 = 8, D4 = 9, D5 = 10}; @@ -297,8 +297,8 @@ namespace TF { // List of layer and disk regions constexpr regionType layerDiskRegion[trklet::N_LAYER + trklet::N_DISK] = {BARREL, BARREL, BARREL, BARREL, BARREL, BARREL, DISK, DISK, DISK, DISK, DISK}; - // List of phi regions - enum phiRegion {UNDEF_PHI, A = 0, B = 1, C = 2, D = 3, E = 4, F = 5, G = 6, H = 7, I = 8, J = 9, K = 10, L = 11, M = 12, N = 13, O = 14}; + // List of phi regions //WARNING B_E and C_E should be B and C + 16!!! + enum phiRegion {UNDEF_PHI, A = 0, B = 1, C = 2, D = 3, E = 4, F = 5, G = 6, H = 7, I = 8, J = 9, K = 10, L = 11, M = 12, N = 13, O = 14, B_E = B + 16, C_E = C + 16}; } // Layers used for each of the seeds diff --git a/TrackletAlgorithm/InputRouter.h b/TrackletAlgorithm/InputRouter.h index 5c79e071584..7c881b97384 100644 --- a/TrackletAlgorithm/InputRouter.h +++ b/TrackletAlgorithm/InputRouter.h @@ -200,21 +200,6 @@ void getPhiBin( ap_uint hStbWrd phiBn = cBn; } -// clear internal counters -template -void ClearCounters(unsigned int nMemories - , ap_uint nEntries[nEntriesSize]) -{ -#pragma HLS inline -#pragma HLS array_partition variable = nEntries complete - LOOP_ClearCounters: - for (unsigned int cIndx = 0; cIndx < nEntriesSize ; cIndx++) - { -#pragma HLS unroll - nEntries[cIndx]=0; - } -} - // internal memory counter template void CountMemories(const ap_uint hPhBnWord @@ -314,9 +299,6 @@ void InputRouter( const BXType bx unsigned int nMems=0; unsigned int nMemsPerLyr[kMaxLyrsPerDTC]; CountMemories(hPhBnWord, nMems, nMemsPerLyr); - // clear stub counters - ap_uint hNStubs[nOMems]; - ClearCounters(nMems, hNStubs); LOOP_ProcessIR: for (int cStubCounter = 0; cStubCounter < kMaxProc; cStubCounter++) @@ -397,11 +379,8 @@ void InputRouter( const BXType bx #endif #endif - // update counters - auto hEntries = hNStubs[cMemIndx]; - hNStubs[cMemIndx] = hEntries + 1; // fill memory - (&hOutputStubs[cMemIndx])->write_mem(bx, hMemWord, hEntries); + (&hOutputStubs[cMemIndx])->write_mem(hMemWord); } // update output bx port bx_o = bx; diff --git a/TrackletAlgorithm/MatchProcessor.h b/TrackletAlgorithm/MatchProcessor.h index 4eefa42b5f1..400682e61d3 100644 --- a/TrackletAlgorithm/MatchProcessor.h +++ b/TrackletAlgorithm/MatchProcessor.h @@ -917,7 +917,6 @@ void MatchCalculator(BXType bx, ){ #pragma HLS inline -#pragma HLS array_partition variable=fullmatch complete dim=1 using namespace PR; @@ -1128,47 +1127,11 @@ void MatchCalculator(BXType bx, } if(goodmatch) { // Write out only the best match, based on the seeding - switch (proj_seed) { - case 0: - if(FMMask()) { - fullmatch[FMCount()].write_mem_new(bx,fm,savedMatch); // L1L2 seed - } - break; - case 1: - if(FMMask()) { - fullmatch[FMCount()].write_mem_new(bx,fm,savedMatch); // L2L3 seed - } - break; - case 2: - if(FMMask()) { - fullmatch[FMCount()].write_mem_new(bx,fm,savedMatch); // L3L4 seed - } - break; - case 3: - if(FMMask()) { - fullmatch[FMCount()].write_mem_new(bx,fm,savedMatch); // L5L6 seed - } - break; - case 4: - if(FMMask()) { - fullmatch[FMCount()].write_mem_new(bx,fm,savedMatch); // D1D2 seed - } - break; - case 5: - if(FMMask()) { - fullmatch[FMCount()].write_mem_new(bx,fm,savedMatch); // D3D4 seed - } - break; - case 6: - if(FMMask()) { - fullmatch[FMCount()].write_mem_new(bx,fm,savedMatch); // L1D1 seed - } - break; - case 7: - if(FMMask()) { - fullmatch[FMCount()].write_mem_new(bx,fm,savedMatch); // L2D1 seed - } - break; + + if (proj_seed == TF::L1L2 || proj_seed == TF::L2L3 || proj_seed == TF::L5L6 || proj_seed == TF::L2D1 || maxFullMatchVariants == 1) { + fullmatch[0].write_mem(fm,savedMatch); // AAAA FM + } else { + fullmatch[1].write_mem(fm,savedMatch); // BBBB FM } savedMatch = 1; } @@ -1192,6 +1155,7 @@ void MatchProcessor(BXType bx, BXType& bx_o, FullMatchMemory fullmatch[maxFullMatchVariants] ){ +#pragma HLS latency min=11 max=11 #pragma HLS inline using namespace PR; @@ -1248,6 +1212,7 @@ void MatchProcessor(BXType bx, ap_uint mem_hasdata = 0; #pragma HLS ARRAY_PARTITION variable=numbersin complete +#pragma HLS array_partition variable=fullmatch init> (bx, iMem, iPage, nPages, mem_hasdata, numbersin, projin); @@ -1256,18 +1221,6 @@ void MatchProcessor(BXType bx, ap_uint mem_read_addr = 0; ap_uint read_address = 0; - //The next projection to read, the number of projections and flag if we have - //more projections to read - - ap_uint<8> vmstubsmask[16]; -#pragma HLS array_partition variable=vmstubsmask complete dim=1 - - entriesloop:for(unsigned int i=0; i<16; i++) { -#pragma HLS unroll - vmstubsmask[i]=instubdata.getBinMask8(bx,i); - } - - constexpr int nPRBAbits = 3; ProjectionRouterBufferArray projbufferarray; @@ -1636,10 +1589,15 @@ void MatchProcessor(BXType bx, ap_uint<1> useSecond = zbin.range(0,0) == 1; - ap_uint<1> usefirstMinus = vmstubsmask[slot][ivmMinus]; - ap_uint<1> usesecondMinus = useSecond && vmstubsmask[slot+1][ivmMinus]; - ap_uint<1> usefirstPlus = ivmPlus != ivmMinus && vmstubsmask[slot][ivmPlus]; - ap_uint<1> usesecondPlus = ivmPlus != ivmMinus && useSecond && vmstubsmask[slot+1][ivmPlus]; + ap_uint<1 + nZbinBits> tmp((bx&1)*(1< tmpplusone((bx&1)*(1< vmstubsmasktmpA = instubdata.getBinMaskA(tmp); + ap_uint<8> vmstubsmasktmpB = instubdata.getBinMaskB(tmpplusone); + + ap_uint<1> usefirstMinus = vmstubsmasktmpA[ivmMinus]; + ap_uint<1> usesecondMinus = useSecond && vmstubsmasktmpB[ivmMinus]; + ap_uint<1> usefirstPlus = ivmPlus != ivmMinus && vmstubsmasktmpA[ivmPlus]; + ap_uint<1> usesecondPlus = ivmPlus != ivmMinus && useSecond && vmstubsmasktmpB[ivmPlus]; increase = usefirstPlus || usesecondPlus || usefirstMinus || usesecondMinus; diff --git a/TrackletAlgorithm/MemoryTemplate.h b/TrackletAlgorithm/MemoryTemplate.h index db6337eccf3..c2b4f46c1dc 100644 --- a/TrackletAlgorithm/MemoryTemplate.h +++ b/TrackletAlgorithm/MemoryTemplate.h @@ -3,6 +3,9 @@ #define TrackletAlgorithm_MemoryTemplate_h #include +#include +#include +#include //This is a bit of a hack, but until we find a cleaner //way to implement this we will use this... @@ -48,109 +51,56 @@ class MemoryTemplate DataType dataarray_[DEPTH_BX][DEPTH_ADDR]; // data array NEntryT nentries_[DEPTH_BX]; // number of entries +#if !(defined __SYNTHESIS__ && !defined SYNTHESIS_TEST_BENCH) + BunchXingT write_bx_; //BX for writing +#endif public: unsigned int getDepth() const {return DEPTH_ADDR;} unsigned int getNBX() const {return DEPTH_BX;} - NEntryT getEntries(BunchXingT bx) const { + NEntryT getEntries(const BunchXingT& bx) const { #pragma HLS ARRAY_PARTITION variable=nentries_ complete dim=0 return nentries_[bx]; } +#if !(defined __SYNTHESIS__ && !defined SYNTHESIS_TEST_BENCH) + void setWriteBX(const BunchXingT& ibx) { + write_bx_ = ibx; + } +#endif + const DataType (&get_mem() const)[DEPTH_BX][DEPTH_ADDR] {return dataarray_;} - DataType read_mem(BunchXingT ibx, ap_uint index) const + DataType read_mem(const BunchXingT& ibx, const ap_uint &index) const { // TODO: check if valid - if(!NBIT_BX) ibx = 0; + if(!NBIT_BX) assert(ibx == 0); return dataarray_[ibx][index]; } - - template - bool write_mem(BunchXingT ibx, SpecType data) - { -#pragma HLS inline - const NEntryT addr_index = -#ifdef __SYNTHESIS__ - 0; -#else - nentries_[ibx]; -#endif - return write_mem(ibx,data,addr_index); - } - - template - bool write_mem(BunchXingT ibx, SpecType data, NEntryT addr_index) - { -#pragma HLS inline - if(!NBIT_BX) ibx = 0; - static_assert( - std::is_same::value - || (std::is_same >::value && std::is_same >::value) - || (std::is_same >::value && std::is_same >::value) - , "Invalid conversion between data types"); - DataType sameData(data.raw()); - return write_mem(ibx,sameData,addr_index); - } - - bool write_mem(BunchXingT ibx, DataType data) - { -#pragma HLS inline - const NEntryT addr_index = -#ifdef __SYNTHESIS__ - 0; -#else - nentries_[ibx]; -#endif - return write_mem(ibx,data,addr_index); - } - - bool write_mem(BunchXingT ibx, DataType data, NEntryT addr_index) + + bool write_mem(const DataType& data, ap_uint<1> overwrite=0) { -#pragma HLS ARRAY_PARTITION variable=nentries_ complete dim=0 #pragma HLS inline - if(!NBIT_BX) ibx = 0; - if (addr_index < DEPTH_ADDR) { #if defined __SYNTHESIS__ && !defined SYNTHESIS_TEST_BENCH //The vhd memory implementation will write to the correct address!! - dataarray_[ibx][0] = data; -#else - dataarray_[ibx][nentries_[ibx]++] = data; -#endif - -#ifndef __SYNTHESIS__ - nentries_[ibx] = addr_index + 1; -#endif - + dataarray_[0][overwrite] = data; return true; - } else { - return false; - } - } - - bool write_mem_new(BunchXingT ibx, DataType data, ap_uint<1> overwrite) - { -#pragma HLS ARRAY_PARTITION variable=nentries_ complete dim=0 -#pragma HLS inline - if(!NBIT_BX) ibx = 0; - if (nentries_[ibx] < DEPTH_ADDR) { -#if defined __SYNTHESIS__ && !defined SYNTHESIS_TEST_BENCH - //The vhd memory implementation will write to the correct address!! - dataarray_[ibx][0] = data; #else +#pragma HLS ARRAY_PARTITION variable=nentries_ complete dim=0 + if(!NBIT_BX) write_bx_ = 0; + if (nentries_[write_bx_] < DEPTH_ADDR) { if(overwrite == 0) { - dataarray_[ibx][nentries_[ibx]++] = data; + dataarray_[write_bx_][nentries_[write_bx_]++] = data; } else { - dataarray_[ibx][nentries_[ibx]-1] = data; + dataarray_[write_bx_][nentries_[write_bx_]-1] = data; } -#endif - return true; } else { return false; } +#endif } // Methods for C simulation only @@ -165,43 +115,35 @@ class MemoryTemplate void clear() { DataType data("0",16); + setWriteBX(0); MEM_RST: for (size_t ibx=0; ibx& split_line, int base=16) { + assert(split_line.size()==3); + DataType data(split_line.back().c_str(), base); - return success; - } - - bool write_mem(BunchXingT ibx, const std::string& datastr, int base=16) - { - return write_mem(ibx, datastr.c_str(), base); + return write_mem(data); } // print memory contents - void print_data(const DataType data) const + void print_data(const DataType& data) const { edm::LogVerbatim("L1trackHLS") << std::hex << data.raw() << std::endl; // TODO: overload '<<' in data class } - void print_entry(BunchXingT bx, NEntryT index) const + void print_entry(const BunchXingT& bx, NEntryT index) const { print_data(dataarray_[bx][index]); } - void print_mem(BunchXingT bx) const + void print_mem(const BunchXingT& bx) const { for (unsigned int i = 0; i < nentries_[bx]; ++i) { edm::LogVerbatim("L1trackHLS") << bx << " " << i << " "; diff --git a/TrackletAlgorithm/MemoryTemplateBinnedCM.h b/TrackletAlgorithm/MemoryTemplateBinnedCM.h index cf1a28d1a4d..0557928992f 100644 --- a/TrackletAlgorithm/MemoryTemplateBinnedCM.h +++ b/TrackletAlgorithm/MemoryTemplateBinnedCM.h @@ -13,6 +13,11 @@ #endif #endif +#include +#include +#include +#include + //This is a bit of a hack, but until we find a cleaner //way to implement this we will use this... #include "SynthesisOptions.h" @@ -60,15 +65,23 @@ class MemoryTemplateBinnedCM{ kNSlots = DEPTH_BIN, kNMemDepth = DEPTH_ADDR, kNBitsRZBinCM = NBIT_BIN-kNBitsphibinCM, - kNBinsRZ = (1< binmask8_[kNBxBins][1< nentries_[slots]; + ap_uint<8> binmaskA_[slots]; + ap_uint<8> binmaskB_[slots]; + + +#if !(defined __SYNTHESIS__ && !defined SYNTHESIS_TEST_BENCH) + ap_uint<4> nentriestmp_[1< slot) const { + ap_uint<8> getBinMaskA(const ap_uint& addrbinmaskA) const { + // std::cout << "getBinMaskA:" << addrbinmaskA << std::endl; + return binmaskA_[addrbinmaskA]; + } + + ap_uint<8> getBinMaskB(const ap_uint& addrbinmaskB) const { + return binmaskB_[addrbinmaskB]; + } + +#if !(defined __SYNTHESIS__ && !defined SYNTHESIS_TEST_BENCH) + void setWriteBX(const BunchXingT& ibx) { + write_bx_ = ibx; + } +#endif + + NEntryT getEntries(const BunchXingT& bx, ap_uint slot) const { ap_uint ibin; ap_uint ireg; (ireg,ibin)=slot; return nentries_[bx][ibin].range(ireg*4+3,ireg*4); } - ap_uint<64> getEntries(BunchXingT bx, ap_uint ibin) const { + ap_uint<64> getEntries(const BunchXingT& bx, ap_uint ibin) const { return nentries_[bx*(1< getBinMask8(BunchXingT bx, ap_uint ibin) const { -#pragma HLS ARRAY_PARTITION variable=binmask8_ complete dim=0 - return binmask8_[bx][ibin]; - } - - NEntryT getEntries(BunchXingT bx) const { + NEntryT getEntries(const BunchXingT& bx) const { NEntryT val = 0; for ( auto i = 0; i < getDepth(); ++i ) { val += getEntries(bx, i); @@ -113,68 +136,73 @@ class MemoryTemplateBinnedCM{ } #endif - DataType read_mem(unsigned int icopy, BunchXingT ibx, ap_uint index) const { + DataType read_mem(unsigned int icopy, const BunchXingT& ibx, ap_uint index) const { #pragma HLS ARRAY_PARTITION variable=dataarray_ dim=1 // TODO: check if valid - if (isCMSSW) {ibx = 0; icopy = 0;} + if (isCMSSW) {assert(ibx == 0 && icopy == 0);} return dataarray_[icopy][ibx][index]; } - DataType read_mem(unsigned int icopy, BunchXingT ibx, ap_uint slot, - ap_uint index) const { + DataType read_mem(unsigned int icopy, const BunchXingT& ibx, + ap_uint slot, ap_uint index) const { #pragma HLS ARRAY_PARTITION variable=dataarray_ dim=1 // TODO: check if valid - if (isCMSSW) {ibx = 0; icopy = 0;} + if (isCMSSW) {assert(ibx == 0 && icopy == 0);} return dataarray_[icopy][ibx][getNEntryPerBin()*slot+index]; } - bool write_mem(BunchXingT ibx, ap_uint slot, DataType data, unsigned int nentry_ibx) { + bool write_mem(ap_uint slot, const DataType& data) { #pragma HLS ARRAY_PARTITION variable=dataarray_ dim=1 -#pragma HLS ARRAY_PARTITION variable=binmask8_ complete dim=0 #pragma HLS ARRAY_PARTITION variable=nentries_ complete dim=0 #pragma HLS inline - if (isCMSSW && !NBIT_BX) {ibx = 0;} - if (nentry_ibx < getNEntryPerBin()-1) { // Max 15 stubs in each memory due to 4 bit nentries #if defined __SYNTHESIS__ && !defined SYNTHESIS_TEST_BENCH - - dataarray_[0][ibx][getNEntryPerBin()*slot] = data; + //The vhdl implementation will write to the correct address + dataarray_[0][0][slot] = data; + return true; #else - // write address for slot: getNEntryPerBin() * slot + nentry_ibx +#pragma HLS ARRAY_PARTITION variable=nentriestmp_ complete dim=0 - ap_uint ibin; - ap_uint ireg; - (ibin,ireg)=slot; + if (isCMSSW && !NBIT_BX) {write_bx_ = 0;} - unsigned int nentry = nentries_[ibx*kNBinsRZ+ibin].range(ireg*4+3,ireg*4); + ap_uint ibin; + ap_uint ireg; + (ibin,ireg)=slot; - if (nentry == ((1 << (NBIT_ADDR-NBIT_BIN)) - 1)) return false; + unsigned int nentry = nentriestmp_[slot]; - nentries_[ibx*kNBinsRZ+ibin].range(ireg*4+3,ireg*4)=nentry+1; - if (ibin!=0) { - nentries_[ibx*kNBinsRZ+ibin-1].range((ireg+8)*4+3,(ireg+8)*4)=nentry+1; - } - binmask8_[ibx][ibin].set_bit(ireg,true); + if (nentry == ((1 << (NBIT_ADDR-NBIT_BIN)) - 1)) return false; - //icopy comparison must be signed int or future SW fails - writememloop:for (signed int icopy=0;icopy< (signed) NCP;icopy++) { -#pragma HLS unroll - dataarray_[icopy][ibx][getNEntryPerBin()*slot+nentry] = data; - } -#endif - return true; + nentries_[write_bx_*kNBinsRZ+ibin].range(ireg*4+3,ireg*4)=nentry+1; + //The next ifdef is a real hack. In order to meet II=1 for test benches + //where we write to a VM memory we don't properly fill the nentries_ + //array. This works because the test benches does not check the nentries_ + //However, in a testbench when we read in a VM memory we need the + //nentries_ to be properly set for use in the TP or MP modules + +#if !defined __SYNTHESIS__ + if (ibin!=0) { + nentries_[write_bx_*kNBinsRZ+ibin-1].range((ireg+8)*4+3,(ireg+8)*4)=nentry+1; } - else { -#ifndef __SYNTHESIS__ - if (data.raw() != 0) { // To avoid lots of prints when we're clearing the memories - edm::LogVerbatim("L1trackHLS") << "Warning out of range. nentry_ibx = "< split(const std::string& s, char delimiter) - { - std::vector tokens; - std::string token; - std::istringstream sstream(s); - while (getline(sstream, token, delimiter)) - { - tokens.push_back(token); - } - return tokens; + for (size_t ibin=0; ibin < slots; ibin++) { + nentries_[ibin] = 0; + } + } // write memory from text file - bool write_mem(BunchXingT ibx, const std::string& line, int base=16) - { + bool write_mem(const std::vector& split_line, int base=16) { - if (isCMSSW) {ibx = 0;} + assert(split_line.size()==4); - std::string datastr = split(line, ' ').back(); + if (isCMSSW) {write_bx_ = 0;} - int slot = (int)strtol(split(line, ' ').front().c_str(), nullptr, base); // Convert string (in hexadecimal) to int + std::string datastr = split_line.back(); - ap_uint ibin; - ap_uint ireg; - (ibin, ireg)=slot; - ap_uint<4> nentry_ibx = nentries_[ibx*kNBinsRZ+ibin].range(ireg*4+3,ireg*4); + int slot = (int)strtol(split_line.front().c_str(), nullptr, base); // Convert string (in hexadecimal) to int DataType data(datastr.c_str(), base); - bool success = write_mem(ibx, slot, data, nentry_ibx); + bool success = write_mem(slot, data); return success; } - + // print memory contents - void print_data(const DataType data) const + void print_data(const DataType& data) const { edm::LogVerbatim("L1trackHLS") << std::hex << data.raw() << std::endl; // TODO: overload '<<' in data class } - void print_entry(BunchXingT bx, ap_uint index) const + void print_entry(const BunchXingT& bx, ap_uint index) const { print_data(dataarray_[bx][index]); } - //These are broken - comment out for now (ryd, 2024-10-27) - /* - void print_mem(BunchXingT bx) const { - for(unsigned int ibin=0;ibin<8;ibin++) { - for(unsigned int ireg=0;ireg<8;ireg++) { - for (unsigned int i = 0; i < nentries_[ibx*kNBinsRZ+ibin].range(ireg*4+3,ireg*4); ++i) { - edm::LogVerbatim("L1trackHLS") << bx << " " << i << " "; - print_entry(bx, i + slot*getNEntryPerBin() ); - } - } - } - } - - void print_mem() const { - for (unsigned int ibx = 0; ibx < kNBxBins; ++ibx) { - for (unsigned int i = 0; i < 8; ++i) { - edm::LogVerbatim("L1trackHLS") << ibx << " " << i << " "; - print_entry(ibx,i); - } - } - } - */ - static constexpr int getWidth() {return DataType::getWidth();} #endif diff --git a/TrackletAlgorithm/MemoryTemplateTPROJ.h b/TrackletAlgorithm/MemoryTemplateTPROJ.h index c355ab55b73..4e4635ec916 100644 --- a/TrackletAlgorithm/MemoryTemplateTPROJ.h +++ b/TrackletAlgorithm/MemoryTemplateTPROJ.h @@ -1,17 +1,17 @@ -// Class template for memory module +// Class template for memory module with pages #ifndef TrackletAlgorithm_MemoryTemplateTPROJ_h #define TrackletAlgorithm_MemoryTemplateTPROJ_h #include -#include "../TestBenches/FileReadUtility.h" +#include +#include +#include //This is a bit of a hack, but until we find a cleaner //way to implement this we will use this... #include "SynthesisOptions.h" -template class AllStub; - #ifndef __SYNTHESIS__ #ifdef CMSSW_GIT_HASH #include "FWCore/MessageLogger/interface/MessageLogger.h" @@ -69,6 +69,9 @@ class MemoryTemplateTPROJ DataType dataarray_[DEPTH_BX][NPAGE*DEPTH_ADDR]; // data array NEntryT nentries_[DEPTH_BX*NPAGE]; // number of entries ap_uint mask_[DEPTH_BX]; //bitmask for hits +#if !(defined __SYNTHESIS__ && !defined SYNTHESIS_TEST_BENCH) + BunchXingT write_bx_; //BX for writing +#endif public: @@ -76,66 +79,52 @@ class MemoryTemplateTPROJ unsigned int getNBX() const {return DEPTH_BX;} unsigned int getNPage() const {return NPAGE;} - NEntryT getEntries(BunchXingT bx, unsigned int page = 0) const { +#if !(defined __SYNTHESIS__ && !defined SYNTHESIS_TEST_BENCH) + void setWriteBX(const BunchXingT& ibx) { + write_bx_ = ibx; + } +#endif + + NEntryT getEntries(const BunchXingT& bx, unsigned int page = 0) const { #pragma HLS ARRAY_PARTITION variable=nentries_ complete dim=0 #pragma HLS inline return nentries_[bx*NPAGE+page]; } - ap_uint getMask(BunchXingT bx) const { -#pragma HLS ARRAY_PARTITION variable=mask__ complete dim=0 + ap_uint getMask(const BunchXingT& bx) const { +#pragma HLS ARRAY_PARTITION variable=mask_ complete dim=0 #pragma HLS inline return mask_[bx]; } const DataType (&get_mem() const)[DEPTH_BX][(DEPTH_ADDR)*NPAGE] {return dataarray_;} - DataType read_mem(BunchXingT ibx, ap_uint index, unsigned int page = 0) const + DataType read_mem(const BunchXingT& ibx, ap_uint index, unsigned int page = 0) const { - //assert(page < NPAGE); // TODO: check if valid - if(!NBIT_BX) ibx = 0; + if(!NBIT_BX) assert(ibx == 0); return dataarray_[ibx][DEPTH_ADDR*page+index]; } - template - bool write_mem(BunchXingT ibx, SpecType data, NEntryT addr_index, unsigned int page) + bool write_mem(const DataType& data, unsigned int page) { +#pragma HLS ARRAY_PARTITION variable=mask_ complete dim=0 +#pragma HLS ARRAY_PARTITION variable=nentries_ complete dim=0 #pragma HLS inline - if(!NBIT_BX) ibx = 0; - static_assert( - std::is_same::value - || (std::is_same >::value && std::is_same >::value) - || (std::is_same >::value && std::is_same >::value) - , "Invalid conversion between data types"); - DataType sameData(data.raw()); - return write_mem(ibx, sameData, addr_index, page); - } - - bool write_mem(BunchXingT ibx, DataType data, NEntryT addr_index, unsigned int page = 0) - { - //assert(page < NPAGE); -#pragma HLS inline - if(!NBIT_BX) ibx = 0; - if (addr_index < DEPTH_ADDR) { - //dataarray_[ibx][addr_index] = data; #if defined __SYNTHESIS__ && !defined SYNTHESIS_TEST_BENCH - //The vhd memory implementation will write to the correct address!! - dataarray_[ibx][DEPTH_ADDR*page+addr_index] = data; + //The vhd memory implementation will write to the correct address!! + dataarray_[0][page] = data; #else - //NBIT_BX==1 is to identify the projection memories - if (NBIT_BX==1 && nentries_[ibx*NPAGE+page]>=MAX_TPROJ_PAGE_SIZE) { - return false; - } - dataarray_[ibx][DEPTH_ADDR*page+nentries_[ibx*NPAGE+page]++] = data; - mask_[ibx].set(page); - -#endif - - return true; - } else { + if(!NBIT_BX) assert(write_bx_ == 0); + //NBIT_BX==1 is to identify the projection memories + if (NBIT_BX==1 && nentries_[write_bx_*NPAGE+page]>=MAX_TPROJ_PAGE_SIZE) { return false; } + dataarray_[write_bx_][DEPTH_ADDR*page+nentries_[write_bx_*NPAGE+page]++] = data; + mask_[write_bx_].set_bit(page,true); +#endif + return true; + } // Methods for C simulation only @@ -161,67 +150,34 @@ class MemoryTemplateTPROJ } } - bool write_mem_clear(BunchXingT ibx, DataType data, NEntryT addr_index, unsigned int page) + bool write_mem(const std::vector& split_line, int base=16) { - if(!NBIT_BX) ibx = 0; - if (addr_index < DEPTH_ADDR) { - //FIXME - shoudl this method be removed? - return true; - } else { - return false; - } - } - - - // write memory from text file - bool write_mem(BunchXingT ibx, const char* datastr, int base=16, unsigned int page = 0 ) { + assert(split_line.size()==4); + const std::string datastr = split_line.back(); - if(!NBIT_BX) ibx = 0; - - DataType data(datastr, base); - NEntryT nent = nentries_[ibx*NPAGE+page]; - bool success = write_mem(ibx, data, nent, page); + unsigned int page = (int)strtol(split_line.front().c_str(), nullptr, base); // Convert string (in hexadecimal) to int - return success; - } - - bool write_mem(BunchXingT ibx, const std::string& line, int base=16) - { - assert(split(line,' ').size()==4); - - const std::string datastr = split(line,' ').back(); - - const std::string pagestr = split(line,' ').front(); - - unsigned int page = NPAGE; - if (pagestr=="0x00") page = 0; - if (pagestr=="0x01") page = 1; - if (pagestr=="0x02") page = 2; - if (pagestr=="0x03") page = 3; - assert(page < NPAGE); - - if(!NBIT_BX) ibx = 0; DataType data(datastr.c_str(), base); - NEntryT nent = nentries_[ibx*NPAGE+page]; - bool success = write_mem(ibx, data, nent, page); + + bool success = write_mem(data, page); return success; } // print memory contents - void print_data(const DataType data) const + void print_data(const DataType& data) const { edm::LogVerbatim("L1trackHLS") << std::hex << data.raw() << std::endl; // TODO: overload '<<' in data class } - void print_entry(BunchXingT bx, NEntryT index, unsigned int page = 0) const + void print_entry(const BunchXingT& bx, NEntryT index, unsigned int page = 0) const { print_data(dataarray_[bx][DEPTH_ADDR*page+index]); } - void print_mem(BunchXingT bx) const { + void print_mem(const BunchXingT& bx) const { for (unsigned int page = 0; page < NPAGE; ++page) { for (unsigned int i = 0; i < nentries_[bx*NPAGE+page]; ++i) { edm::LogVerbatim("L1trackHLS") << bx << " " << i << " "; diff --git a/TrackletAlgorithm/ProjectionCalculator.h b/TrackletAlgorithm/ProjectionCalculator.h index 84288d7b0fe..d06653833d8 100644 --- a/TrackletAlgorithm/ProjectionCalculator.h +++ b/TrackletAlgorithm/ProjectionCalculator.h @@ -41,24 +41,22 @@ PC::addProj(const TrackletProjection &proj, const BXType bx, Tracklet int ipage = trackletIndex >> kNBits_MemAddr; - trackletIndex = trackletIndex&((1 << kNBits_MemAddr) -1); - if (NProjOut > 0 && TPROJMask & (0x1 << 0) && success && proj_success && phi == 0) - projout[0].write_mem(bx, proj, trackletIndex, ipage); + projout[0].write_mem(proj, ipage); if (NProjOut > 1 && TPROJMask & (0x1 << 1) && success && proj_success && phi == 1) - projout[1].write_mem(bx, proj, trackletIndex, ipage); + projout[1].write_mem(proj, ipage); if (NProjOut > 2 && TPROJMask & (0x1 << 2) && success && proj_success && phi == 2) - projout[2].write_mem(bx, proj, trackletIndex, ipage); + projout[2].write_mem(proj, ipage); if (NProjOut > 3 && TPROJMask & (0x1 << 3) && success && proj_success && phi == 3) - projout[3].write_mem(bx, proj, trackletIndex, ipage); + projout[3].write_mem(proj, ipage); if (NProjOut > 4 && TPROJMask & (0x1 << 4) && success && proj_success && phi == 4) - projout[4].write_mem(bx, proj, trackletIndex, ipage); + projout[4].write_mem(proj, ipage); if (NProjOut > 5 && TPROJMask & (0x1 << 5) && success && proj_success && phi == 5) - projout[5].write_mem(bx, proj, trackletIndex, ipage); + projout[5].write_mem(proj, ipage); if (NProjOut > 6 && TPROJMask & (0x1 << 6) && success && proj_success && phi == 6) - projout[6].write_mem(bx, proj, trackletIndex, ipage); + projout[6].write_mem(proj, ipage); if (NProjOut > 7 && TPROJMask & (0x1 << 7) && success && proj_success && phi == 7) - projout[7].write_mem(bx, proj, trackletIndex, ipage); + projout[7].write_mem(proj, ipage); return (success && proj_success); } @@ -80,12 +78,13 @@ template< TrackletProjectionMemory projout_barrel_2s[TP::N_PROJOUT_BARREL2S], TrackletProjectionMemory projout_disk[TP::N_PROJOUT_DISK]) { - +#pragma HLS latency min=13 max=13 + if (!valid) return; - int ipage = trackletIndex >> 7; + int ipage = trackletIndex >> kNBits_MemAddr; - tparout.write_mem(bx, tpar, trackletIndex&((1 << kNBits_MemAddr) -1), ipage); + tparout.write_mem(tpar, ipage); // Load the initial track parameters (phi0, z0, t, rinv) TrackletParameters::PHI0PAR phi0 = tpar.getPhi0(); @@ -250,6 +249,8 @@ template< nproj_disk[i] = 0; } + ipage = ipage & ((1 << kNBits_MemTPage) - 1); + //iTC gives you the first TCID in e.g. ABC, ipage gives you corrected TCID for B and C const int TCID = ((TrackletProjection::TProjTCID(Seed) << TrackletProjection::kTProjITCSize) + iTC + ipage); bool addL3 = false, addL4 = false, addL5 = false, addL6 = false; // whether a projection has been added successfully diff --git a/TrackletAlgorithm/TrackBuilder.h b/TrackletAlgorithm/TrackBuilder.h index 7af4c27d237..3f508e9aab4 100644 --- a/TrackletAlgorithm/TrackBuilder.h +++ b/TrackletAlgorithm/TrackBuilder.h @@ -1,6 +1,7 @@ #ifndef TrackletAlgorithm_TrackBuilder_h #define TrackletAlgorithm_TrackBuilder_h +#include "Constants.h" #include "TrackletParameterMemory.h" #include "FullMatchMemory.h" #include "TrackFitMemory.h" @@ -21,8 +22,7 @@ typedef ap_uint ITCType; typedef ap_uint IndexType; typedef ap_uint TrackletIDType; -template void -setTrackPars(TrackFit &track, const TrackletParameters &tpar) +void setTrackPars(TrackFit &track, const TrackletParameters &tpar) { track.setPhiRegionInner(tpar.getPhiRegion()); track.setStubIndexInner(tpar.getStubIndexInner()); @@ -74,13 +74,13 @@ class Merger { if (!valid_A_) { in_A_ = in_A; valid_A_ = valid_A; - read_A = true; + read_A = valid_A; } if (!valid_B_) { in_B_ = in_B; valid_B_ = valid_B; - read_B = true; + read_B = valid_B; } first_A_ = (valid_A_ && valid_B_ @@ -104,7 +104,9 @@ class Merger { }; // TrackBuilder top template function -template +// NFMPerStubBarrel/Disk uses 3 bits for each layer and disk +// +template void TrackBuilder( const BXType bx, const TrackletParameterMemory1 trackletParameters1[], @@ -114,70 +116,134 @@ void TrackBuilder( const FullMatchMemory barrelFullMatches[], const FullMatchMemory diskFullMatches[], BXType &bx_o, - typename TrackFit::TrackWord trackWord[], - typename TrackFit::BarrelStubWord barrelStubWords[][kMaxProc], - typename TrackFit::DiskStubWord diskStubWords[][kMaxProc], + typename TrackFit::TrackWord trackWord[], + typename TrackFit::BarrelStubWord barrelStubWords[][kMaxProc], + typename TrackFit::DiskStubWord diskStubWords[][kMaxProc], bool &done ) { - // The ordered merges are currently configured assuming four FM memories per - // layer/disk or potentially eight in the first layer. Other numbers would - // require setting up the code differently. - static_assert(NFMPerStubBarrel0 == 4 - || NFMPerStubBarrel0 == 8 - || NFMPerStubBarrel == 4 - || NFMPerStubDisk == 4, - "Ordered merges require 4 or 8 FM memories per layer/disk."); + constexpr unsigned int mergerDepth = 3; + constexpr unsigned int maxFMLayer = (1<>4)&15, + (NFMPerStubBarrel>>8)&15, + (NFMPerStubBarrel>>12)&15, + (NFMPerStubBarrel>>16)&15, + (NFMPerStubBarrel>>20)&15 + }; + + constexpr unsigned int NFMDisk[trklet::N_DISK] = { + NFMPerStubDisk&15, + (NFMPerStubDisk>>4)&15, + (NFMPerStubDisk>>8)&15, + (NFMPerStubDisk>>12)&15, + (NFMPerStubDisk>>16)&15}; + + constexpr unsigned int FMBarrelStart[trklet::N_LAYER] = { + 0, + NFMBarrel[0], + NFMBarrel[0]+NFMBarrel[1], + NFMBarrel[0]+NFMBarrel[1]+NFMBarrel[2], + NFMBarrel[0]+NFMBarrel[1]+NFMBarrel[2]+NFMBarrel[3], + NFMBarrel[0]+NFMBarrel[1]+NFMBarrel[2]+NFMBarrel[3]+NFMBarrel[4]}; + + constexpr unsigned int FMDiskStart[trklet::N_DISK] = { + 0, + NFMDisk[0], + NFMDisk[0]+NFMDisk[1], + NFMDisk[0]+NFMDisk[1]+NFMDisk[2], + NFMDisk[0]+NFMDisk[1]+NFMDisk[2]+NFMDisk[3]}; + + /* + std::cout << "NFMBarrel:"; + for(unsigned int i=0; i > merger_L_top[NBarrelStubs], // root node - merger_L_b1[NBarrelStubs], merger_L_b2[NBarrelStubs], // first level - merger_L_b1_b1, merger_L_b1_b2, merger_L_b2_b1, merger_L_b2_b2; // second level (only used for the first layer) - + Merger > + merger_L_top[NBarrelStubs], // root node + merger_L_b1[NBarrelStubs], + merger_L_b2[NBarrelStubs], // first level + merger_L_b1_b1[NBarrelStubs], + merger_L_b1_b2[NBarrelStubs], + merger_L_b2_b1[NBarrelStubs], + merger_L_b2_b2[NBarrelStubs]; + + Merger > + merger_D_top[NDiskStubs], // root node + merger_D_b1[NDiskStubs], + merger_D_b2[NDiskStubs], // first level + merger_D_b1_b1[NDiskStubs], + merger_D_b1_b2[NDiskStubs], + merger_D_b2_b1[NDiskStubs], + merger_D_b2_b2[NDiskStubs]; + + // counters for each possible leaf node in the merge tree // (up to eight for stub 0) - int count_L_0[NBarrelStubs], - count_L_1[NBarrelStubs], - count_L_2[NBarrelStubs], - count_L_3[NBarrelStubs], - count_L_4[NBarrelStubs], - count_L_5[NBarrelStubs], - count_L_6[NBarrelStubs], - count_L_7[NBarrelStubs]; + int count_barrel[NBarrelStubs][maxFMLayer]; initialize_barrel_mergers : for (short i = 0; NBarrelStubs > 0 && i < NBarrelStubs; i++) { #pragma HLS unroll merger_L_top[i].reset(); merger_L_b1[i].reset(); merger_L_b2[i].reset(); - count_L_0[i] = count_L_1[i] = count_L_2[i] = count_L_3[i] = count_L_4[i] = count_L_5[i] = count_L_6[i] = count_L_7[i] = 0; + merger_L_b1_b1[i].reset(); + merger_L_b1_b2[i].reset(); + merger_L_b2_b1[i].reset(); + merger_L_b2_b2[i].reset(); + for(unsigned int j=0; j > merger_D_top[NDiskStubs], // root node - merger_D_b1[NDiskStubs], merger_D_b2[NDiskStubs]; // first level - + // counters for each possible leaf node in the merge tree - int count_D_0[NDiskStubs], - count_D_1[NDiskStubs], - count_D_2[NDiskStubs], - count_D_3[NDiskStubs]; + int count_disk[NDiskStubs][maxFMLayer]; initialize_disk_mergers : for (short i = 0; NDiskStubs > 0 && i < NDiskStubs; i++) { #pragma HLS unroll merger_D_top[i].reset(); merger_D_b1[i].reset(); merger_D_b2[i].reset(); - count_D_0[i] = count_D_1[i] = count_D_2[i] = count_D_3[i] = 0; + merger_D_b1_b1[i].reset(); + merger_D_b1_b2[i].reset(); + merger_D_b2_b1[i].reset(); + merger_D_b2_b2[i].reset(); + for(unsigned int j=0; j> kNBits_MemAddr) : TrackletIDType(0); const ITCType &iTC = TCID.range(kNBitsITC - 1, 0); - const auto mparNPages = getMPARNPages(iTC); - const auto mparMem = getMPARMem(iTC); - const auto mparPage = getMPARPage(iTC); + typename TrackFit::TFSEEDTYPE iseed = TCID >> kNBitsITC; //TCID.range(3+kNBitsITC-1,kNBitsITC); + + //These are actually not needed any more... + auto mparNPages = getMPARNPages(iTC); + auto mparMem = getMPARMem(iTC); + auto mparPage = getMPARPage(iTC); + //This block is for AAAA + //This should be automatically generate by the generate_TB.py script... + if (iseed==0) { + if (iTC==0) {mparNPages=3; mparMem=0; mparPage=0;} + if (iTC==1) {mparNPages=3; mparMem=0; mparPage=1;} + if (iTC==2) {mparNPages=3; mparMem=0; mparPage=2;} + if (iTC==3) {mparNPages=2; mparMem=0; mparPage=0;} + if (iTC==4) {mparNPages=2; mparMem=0; mparPage=1;} + if (iTC==5) {mparNPages=1; mparMem=0; mparPage=0;} + if (iTC==6) {mparNPages=1; mparMem=1; mparPage=0;} + if (iTC==7) {mparNPages=2; mparMem=1; mparPage=0;} + if (iTC==8) {mparNPages=2; mparMem=1; mparPage=1;} + if (iTC==9) {mparNPages=3; mparMem=1; mparPage=0;} + if (iTC==10) {mparNPages=3; mparMem=1; mparPage=1;} + if (iTC==11) {mparNPages=3; mparMem=1; mparPage=2;} + } + if (iseed==1) { + if (iTC==0) {mparNPages=4; mparMem=0; mparPage=0;} + if (iTC==1) {mparNPages=4; mparMem=0; mparPage=1;} + if (iTC==2) {mparNPages=4; mparMem=0; mparPage=2;} + if (iTC==3) {mparNPages=4; mparMem=0; mparPage=3;} + } + if (iseed==3) { + if (iTC==0) {mparNPages=4; mparMem=1; mparPage=0;} + if (iTC==1) {mparNPages=4; mparMem=1; mparPage=1;} + if (iTC==2) {mparNPages=4; mparMem=1; mparPage=2;} + if (iTC==3) {mparNPages=4; mparMem=1; mparPage=3;} + } + if (iseed==7) { + if (iTC==0) {mparNPages=4; mparMem=2; mparPage=0;} + if (iTC==1) {mparNPages=4; mparMem=2; mparPage=1;} + if (iTC==2) {mparNPages=4; mparMem=2; mparPage=2;} + if (iTC==3) {mparNPages=4; mparMem=2; mparPage=3;} + } + //This block is for BBBB + if (iseed==2) { + if (iTC==0) {mparNPages=2; mparMem=0; mparPage=0;} + if (iTC==1) {mparNPages=2; mparMem=0; mparPage=1;} + if (iTC==2) {mparNPages=2; mparMem=1; mparPage=0;} + if (iTC==3) {mparNPages=2; mparMem=1; mparPage=1;} + } + if (iseed==4) { + if (iTC==0) {mparNPages=4; mparMem=0; mparPage=0;} + if (iTC==1) {mparNPages=4; mparMem=0; mparPage=1;} + if (iTC==2) {mparNPages=4; mparMem=0; mparPage=2;} + if (iTC==3) {mparNPages=4; mparMem=0; mparPage=3;} + } + if (iseed==5) { + if (iTC==0) {mparNPages=4; mparMem=1; mparPage=0;} + if (iTC==1) {mparNPages=4; mparMem=1; mparPage=1;} + if (iTC==2) {mparNPages=4; mparMem=1; mparPage=2;} + if (iTC==3) {mparNPages=4; mparMem=1; mparPage=3;} + } + if (iseed==6) { + if (iTC==0) {mparNPages=4; mparMem=2; mparPage=0;} + if (iTC==1) {mparNPages=4; mparMem=2; mparPage=1;} + if (iTC==2) {mparNPages=4; mparMem=2; mparPage=2;} + if (iTC==3) {mparNPages=4; mparMem=2; mparPage=3;} + } + const IndexType &trackletIndex = (min_id != kInvalidTrackletID) ? (min_id & TrackletIDType(0x7F)) : TrackletIDType(0); - const typename TrackFit::TFPHIREGION phiRegionOuter = iTC / (Seed == TF::L1L2 ? 3 : (Seed == TF::L1D1 ? 2 : 1)); - - TrackFit track(typename TrackFit::TFSEEDTYPE(TCID >> kNBitsITC)); + const typename TrackFit::TFPHIREGION phiRegionOuter = iTC / (iseed == TF::L1L2 ? 3 : (iseed == TF::L1D1 ? 2 : 1)); + + TrackFit track(iseed); track.setPhiRegionOuter(phiRegionOuter); if ((TPARMask & 0x1) && mparNPages == 1) { const auto &tpar = trackletParameters1[mparMem].read_mem(bx, trackletIndex); - setTrackPars(track, tpar); + setTrackPars(track, tpar); } else if ((TPARMask & 0x2) && mparNPages == 2) { const auto &tpar = trackletParameters2[mparMem].read_mem(bx, trackletIndex, mparPage); - setTrackPars(track, tpar); + setTrackPars(track, tpar); } else if ((TPARMask & 0x4) && mparNPages == 3) { const auto &tpar = trackletParameters3[mparMem].read_mem(bx, trackletIndex, mparPage); - setTrackPars(track, tpar); + setTrackPars(track, tpar); } else if ((TPARMask & 0x8) && mparNPages == 4) { const auto &tpar = trackletParameters4[mparMem].read_mem(bx, trackletIndex, mparPage); - setTrackPars(track, tpar); + setTrackPars(track, tpar); } // Retrieve the full information for each full match that has the minimum @@ -267,7 +398,7 @@ void TrackBuilder( //This is a hack to match the emulation where for D1D2 seeds //We don't use both L2 and D3 matches bool barrelD1D2Match1 = false; - + barrel_stub_association : for (short j = 0; j < NBarrelStubs; j++) { const auto &barrel_stub = merger_L_top[j].peek(); @@ -318,7 +449,8 @@ void TrackBuilder( break; } } - disk_stub_association : for (short j = 0; j < NDiskStubs; j++) { + + disk_stub_association : for (short j = 0; j < NDiskStubs; j++) { const auto &disk_stub = merger_D_top[j].peek(); bool disk_stub_valid = merger_D_top[j].valid() && smallest[j+NBarrelStubs]; @@ -356,7 +488,7 @@ void TrackBuilder( track.template setDiskStub(disk_stub_valid, disk_stub_index, disk_stub_r, disk_phi_res, disk_z_res); track.template setTrackIndex(nTracks); break; - case 5: + case 5: //should never get here? track.template setDiskStub(disk_stub_valid, disk_stub_index, disk_stub_r, disk_phi_res, disk_z_res); track.template setTrackIndex(nTracks); break; @@ -374,10 +506,10 @@ void TrackBuilder( // Only tracks with at least two matches are valid. track.setTrackValid(!done && (nMatches >= kMinNMatches)); - // Output the track word and eight stub words associated with the TrackFit + // Output the track word and eleven stub words associated with the TrackFit // object that was constructed. trackWord[nTracks] = track.getTrackWord(); - barrel_stub_words: for (short j = 0 ; NBarrelStubs > 0 && j < NBarrelStubs; j++) { // Note: need to have NBarrelStubs > 0 to prevent compilation error due to -Werror=type-limits flag in CMSSW + barrel_stub_words: for (short j = 0 ; j < trklet::N_LAYER; j++) { // Note: need to have NBarrelStubs > 0 to prevent compilation error due to -Werror=type-limits flag in CMSSW switch (j) { case 0: barrelStubWords[j][nTracks] = track.template getBarrelStubWord<0>(); @@ -391,9 +523,16 @@ void TrackBuilder( case 3: barrelStubWords[j][nTracks] = track.template getBarrelStubWord<3>(); break; + case 4: + barrelStubWords[j][nTracks] = track.template getBarrelStubWord<4>(); + break; + case 5: + barrelStubWords[j][nTracks] = track.template getBarrelStubWord<5>(); + break; } } - disk_stub_words: for (short j = 0 ; NDiskStubs > 0 && j < NDiskStubs; j++) { // Note: need to have NDiskStubs > 0 to prevent compilation error due to -Werror=type-limits flag in CMSSW + + disk_stub_words: for (short j = 0 ; j < trklet::N_DISK; j++) { // Note: need to have NDiskStubs > 0 to prevent compilation error due to -Werror=type-limits flag in CMSSW switch (j) { case 0: diskStubWords[j][nTracks] = track.template getDiskStubWord(); @@ -407,12 +546,16 @@ void TrackBuilder( case 3: diskStubWords[j][nTracks] = track.template getDiskStubWord(); break; + case 4: + diskStubWords[j][nTracks] = track.template getDiskStubWord(); + break; } } nTracks += (track.getTrackValid() ? 1 : 0); // Do the next set of pairwise comparisons in the merge trees. barrel_merger : for (unsigned short j = 0; j < NBarrelStubs; j++) { +#pragma HLS unroll bool read_1, read_2; @@ -420,96 +563,74 @@ void TrackBuilder( merger_L_b2[j].peek(), merger_L_b2[j].valid(), read_2, smallest[j]); - // We use the second layer of the merge tree only when there are eight FM - // memories per layer, which should only occur for the first layer. - if (NFMPerStubBarrel0 == 8 && j == 0) { - - bool read_b1_1, read_b1_2, read_b2_1, read_b2_2, - read_b1_b1_1, read_b1_b1_2, read_b1_b2_1, read_b1_b2_2, - read_b2_b1_1, read_b2_b1_2, read_b2_b2_1, read_b2_b2_2; - - merger_L_b1[0].next(merger_L_b1_b1.peek(), merger_L_b1_b1.valid(), read_b1_1, - merger_L_b1_b2.peek(), merger_L_b1_b2.valid(), read_b1_2, - read_1); - - merger_L_b1_b1.next(barrelFullMatches[0].read_mem(bx,count_L_0[j]), - count_L_0[j] < barrelFullMatches[0].getEntries(bx), - read_b1_b1_1, - barrelFullMatches[1].read_mem(bx,count_L_1[j]), - count_L_1[j] < barrelFullMatches[1].getEntries(bx), - read_b1_b1_2, - read_b1_1); - - if (read_b1_b1_1) count_L_0[j]++; - if (read_b1_b1_2) count_L_1[j]++; - - merger_L_b1_b2.next(barrelFullMatches[2].read_mem(bx,count_L_2[j]), - count_L_2[j] < barrelFullMatches[2].getEntries(bx), - read_b1_b2_1, - barrelFullMatches[3].read_mem(bx,count_L_3[j]), - count_L_3[j] < barrelFullMatches[3].getEntries(bx), - read_b1_b2_2, - read_b1_2); - - if (read_b1_b2_1) count_L_2[j]++; - if (read_b1_b2_2) count_L_3[j]++; - - merger_L_b2[0].next(merger_L_b2_b1.peek(), merger_L_b2_b1.valid(), read_b2_1, - merger_L_b2_b2.peek(), merger_L_b2_b2.valid(), read_b2_2, - read_2); - - merger_L_b2_b1.next(barrelFullMatches[4].read_mem(bx,count_L_4[j]), - count_L_4[j] < barrelFullMatches[4].getEntries(bx), - read_b2_b1_1, - barrelFullMatches[5].read_mem(bx,count_L_5[j]), - count_L_5[j] < barrelFullMatches[5].getEntries(bx), - read_b2_b1_2, - read_b2_1); - - if (read_b2_b1_1) count_L_4[j]++; - if (read_b2_b1_2) count_L_5[j]++; - - merger_L_b2_b2.next(barrelFullMatches[6].read_mem(bx,count_L_6[j]), - count_L_6[j] < barrelFullMatches[6].getEntries(bx), - read_b2_b2_1, - barrelFullMatches[7].read_mem(bx,count_L_7[j]), - count_L_7[j] < barrelFullMatches[7].getEntries(bx), - read_b2_b2_2, - read_b2_2); - - if (read_b2_b2_1) count_L_6[j]++; - if (read_b2_b2_2) count_L_7[j]++; + bool read_b1_1, read_b1_2, read_b2_1, read_b2_2, + read_b1_b1_1, read_b1_b1_2, read_b1_b2_1, read_b1_b2_2, + read_b2_b1_1, read_b2_b1_2, read_b2_b2_1, read_b2_b2_2; + + merger_L_b1[j].next(merger_L_b1_b1[j].peek(), merger_L_b1_b1[j].valid(), read_b1_1, + merger_L_b1_b2[j].peek(), merger_L_b1_b2[j].valid(), read_b1_2, + read_1); + bool validmatch[maxFMLayer]={false}; + FullMatch fullmatch[maxFMLayer]; + for (unsigned int k=0; k < NFMBarrel[j]; k++) { +#pragma HLS unroll + validmatch[k] = count_barrel[j][k] < barrelFullMatches[k+FMBarrelStart[j]].getEntries(bx); + fullmatch[k] = barrelFullMatches[k+FMBarrelStart[j]].read_mem(bx,count_barrel[j][k]); } - else { - if (NFMPerStubBarrel0 != 8 || i > 0) { - bool read_b1_1, read_b1_2, read_b2_1, read_b2_2; - - merger_L_b1[j].next(barrelFullMatches[NFMPerStubBarrel0-NFMPerStubBarrel+j*NFMPerStubBarrel].read_mem(bx,count_L_0[j]), - count_L_0[j] < barrelFullMatches[NFMPerStubBarrel0-NFMPerStubBarrel+j*NFMPerStubBarrel].getEntries(bx), - read_b1_1, - barrelFullMatches[1+NFMPerStubBarrel0-NFMPerStubBarrel+j*NFMPerStubBarrel].read_mem(bx,count_L_1[j]), - count_L_1[j] < barrelFullMatches[1+NFMPerStubBarrel0-NFMPerStubBarrel+j*NFMPerStubBarrel].getEntries(bx), - read_b1_2, - read_1); - - if (read_b1_1) count_L_0[j]++; - if (read_b1_2) count_L_1[j]++; - - merger_L_b2[j].next(barrelFullMatches[2+NFMPerStubBarrel0-NFMPerStubBarrel+j*NFMPerStubBarrel].read_mem(bx,count_L_2[j]), - count_L_2[j] < barrelFullMatches[2+NFMPerStubBarrel0-NFMPerStubBarrel+j*NFMPerStubBarrel].getEntries(bx), - read_b2_1, - barrelFullMatches[3+NFMPerStubBarrel0-NFMPerStubBarrel+j*NFMPerStubBarrel].read_mem(bx,count_L_3[j]), - count_L_3[j] < barrelFullMatches[3+NFMPerStubBarrel0-NFMPerStubBarrel+j*NFMPerStubBarrel].getEntries(bx), - read_b2_2, - read_2); - - if (read_b2_1) count_L_2[j]++; - if (read_b2_2) count_L_3[j]++; - } - } + + merger_L_b1_b1[j].next(fullmatch[0], + validmatch[0], + read_b1_b1_1, + fullmatch[1], + validmatch[1], + read_b1_b1_2, + read_b1_1); + + if (read_b1_b1_1) count_barrel[j][0]++; + if (read_b1_b1_2) count_barrel[j][1]++; + + merger_L_b1_b2[j].next(fullmatch[2], + validmatch[2], + read_b1_b2_1, + fullmatch[3], + validmatch[3], + read_b1_b2_2, + read_b1_2); + + if (read_b1_b2_1) count_barrel[j][2]++; + if (read_b1_b2_2) count_barrel[j][3]++; + + merger_L_b2[j].next(merger_L_b2_b1[j].peek(), merger_L_b2_b1[j].valid(), read_b2_1, + merger_L_b2_b2[j].peek(), merger_L_b2_b2[j].valid(), read_b2_2, + read_2); + + merger_L_b2_b1[j].next(fullmatch[4], + validmatch[4], + read_b2_b1_1, + fullmatch[5], + validmatch[5], + read_b2_b1_2, + read_b2_1); + + if (read_b2_b1_1) count_barrel[j][4]++; + if (read_b2_b1_2) count_barrel[j][5]++; + + merger_L_b2_b2[j].next(fullmatch[6], + validmatch[6], + read_b2_b2_1, + fullmatch[7], + validmatch[7], + read_b2_b2_2, + read_b2_2); + + if (read_b2_b2_1) count_barrel[j][6]++; + if (read_b2_b2_2) count_barrel[j][7]++; + } - disk_merger : for (unsigned int j = 0 ; j < NDiskStubs; j++) { + + disk_merger : for (unsigned int j = 0 ; j < NDiskStubs; j++) { +#pragma HLS unroll bool read_1, read_2; @@ -517,32 +638,72 @@ void TrackBuilder( merger_D_b2[j].peek(), merger_D_b2[j].valid(), read_2, smallest[j+NBarrelStubs]); - if (NFMPerStubBarrel0 != 8 || i > 0) { - bool read_b1_1, read_b1_2, read_b2_1, read_b2_2; - - merger_D_b1[j].next(diskFullMatches[0+j*NFMPerStubDisk].read_mem(bx,count_D_0[j]), - count_D_0[j] < diskFullMatches[0+j*NFMPerStubDisk].getEntries(bx), - read_b1_1, - diskFullMatches[1+j*NFMPerStubDisk].read_mem(bx,count_D_1[j]), - count_D_1[j] < diskFullMatches[1+j*NFMPerStubDisk].getEntries(bx), - read_b1_2, - read_1); - - if (read_b1_1) count_D_0[j]++; - if (read_b1_2) count_D_1[j]++; - - merger_D_b2[j].next(diskFullMatches[2+j*NFMPerStubDisk].read_mem(bx,count_D_2[j]), - count_D_2[j] < diskFullMatches[2+j*NFMPerStubDisk].getEntries(bx), - read_b2_1, - diskFullMatches[3+j*NFMPerStubDisk].read_mem(bx,count_D_3[j]), - count_D_3[j] < diskFullMatches[3+j*NFMPerStubDisk].getEntries(bx), - read_b2_2, - read_2); - - if (read_b2_1) count_D_2[j]++; - if (read_b2_2) count_D_3[j]++; + bool read_b1_1, read_b1_2, read_b2_1, read_b2_2, + read_b1_b1_1, read_b1_b1_2, read_b1_b2_1, read_b1_b2_2, + read_b2_b1_1, read_b2_b1_2, read_b2_b2_1, read_b2_b2_2; + + merger_D_b1[j].next(merger_D_b1_b1[j].peek(), merger_D_b1_b1[j].valid(), read_b1_1, + merger_D_b1_b2[j].peek(), merger_D_b1_b2[j].valid(), read_b1_2, + read_1); + + bool validmatch[maxFMLayer]={false}; + FullMatch fullmatch[maxFMLayer]; + for (unsigned int k=0; k return (kTFStubValidLSB(i) + TrackFitBase::kTFValidSize - 1); } static constexpr unsigned kTFHitCountSizeLSB(const int i) { - return (kTFStubValidMSB(0) + (7 - i) * TrackFitBase::kTFHitCountSize + 1); + return (kTFStubValidMSB(0) + (NBarrelStubs + NDiskStubs -1 - i) * TrackFitBase::kTFHitCountSize + 1); } static constexpr unsigned kTFHitCountSizeMSB(const int i) { return (kTFHitCountSizeLSB(i) + TrackFitBase::kTFHitCountSize - 1); diff --git a/TrackletAlgorithm/TrackHandler.cc b/TrackletAlgorithm/TrackHandler.cc index 7b850d36e8a..82fefd03b73 100644 --- a/TrackletAlgorithm/TrackHandler.cc +++ b/TrackletAlgorithm/TrackHandler.cc @@ -3,7 +3,7 @@ void TrackStruct::resetTracks(){ _trackWord = 0; LOOP_BarrelStubReset: - for (unsigned int nBarrelLayer = 0; nBarrelLayer < NBarrelStub; nBarrelLayer++){ + for (unsigned int nBarrelLayer = 0; nBarrelLayer < trklet::N_LAYER; nBarrelLayer++){ #pragma HLS unroll for (unsigned int nBarrelStubs = 0; nBarrelStubs < maxNumStubs; nBarrelStubs++){ #pragma HLS loop_flatten @@ -11,7 +11,7 @@ void TrackStruct::resetTracks(){ } } LOOP_DiskStubReset: - for (unsigned int nDiskLayer = 0; nDiskLayer < NDiskStub; nDiskLayer++){ + for (unsigned int nDiskLayer = 0; nDiskLayer < trklet::N_DISK; nDiskLayer++){ #pragma HLS unroll for (unsigned int nDiskStubs = 0; nDiskStubs < maxNumStubs; nDiskStubs++){ #pragma HLS loop_flatten @@ -31,7 +31,7 @@ bool TrackHandler::compareTrack(const TrackStruct &trk, TrackStruct &masterTrk, #pragma HLS array_partition variable=masterTrk._diskStubArray complete dim=0 #pragma HLS array_partition variable=trk._diskStubArray complete dim=0 LOOP_CompareBarrelStubs: - for (unsigned int barrelStubNum = 0; barrelStubNum < NBarrelStub; barrelStubNum++){ + for (unsigned int barrelStubNum = 0; barrelStubNum < trklet::N_LAYER; barrelStubNum++){ #pragma HLS unroll ap_uint masterBarrelStubIndex = ap_uint(masterTrk._barrelStubArray[barrelStubNum][0].range(kBarrelStubIndexSizeMSB, kBarrelStubIndexSizeLSB)); ap_uint inputBarrelStubIndex = ap_uint(trk._barrelStubArray[barrelStubNum][0].range(kBarrelStubIndexSizeMSB, kBarrelStubIndexSizeLSB)); @@ -39,7 +39,7 @@ bool TrackHandler::compareTrack(const TrackStruct &trk, TrackStruct &masterTrk, matchesFoundBarrel[barrelStubNum][0] = ((masterBarrelStubIndex == inputBarrelStubIndex) && (masterBarrelStubIndex > 0)) ? 1 : 0; } LOOP_CompareDiskStubs: - for (unsigned int diskStubNum = 0; diskStubNum < NDiskStub; diskStubNum++){ + for (unsigned int diskStubNum = 0; diskStubNum < trklet::N_DISK; diskStubNum++){ #pragma HLS unroll ap_uint masterDiskStubIndex = ap_uint(masterTrk._diskStubArray[diskStubNum][0].range(kDiskStubIndexSizeMSB, kDiskStubIndexSizeLSB)); ap_uint inputDiskStubIndex = ap_uint(trk._diskStubArray[diskStubNum][0].range(kDiskStubIndexSizeMSB, kDiskStubIndexSizeLSB)); @@ -68,7 +68,7 @@ void TrackHandler::mergeTrack(const TrackStruct &trk, TrackStruct &masterTrk){ // Check whether the stub word is non-zero in the compared track // Then add stub into master track if share > 3 stubs in common LOOP_SetInputBarrelStubToMaster: - for(unsigned int barrelStubNum = 0; barrelStubNum < NBarrelStub; barrelStubNum++){ + for(unsigned int barrelStubNum = 0; barrelStubNum < trklet::N_LAYER; barrelStubNum++){ #pragma HLS unroll if((masterTrk._barrelStubArray[barrelStubNum][0] == 0) && (trk._barrelStubArray[barrelStubNum][0] != 0)){ masterTrk._barrelStubArray[barrelStubNum][0] = trk._barrelStubArray[barrelStubNum][0]; @@ -76,7 +76,7 @@ void TrackHandler::mergeTrack(const TrackStruct &trk, TrackStruct &masterTrk){ } } LOOP_SetInputDiskStubToMaster: - for (unsigned int diskStubNum = 0; diskStubNum < NDiskStub; diskStubNum++){ + for (unsigned int diskStubNum = 0; diskStubNum < trklet::N_DISK; diskStubNum++){ #pragma HLS unroll if((masterTrk._diskStubArray[diskStubNum][0] == 0) && (trk._diskStubArray[diskStubNum][0] !=0 )){ masterTrk._diskStubArray[diskStubNum][0] = trk._diskStubArray[diskStubNum][0]; @@ -87,7 +87,7 @@ void TrackHandler::mergeTrack(const TrackStruct &trk, TrackStruct &masterTrk){ totalHitMap = mergedBarrelStubsMap + mergedDiskStubsMap; masterTrk._trackWord | totalHitMap; LOOP_BarrelStubs: - for (unsigned int barrelStubNum = 0; barrelStubNum < NBarrelStub; barrelStubNum++){ + for (unsigned int barrelStubNum = 0; barrelStubNum < trklet::N_LAYER; barrelStubNum++){ #pragma HLS unroll LOOP_MergeBarrelStubs: for (unsigned int barrelStubIndex = 1; barrelStubIndex < maxNumStubs; barrelStubIndex++){ @@ -103,7 +103,7 @@ void TrackHandler::mergeTrack(const TrackStruct &trk, TrackStruct &masterTrk){ } } LOOP_DiskStubs: - for (unsigned int diskStubNum = 0; diskStubNum < NDiskStub; diskStubNum++){ + for (unsigned int diskStubNum = 0; diskStubNum < trklet::N_DISK; diskStubNum++){ #pragma HLS unroll LOOP_MergeDiskStubs: for (unsigned int diskStubIndex = 1; diskStubIndex < maxNumStubs; diskStubIndex++){ @@ -120,4 +120,4 @@ void TrackHandler::mergeTrack(const TrackStruct &trk, TrackStruct &masterTrk){ } } return; -} \ No newline at end of file +} diff --git a/TrackletAlgorithm/TrackHandler.h b/TrackletAlgorithm/TrackHandler.h index 67bb15f79f7..39b7b865ba3 100644 --- a/TrackletAlgorithm/TrackHandler.h +++ b/TrackletAlgorithm/TrackHandler.h @@ -2,26 +2,25 @@ #define TrackletAlgorithm_TrackHandler_h #include "TrackFitMemory.h" #include "hls_stream.h" -const int NBarrelStub = 4; -const int NDiskStub = 4; -typedef TrackFit TrackFitType; -const unsigned int kFullBarrelStubSize = TrackFitType::kBarrelStubSize * NBarrelStub; -const unsigned int kFullDiskStubSize = TrackFitType::kDiskStubSize * NDiskStub; + +typedef TrackFit TrackFitType; +const unsigned int kFullBarrelStubSize = TrackFitType::kBarrelStubSize * trklet::N_LAYER; +const unsigned int kFullDiskStubSize = TrackFitType::kDiskStubSize * trklet::N_DISK; const unsigned int kFullTrackWordSize = TrackFitType::kTrackWordSize; const unsigned int kBarrelStubIndexSizeMSB = TrackFitType::kTFBarrelStubRSize + TrackFitType::kTFPhiResidSize + TrackFitType::kTFZResidSize + TrackFitType::kTFStubIndexSize; const unsigned int kBarrelStubIndexSizeLSB = TrackFitType::kTFBarrelStubRSize + TrackFitType::kTFPhiResidSize + TrackFitType::kTFZResidSize; const unsigned int kDiskStubIndexSizeMSB = TrackFitType::kTFDiskStubRSize + TrackFitType::kTFPhiResidSize + TrackFitType::kTFRResidSize + TrackFitType::kTFStubIndexSize; const unsigned int kDiskStubIndexSizeLSB = TrackFitType::kTFDiskStubRSize + TrackFitType::kTFPhiResidSize + TrackFitType::kTFRResidSize; const unsigned int maxNumStubs = 1; // 4 stubs per layer -const unsigned int kBarrelStubMap = TrackFitType::kTFHitCountSize * NBarrelStub; -const unsigned int kDiskStubMap = TrackFitType::kTFHitCountSize * NBarrelStub; +const unsigned int kBarrelStubMap = TrackFitType::kTFHitCountSize * trklet::N_LAYER; +const unsigned int kDiskStubMap = TrackFitType::kTFHitCountSize * trklet::N_LAYER; const unsigned int kTotHitMap = kBarrelStubMap + kDiskStubMap; struct TrackStruct { TrackFitType::TrackWord _trackWord; - TrackFitType::BarrelStubWord _barrelStubArray[NBarrelStub][maxNumStubs]; - TrackFitType::DiskStubWord _diskStubArray[NDiskStub][maxNumStubs]; + TrackFitType::BarrelStubWord _barrelStubArray[trklet::N_LAYER][maxNumStubs]; + TrackFitType::DiskStubWord _diskStubArray[trklet::N_DISK][maxNumStubs]; TrackFitType::TrackWord getTrkWord() const {return _trackWord;}; @@ -54,8 +53,8 @@ class TrackHandler { private: - ap_uint<1> matchesFoundBarrel[NBarrelStub][maxNumStubs]; - ap_uint<1> matchesFoundDisk[NDiskStub][maxNumStubs]; + ap_uint<1> matchesFoundBarrel[trklet::N_LAYER][maxNumStubs]; + ap_uint<1> matchesFoundDisk[trklet::N_DISK][maxNumStubs]; ap_uint<1> stubPadding = 0; unsigned int debug = 0; ap_uint mergedBarrelStubsMap; @@ -65,4 +64,4 @@ class TrackHandler { -#endif \ No newline at end of file +#endif diff --git a/TrackletAlgorithm/TrackMerger.cc b/TrackletAlgorithm/TrackMerger.cc index b4c50dcb520..9cd22a95d54 100644 --- a/TrackletAlgorithm/TrackMerger.cc +++ b/TrackletAlgorithm/TrackMerger.cc @@ -42,8 +42,8 @@ void fillTrackArray(const TrackStruct& inTrack, TrackStruct* outTrack, unsigned void loadTrack( const TrackFitType::TrackWord& trackWordIn, - const TrackFitType::BarrelStubWord (&barrelStubWordsIn)[NBarrelStub], - const TrackFitType::DiskStubWord (&diskStubWordsIn)[NDiskStub], + const TrackFitType::BarrelStubWord (&barrelStubWordsIn)[trklet::N_LAYER], + const TrackFitType::DiskStubWord (&diskStubWordsIn)[trklet::N_DISK], TrackStruct& aTrack ) { @@ -51,12 +51,12 @@ void loadTrack( #pragma HLS array_partition variable=diskStubWordsIn aTrack._trackWord = trackWordIn; - for (unsigned int i = 0; i < NBarrelStub; i++){ + for (unsigned int i = 0; i < trklet::N_LAYER; i++){ #pragma HLS unroll aTrack._barrelStubArray[i][0] = barrelStubWordsIn[i]; } - for (unsigned int j = 0; j < NDiskStub; j++){ + for (unsigned int j = 0; j < trklet::N_DISK; j++){ #pragma HLS unroll aTrack._diskStubArray[j][0] = diskStubWordsIn[j]; } @@ -68,20 +68,20 @@ void loadTrack( void unloadTrack( TrackStruct& aTrack, TrackFitType::TrackWord& trackWordOut, - TrackFitType::BarrelStubWord (&barrelStubWordsOut)[NBarrelStub], - TrackFitType::DiskStubWord (&diskStubWordsOut)[NDiskStub] + TrackFitType::BarrelStubWord (&barrelStubWordsOut)[trklet::N_LAYER], + TrackFitType::DiskStubWord (&diskStubWordsOut)[trklet::N_DISK] ) { #pragma HLS array_partition variable=barrelStubWordsOut #pragma HLS array_partition variable=diskStubWordsOut trackWordOut = aTrack.getTrkWord(); - for (unsigned int i = 0; i < NBarrelStub; i++){ + for (unsigned int i = 0; i < trklet::N_LAYER; i++){ #pragma HLS unroll barrelStubWordsOut[i] = aTrack.getBarrelStub(i, 0); } - for (unsigned int j = 0; j < NDiskStub; j++){ + for (unsigned int j = 0; j < trklet::N_DISK; j++){ #pragma HLS unroll diskStubWordsOut[j]= aTrack.getDiskStub(j, 0); } @@ -91,12 +91,12 @@ void unloadTrack( void TrackMerger(const BXType bx, const TrackFitType::TrackWord trackWord[kMaxTrack], - const TrackFitType::BarrelStubWord barrelStubWords[kMaxTrack][NBarrelStub], - const TrackFitType::DiskStubWord diskStubWords[kMaxTrack][NDiskStub], + const TrackFitType::BarrelStubWord barrelStubWords[kMaxTrack][trklet::N_LAYER], + const TrackFitType::DiskStubWord diskStubWords[kMaxTrack][trklet::N_DISK], BXType bx_o, TrackFitType::TrackWord (&trackWord_o)[kMaxTrack], - TrackFitType::BarrelStubWord (&barrelStubWords_o)[kMaxTrack][NBarrelStub], - TrackFitType::DiskStubWord (&diskStubWords_o)[kMaxTrack][NDiskStub] + TrackFitType::BarrelStubWord (&barrelStubWords_o)[kMaxTrack][trklet::N_LAYER], + TrackFitType::DiskStubWord (&diskStubWords_o)[kMaxTrack][trklet::N_DISK] ) { ComparisonModule comparisonModule[kNComparisonModules]; @@ -189,4 +189,4 @@ void TrackMerger(const BXType bx, bx_o = bx; return; -} \ No newline at end of file +} diff --git a/TrackletAlgorithm/TrackMerger.h b/TrackletAlgorithm/TrackMerger.h index 4149e5bf00c..1b33b7374c6 100644 --- a/TrackletAlgorithm/TrackMerger.h +++ b/TrackletAlgorithm/TrackMerger.h @@ -46,16 +46,16 @@ class ComparisonModule{ void loadTrack( const TrackFitType::TrackWord& trackWordIn, - const TrackFitType::BarrelStubWord (&barrelStubWordsIn)[NBarrelStub], - const TrackFitType::DiskStubWord (&diskStubWordsIn)[NDiskStub], + const TrackFitType::BarrelStubWord (&barrelStubWordsIn)[trklet::N_LAYER], + const TrackFitType::DiskStubWord (&diskStubWordsIn)[trklet::N_DISK], TrackStruct& aTrack ); void unloadTrack( TrackStruct& aTrack, TrackFitType::TrackWord& trackWordOut, - TrackFitType::BarrelStubWord (&barrelStubWordsOut)[NBarrelStub], - TrackFitType::DiskStubWord (&diskStubWordsOut)[NDiskStub] + TrackFitType::BarrelStubWord (&barrelStubWordsOut)[trklet::N_LAYER], + TrackFitType::DiskStubWord (&diskStubWordsOut)[trklet::N_DISK] ); @@ -63,13 +63,13 @@ class ComparisonModule{ void TrackMerger(const BXType bx, const TrackFitType::TrackWord trackWord[kMaxTrack], - const TrackFitType::BarrelStubWord barrelStubWords[kMaxTrack][NBarrelStub], - const TrackFitType::DiskStubWord diskStubWords[kMaxTrack][NDiskStub], + const TrackFitType::BarrelStubWord barrelStubWords[kMaxTrack][trklet::N_LAYER], + const TrackFitType::DiskStubWord diskStubWords[kMaxTrack][trklet::N_DISK], BXType bx_o, TrackFitType::TrackWord (&trackWord_o)[kMaxTrack], - TrackFitType::BarrelStubWord (&barrelStubWords_o)[kMaxTrack][NBarrelStub], - TrackFitType::DiskStubWord (&diskStubWords_o)[kMaxTrack][NDiskStub] + TrackFitType::BarrelStubWord (&barrelStubWords_o)[kMaxTrack][trklet::N_LAYER], + TrackFitType::DiskStubWord (&diskStubWords_o)[kMaxTrack][trklet::N_DISK] ); -#endif \ No newline at end of file +#endif diff --git a/TrackletAlgorithm/TrackletProcessor.h b/TrackletAlgorithm/TrackletProcessor.h index 1ee9317f3ff..25029e77df9 100644 --- a/TrackletAlgorithm/TrackletProcessor.h +++ b/TrackletAlgorithm/TrackletProcessor.h @@ -476,21 +476,21 @@ TP::addProj(const TrackletProjection &proj, const BXType bx, Tracklet phi >>= 3; if (NProjOut > 0 && TPROJMask & (0x1 << 0) && success && proj_success && phi == 0) - projout[0].write_mem(bx, proj, 0); + projout[0].write_mem(proj,0); if (NProjOut > 1 && TPROJMask & (0x1 << 1) && success && proj_success && phi == 1) - projout[1].write_mem(bx, proj, 0); + projout[1].write_mem(proj,0); if (NProjOut > 2 && TPROJMask & (0x1 << 2) && success && proj_success && phi == 2) - projout[2].write_mem(bx, proj, 0); + projout[2].write_mem(proj,0); if (NProjOut > 3 && TPROJMask & (0x1 << 3) && success && proj_success && phi == 3) - projout[3].write_mem(bx, proj, 0); + projout[3].write_mem(proj,0); if (NProjOut > 4 && TPROJMask & (0x1 << 4) && success && proj_success && phi == 4) - projout[4].write_mem(bx, proj, 0); + projout[4].write_mem(proj,0); if (NProjOut > 5 && TPROJMask & (0x1 << 5) && success && proj_success && phi == 5) - projout[5].write_mem(bx, proj, 0); + projout[5].write_mem(proj,0); if (NProjOut > 6 && TPROJMask & (0x1 << 6) && success && proj_success && phi == 6) - projout[6].write_mem(bx, proj, 0); + projout[6].write_mem(proj,0); if (NProjOut > 7 && TPROJMask & (0x1 << 7) && success && proj_success && phi == 7) - projout[7].write_mem(bx, proj, 0); + projout[7].write_mem(proj,0); return (success && proj_success); } @@ -552,7 +552,7 @@ TP::processStubPair( // Write the tracklet parameters and projections to the output memories. const TrackletParameters tpar(phiRegion, stubIndex1, stubIndex2, rinv, phi0, z0, t); if (success) { - trackletParameters->write_mem(bx, tpar, 0); + trackletParameters->write_mem(tpar,0); } bool addL3 = false, addL4 = false, addL5 = false, addL6 = false; @@ -762,16 +762,6 @@ TF::seed Seed, // seed layer combination (TP::L1L2, TP::L3L4, etc.) static const ap_uint<(1<<(2*TrackletEngineUnit()>::kNBitsBuffer))> TENearFullUINT=nearFullTEUnitInit(); - constexpr int NRZBINS = (1<()>::kNBitsRZBin); - - typename TrackletEngineUnit()>::MEMMASK vmstubsmask[NRZBINS]; -#pragma HLS array_partition variable=vmstubsmask complete dim=1 - entriesloop:for(unsigned int i=0;igetBinMask8(bx,i+1),outerVMStubs->getBinMask8(bx,i)); -} - vmstubsmask[NRZBINS-1]=(ap_uint<8>(0),outerVMStubs->getBinMask8(bx,NRZBINS-1)); - constexpr int NTEUBits=3; //ceil(log2(kNTEUnits[Seed])); ap_uint iTEfirstidle = 0; @@ -1054,8 +1044,11 @@ teunits[k].idle_; bool valid=!lutval___.and_reduce(); //Get the mask of bins that has non-zero number of hits - typename TrackletEngineUnit()>::MEMMASK stubmask16 = vmstubsmask[start]; - + ap_uint<1 + kNbitsrzbin> tmp((bx&1)*(1< tmpplusone((bx&1)*(1<()>::MEMMASK stubmask16 = + (outerVMStubs->getBinMaskB(tmpplusone), outerVMStubs->getBinMaskA(tmp)); + //Calculate the stub mask for which bins have hits _and_ are consistent with the inner stub typename TrackletEngineUnit()>::MEMMASK mask = ( (useregion___*usenext,useregion___) ); typename TrackletEngineUnit()>::MEMMASK stubmask = stubmask16&mask; diff --git a/TrackletAlgorithm/VMRouterCM.h b/TrackletAlgorithm/VMRouterCM.h index d89b8012d18..9f5df861d7f 100644 --- a/TrackletAlgorithm/VMRouterCM.h +++ b/TrackletAlgorithm/VMRouterCM.h @@ -219,27 +219,6 @@ void VMRouterCM(const BXType bx, BXType& bx_o, //Create variables that keep track of which memory address to read and write to ap_uint read_addr(0); // Reading of input stubs - ap_uint addrCountASI[nAllInnerVariants]; // Writing of Inner Allstubs - ap_uint<5> addrCountME[1 << (rzSizeME + phiRegSize)]; // Writing of ME stubs, number of bits taken from whatever is defined in the memories: (4+rzSize + phiRegSize)-(rzSize + phiRegSize)+1 - ap_uint<5> addrCountTE[1 << (rzSizeTE + phiRegSize)]; // Writing of TE stubs -#pragma HLS array_partition variable=addrCountASI complete dim=0 -#pragma HLS array_partition variable=addrCountME complete dim=0 -#pragma HLS array_partition variable=addrCountTE complete dim=0 - - if (nAllInnerVariants) { - for (int i = 0; i < nAllInnerVariants; i++) { -#pragma HLS unroll - addrCountASI[i] = 0; - } - } - for (int i = 0; i < 1 << (rzSizeME + phiRegSize); i++) { -#pragma HLS unroll - addrCountME[i] = 0; - } - for (int i = 0; i < 1 << (rzSizeTE + phiRegSize); i++) { -#pragma HLS unroll - addrCountTE[i] = 0; - } ///////////////////////////////////// // Main Loop @@ -294,7 +273,7 @@ void VMRouterCM(const BXType bx, BXType& bx_o, if (nAllCopies > 0) { for (int n = 0; n < nAllCopies; n++) { #pragma HLS UNROLL - memoriesAS[n].write_mem(bx, allstub, i); + memoriesAS[n].write_mem(allstub); } } @@ -370,8 +349,7 @@ void VMRouterCM(const BXType bx, BXType& bx_o, } if (passPhiCut && passSpecialCut) { - memoriesASInner[inner_mem_index].write_mem(bx, allstubinner, addrCountASI[inner_mem_index]); - addrCountASI[inner_mem_index]++; + memoriesASInner[inner_mem_index].write_mem(allstubinner); } inner_mem_index++; @@ -396,8 +374,7 @@ void VMRouterCM(const BXType bx, BXType& bx_o, createVMStub, InType, OutType, Layer, Disk, true>(stub, i, negDisk, METable, phiCorrTable, slotME); // Write the ME stub - memoryME->write_mem(bx, slotME, stubME, addrCountME[slotME]); - addrCountME[slotME] += 1; + memoryME->write_mem(slotME, stubME); #if !defined(__SYNTHESIS__) && defined(VMRCM_DEBUG) edm::LogVerbatim("L1trackHLS") << "ME stub " << std::hex << stubME.raw() << std::dec << " to slot " << slotME; @@ -419,9 +396,8 @@ void VMRouterCM(const BXType bx, BXType& bx_o, // Write stub to all TE memory copies for (int n = 0; n < nTEOCopies; n++) { #pragma HLS UNROLL - memoriesTEO[n].write_mem(bx, slotTE, stubTEO, addrCountTE[slotTE]); + memoriesTEO[n].write_mem(slotTE, stubTEO); } - addrCountTE[slotTE] += 1; #if !defined(__SYNTHESIS__) && defined(VMRCM_DEBUG) edm::LogVerbatim("L1trackHLS") << "TEOuter stub " << std::hex << stubTEO.raw() << std::dec << " to slot " << slotTE; diff --git a/TrackletAlgorithm/VMSMERouter.h b/TrackletAlgorithm/VMSMERouter.h index 55d3be2f379..4ad95f6218f 100644 --- a/TrackletAlgorithm/VMSMERouter.h +++ b/TrackletAlgorithm/VMSMERouter.h @@ -150,21 +150,24 @@ inline T createVMStubME(const AllStub& allStub, // Main function // Two input region types InType and DISK2S due to the disks having both 2S and PS inputs. -template +template void VMSMERouter(const BXType bx, BXType& bx_o, // LUTs const int METable[], const int phiCorrTable[], // Input memories AllStub& allStub, - VMStubMemory *memoryME, - AllStubMemory& memoriesAS, + VMStubMemory memoryME[], + AllStubMemory memoriesAS[], // Array to count how many VMStubs written in each slot unsigned int index, bool valid ) { #pragma HLS inline +#pragma HLS array_partition variable=memoryME complete dim=1 +#pragma HLS array_partition variable=memoriesAS complete dim=1 +#pragma HLS latency min=13 max=13 bool disk2S = false; // Used to determine if DISK2S @@ -185,8 +188,10 @@ void VMSMERouter(const BXType bx, BXType& bx_o, // It seems that the if (nAllCopies > 0) should not be needed, // but if nAllCopies is zero it generates an error in vivado_hls if (valid) { - ap_uint<7> ap_index(index); - memoriesAS.write_mem(bx, stub_copy, ap_index); + for (unsigned int i=0; i 0); @@ -210,7 +215,10 @@ void VMSMERouter(const BXType bx, BXType& bx_o, createVMStubME, InType, Layer, Disk>(allStub, index, negDisk, METable, phiCorrTable, slotME); // Write the ME stub - memoryME->write_mem(bx, slotME, stubME, 0); + for (unsigned int i=0; i fpga2_reducedcm_wires.dat +echo "MPAR_L5L6ABCDin input=> output=> PC_L5L6ABCD.tparin" >> fpga2_reducedcm_wires.dat +sed -i 's/VMR_[L|D][1-9]PHI[A|B|C|D|E|F|G|H].allstubout//g' fpga2_reducedcm_wires.dat +sed -i 's/n1 input/in input/g' fpga2_reducedcm_wires.dat +grep -v VMR_ fpga2_reducedcm_wires.dat > tmp.dat +mv tmp.dat fpga2_reducedcm_wires.dat +cp ../LUTsCMReduced/memorymodules.dat fpga2_reducedcm_memorymodules.dat +sed -i 's/n1 \[42\]/in \[42\]/g' fpga2_reducedcm_memorymodules.dat +echo "TrackletParameters: MPAR_L5L6ABCDin [73]" >> fpga2_reducedcm_memorymodules.dat + +grep -v TP_ ../LUTsCMReduced/processingmodules.dat | grep -v VMR_ | grep -v IR_ > fpga2_reducedcm_processingmodules.dat +sed -i 's/VMStubMERouter/VMSMERouter/g' fpga2_reducedcm_processingmodules.dat +sed -i 's/VMStubMERouter/VMSMERouter/g' fpga1_reducedcm_processingmodules.dat + + cp ../LUTsSplit/wires.dat fpga1_wires.dat cp ../LUTsSplit/processingmodules.dat fpga1_processingmodules.dat cp ../LUTsSplit/memorymodules.dat fpga1_memorymodules.dat @@ -205,40 +169,21 @@ grep -v TP_ ../LUTsSplit/processingmodules.dat | grep -v VMR_ | grep -v IR_ > fp sed -i 's/VMStubMERouter/VMSMERouter/g' fpga2_processingmodules.dat sed -i 's/VMStubMERouter/VMSMERouter/g' fpga1_processingmodules.dat -./makeReducedConfig.py --no-graph -t "TP" -s "C" -o "reducedcm_" -cp -fv ../LUTsCM2/wires.dat ../LUTsCM2/memorymodules.dat ../LUTsCM2/processingmodules.dat ./ -mv wires.dat reducedcm2_wires.dat -mv memorymodules.dat reducedcm2_memorymodules.dat -mv processingmodules.dat reducedcm2_processingmodules.dat -### Reduced Combined IRtoTB -echo "Reduced CM" -./generator_hdl.py ../../ --no_graph --mut IR -u 0 -d 4 -w reducedcm_wires.dat -p reducedcm_processingmodules.dat -m reducedcm_memorymodules.dat -de 1 -./generator_hdl.py ../../ --no_graph --mut IR -u 0 -d 4 -w reducedcm_wires.dat -p reducedcm_processingmodules.dat -m reducedcm_memorymodules.dat -de 1 -x -mkdir -p ../../IntegrationTests/ReducedCombinedConfig/{hdl,tb} -mv -fv memUtil_pkg.vhd SectorProcessor.vhd SectorProcessorFull.vhd ../../IntegrationTests/ReducedCombinedConfig/hdl/ -mv -fv tb_tf_top.vhd ../../IntegrationTests/ReducedCombinedConfig/tb/ -### Reduced Combined 2 IRtoTB -echo "Reduced CM2" -./generator_hdl.py ../../ --no_graph --mut IR -u 0 -d 4 -w reducedcm2_wires.dat -p reducedcm2_processingmodules.dat -m reducedcm2_memorymodules.dat -./generator_hdl.py ../../ --no_graph --mut IR -u 0 -d 4 -w reducedcm2_wires.dat -p reducedcm2_processingmodules.dat -m reducedcm2_memorymodules.dat -x -mkdir -p ../../IntegrationTests/ReducedCombinedConfig2/{hdl,tb} -mv -fv memUtil_pkg.vhd SectorProcessor.vhd SectorProcessorFull.vhd ../../IntegrationTests/ReducedCombinedConfig2/hdl/ -mv -fv tb_tf_top.vhd ../../IntegrationTests/ReducedCombinedConfig2/tb/ -### Reduced Combined 2 IRtoTB -echo "CM Barrel" -./generator_hdl.py ../../ --no_graph --mut IR -u 0 -d 4 -w cmbarrel_wires.dat -p cmbarrel_processingmodules.dat -m cmbarrel_memorymodules.dat -de 1 -./generator_hdl.py ../../ --no_graph --mut IR -u 0 -d 4 -w cmbarrel_wires.dat -p cmbarrel_processingmodules.dat -m cmbarrel_memorymodules.dat -de 1 -x -mkdir -p ../../IntegrationTests/CombinedBarrelConfig/{hdl,tb} -mv -fv memUtil_pkg.vhd SectorProcessor.vhd SectorProcessorFull.vhd ../../IntegrationTests/CombinedBarrelConfig/hdl/ -mv -fv tb_tf_top.vhd ../../IntegrationTests/CombinedBarrelConfig/tb/ -### Combined IRtoTP -echo "CombinedIRtoTP" + +echo "CM FPGA1" ./generator_hdl.py ../../ --no_graph --mut IR -u 0 -d 2 -w fpga1_wires.dat -p fpga1_processingmodules.dat -m fpga1_memorymodules.dat -de 1 -sp 1 ./generator_hdl.py ../../ --no_graph --mut IR -u 0 -d 2 -w fpga1_wires.dat -p fpga1_processingmodules.dat -m fpga1_memorymodules.dat -de 1 -x -sp 1 mkdir -p ../../IntegrationTests/CombinedConfig_FPGA1/{hdl,tb} mv -fv memUtil_pkg.vhd SectorProcessor.vhd SectorProcessorFull.vhd ../../IntegrationTests/CombinedConfig_FPGA1/hdl/ mv -fv tb_tf_top.vhd ../../IntegrationTests/CombinedConfig_FPGA1/tb/ -### Combined PC/VMSMER to TB + +echo "Reduced CM FPGA2" +./generator_hdl.py ../../ --no_graph --sp 2 --mut PC -u 0 -d 2 -w fpga2_reducedcm_wires.dat -p fpga2_reducedcm_processingmodules.dat -m fpga2_reducedcm_memorymodules.dat -de 1 +./generator_hdl.py ../../ --no_graph --sp 2 --mut PC -u 0 -d 2 -w fpga2_reducedcm_wires.dat -p fpga2_reducedcm_processingmodules.dat -m fpga2_reducedcm_memorymodules.dat -de 1 -x +mkdir -p ../../IntegrationTests/ReducedCombinedConfig_FPGA2/{hdl,tb} +mv -fv memUtil_pkg.vhd SectorProcessor.vhd SectorProcessorFull.vhd ../../IntegrationTests/ReducedCombinedConfig_FPGA2/hdl/ +mv -fv tb_tf_top.vhd ../../IntegrationTests/ReducedCombinedConfig_FPGA2/tb/ + echo "CM FPGA2" ./generator_hdl.py ../../ --no_graph --sp 2 --mut PC -u 0 -d 2 -w fpga2_wires.dat -p fpga2_processingmodules.dat -m fpga2_memorymodules.dat -de 1 ./generator_hdl.py ../../ --no_graph --sp 2 --mut PC -u 0 -d 2 -w fpga2_wires.dat -p fpga2_processingmodules.dat -m fpga2_memorymodules.dat -de 1 -x @@ -252,33 +197,20 @@ cd ../ if [[ $tables_only == 0 ]] then - echo "Getting MemPrints tar balls" - # Get memory test data: download and unpack the tarball. - wget --no-check-certificate -O MemPrints.tgz --quiet ${memprints_url_split} - tar -xzmf MemPrints.tgz - mv MemPrints MemPrintsSplit - rm -f MemPrints.tgz - - wget --no-check-certificate -O MemPrints.tgz --quiet ${memprints_url_reducedcm} - tar -xzmf MemPrints.tgz - mv MemPrints MemPrintsReducedCM - rm -f MemPrints.tgz - - wget --no-check-certificate -O MemPrints.tgz --quiet ${memprints_url_cm2} - tar -xzmf MemPrints.tgz - mv MemPrints MemPrintsReducedCM2 - - wget --no-check-certificate -O MemPrints.tgz --quiet ${memprints_url_cmbarrel} - tar -xzmf MemPrints.tgz - mv MemPrints MemPrintsCMBarrel - rm -f MemPrints.tgz - - wget --no-check-certificate -O MemPrints.tgz --quiet ${memprints_url_cm} - tar -xzmf MemPrints.tgz - mv MemPrints MemPrintsCM - rm -f MemPrints.tgz - - echo "Done getting MemPrints tar balls" + # Get memory test data: download and unpack the tarball. + echo "Getting MemPrints tar balls Split" + wget --no-check-certificate -O MemPrints.tgz --quiet ${memprints_url_split} + tar -xzmf MemPrints.tgz + mv MemPrints MemPrintsSplit + rm -f MemPrints.tgz + + echo "Getting MemPrints tar balls Reduced CM" + wget --no-check-certificate -O MemPrints.tgz --quiet ${memprints_url_reducedcm} + tar -xzmf MemPrints.tgz + mv MemPrints MemPrintsReducedCM + rm -f MemPrints.tgz + + echo "Done getting MemPrints tar balls" fi @@ -286,7 +218,7 @@ fi # https://forums.xilinx.com/t5/Installation-and-Licensing/Vivado-2016-4-on-Ubuntu-16-04-LTS-quot-awk-symbol-lookup-error/td-p/747165 unset LD_LIBRARY_PATH -mod_types=(IR FT PD VMRCM VMSMER TP MP PC) +mod_types=(IR TB PD VMRCM VMSMER TP MP PC) for module_type in ${mod_types[@]} do @@ -304,7 +236,6 @@ do echo ${module} memprint_location="MemPrintsSplit" memprint_location_reducedcm="MemPrintsReducedCM" - memprint_location_reducedcm2="MemPrintsReducedCM2" table_location="LUTsSplit" if [[ ${module_type} == "VMRCM" ]] then @@ -319,13 +250,11 @@ do rm -rf ${target_dir} mkdir -p ${target_dir}/ReducedCombinedConfig - mkdir -p ${target_dir}/ReducedCombinedConfig2 for mem in `grep "${module}\." ${wires} | awk '{print $1}' | sort -u`; do find ${memprint_location} -type f -regex ".*_${mem}_04\.dat$" -exec ln -s ../../{} ${target_dir}/ \; find ${memprint_location_reducedcm} -type f -regex ".*_${mem}_04\.dat$" -exec ln -s ../../../{} ${target_dir}/ReducedCombinedConfig/ \; - find ${memprint_location_reducedcm2} -type f -regex ".*_${mem}_04\.dat$" -exec ln -s ../../../{} ${target_dir}/ReducedCombinedConfig2/ \; done fi diff --git a/emData/generate_IR.py b/emData/generate_IR.py index 27d7ad4dca7..1c506c6375d 100755 --- a/emData/generate_IR.py +++ b/emData/generate_IR.py @@ -6,128 +6,126 @@ import argparse # return number of memories filled by each IR -def getNmemsPerIR(wiresFiles='./LUTs/wires.dat'): - dtcNames=[] +def getNmemsPerIR(wiresfiles='./LUTs/wires.dat'): + dtc_names=[] lines=[] - for line in open(wiresFiles,'r'): - my_regex = 'output=> IR_' - if re.search(my_regex, line, re.IGNORECASE): - dtcNames.append(line.split()[0].split('DL_')[1]) - my_regex = 'input=> IR_' - if re.search(my_regex, line, re.IGNORECASE): - lines.append(line) - lines =list(set(lines)) - dtcNames = list(set(dtcNames)) - nMemories = [] - for dtcName in dtcNames: - irLines=[] + with open(wiresfiles,'r') as fin: + for line in fin: + my_regex = 'output=> IR_' + if re.search(my_regex, line, re.IGNORECASE): + dtc_names.append(line.split()[0].split('DL_')[1]) + my_regex = 'input=> IR_' + if re.search(my_regex, line, re.IGNORECASE): + lines.append(line) + lines = list(set(lines)) + dtc_names = list(set(dtc_names)) + nmemories = [] + for dtc_name in dtc_names: + irlines=[] for line in lines: - if re.search(dtcName, line, re.IGNORECASE) and ("neg" in dtcName) == ("neg" in line): - irLines.append(line) - nMemories.append(len(irLines)) - dtcNames, nMemories = (list(t) for t in zip(*sorted(zip(dtcNames, nMemories)))) - return zip(dtcNames, nMemories) + if re.search(dtc_name, line, re.IGNORECASE) and ("neg" in dtc_name) == ("neg" in line): + irlines.append(line) + nmemories.append(len(irlines)) + dtc_names, nmemories = (list(t) for t in zip(*sorted(zip(dtc_names, nmemories)))) + return zip(dtc_names, nmemories) # generate TopLevel declaration template def createDefinitionsTemplate(): - fileName='DefinitionsTemplate.dat' - with open(fileName,'w') as f: - f.write("\n" - "void InputRouterTop_IR_{LinkName}(\n" - " const BXType bx\n" - " , const ap_uint hLinkWord // input link LUT \n" - " , const ap_uint hPhBnWord // n phi bins LUT \n" - " , ap_uint hInputStubs[kMaxProc]//input stubs \n" - " , BXType & bx_o // output bx \n" - " , DTCStubMemory hOutputStubs[cNMemories_IR_{LinkName}])" - "\n{{\n" - " #pragma HLS clock domain = slow_clock\n" - " #pragma HLS stream variable = hInputStubs depth = 108\n" - " #pragma HLS interface register port = bx_o\n" - " InputRouter( bx\n" - " , hLinkWord\n" - " , hPhBnWord\n" - " , hInputStubs\n" - " , bx_o\n" - " , hOutputStubs);\n" - "}}\n" + file_name='DefinitionsTemplate.dat' + with open(file_name,'w') as fout: + fout.write("\n" + "void InputRouterTop_IR_{LinkName}(\n" + " const BXType bx\n" + " , const ap_uint hLinkWord // input link LUT \n" + " , const ap_uint hPhBnWord // n phi bins LUT \n" + " , ap_uint hInputStubs[kMaxProc]//input stubs \n" + " , BXType & bx_o // output bx \n" + " , DTCStubMemory hOutputStubs[cNMemories_IR_{LinkName}])" + "\n{{\n" + " #pragma HLS clock domain = slow_clock\n" + " #pragma HLS stream variable = hInputStubs depth = 108\n" + " #pragma HLS interface register port = bx_o\n" + " InputRouter( bx\n" + " , hLinkWord\n" + " , hPhBnWord\n" + " , hInputStubs\n" + " , bx_o\n" + " , hOutputStubs);\n" + "}}\n" ) - return fileName + return file_name # generate TopLevel declaration template def createDeclarationTemplate(): - fileName = 'DeclarationsTemplate.dat' - with open(fileName,'w') as f: - f.write("\n" - "void InputRouterTop_IR_{LinkName}(\n" - " const BXType bx\n" - " , const ap_uint hLinkWord // input link LUT \n" - " , const ap_uint hPhBnWord // n phi bins LUT \n" - " , ap_uint hInputStubs[kMaxProc]//input stubs \n" - " , BXType & bx_o // output bx \n" - " , DTCStubMemory hOutputStubs[cNMemories_IR_{LinkName}]" - ");\n") - return fileName + file_name = 'DeclarationsTemplate.dat' + with open(file_name,'w') as fout: + fout.write("\n" + "void InputRouterTop_IR_{LinkName}(\n" + " const BXType bx\n" + " , const ap_uint hLinkWord // input link LUT \n" + " , const ap_uint hPhBnWord // n phi bins LUT \n" + " , ap_uint hInputStubs[kMaxProc]//input stubs \n" + " , BXType & bx_o // output bx \n" + " , DTCStubMemory hOutputStubs[cNMemories_IR_{LinkName}]" + ");\n") + return file_name # generate TopLevel parameters template def createParametersTemplate(): - fileName = 'ParametersTemplate.dat' - with open(fileName,'w') as f: - f.write("\n" - "constexpr unsigned int cNMemories_IR_{LinkName} = {Noutputs};\n") - return fileName + file_name = 'ParametersTemplate.dat' + with open(file_name,'w') as fout: + fout.write("\n" + "constexpr unsigned int cNMemories_IR_{LinkName} = {Noutputs};\n") + return file_name # generate all TopLevel parameters InputRouter_parameters.h -def createParameters(wiresFiles='./LUTs/wires.dat', outputDirectory='../TopFunctions/'): - IRs = getNmemsPerIR(wiresFiles) - templateName = createParametersTemplate() - file = open(outputDirectory + '/InputRouter_parameters.h', 'w') - file.write('#ifndef TopFunctions_InputRouter_parameters_h\n') - file.write('#define TopFunctions_InputRouter_parameters_h\n') - for dtcName, nMemories in IRs: - d = {} - d['LinkName'] = "DTC_" + dtcName - d['Noutputs'] = str(nMemories) - with open(templateName, 'r') as ftemp: - templateString = ftemp.read() - file.write(templateString.format(**d)) - file.write('#endif\n') - file.close() - os.remove(templateName) +def createParameters(wiresfiles='./LUTs/wires.dat', output_directory='../TopFunctions/'): + irs = getNmemsPerIR(wiresfiles) + template_name = createParametersTemplate() + with open(output_directory + '/InputRouter_parameters.h', 'w') as file: + file.write('#ifndef TopFunctions_InputRouter_parameters_h\n') + file.write('#define TopFunctions_InputRouter_parameters_h\n') + for dtc_name, nmemories in irs: + dtcs = {} + dtcs['LinkName'] = "DTC_" + dtc_name + dtcs['Noutputs'] = str(nmemories) + with open(template_name, 'r') as ftemp: + template_string = ftemp.read() + file.write(template_string.format(**dtcs)) + file.write('#endif\n') + os.remove(template_name) # generate all TopLevel declarations InputRouterTop.cc -def createDeclarations(wiresFiles='./LUTs/wires.dat', outputDirectory='../TopFunctions/'): - IRs = getNmemsPerIR(wiresFiles) - templateName = createDeclarationTemplate() - file = open(outputDirectory + '/InputRouterTop.h', 'w') - file.write('#ifndef TopFunctions_InputRouterTop_h\n') - file.write('#define TopFunctions_InputRouterTop_h\n') - file.write('#include \"InputRouter.h\"\n') - file.write('#include \"InputRouter_parameters.h\"\n') - for dtcName, _ in IRs: - d = {} - d['LinkName'] = "DTC_" + dtcName - with open(templateName, 'r') as ftemp: - templateString = ftemp.read() - file.write(templateString.format(**d)) - file.write('#endif\n') - file.close() - os.remove(templateName) +def createDeclarations(wiresfiles='./LUTs/wires.dat', output_directory='../TopFunctions/'): + irs = getNmemsPerIR(wiresfiles) + template_name = createDeclarationTemplate() + with open(output_directory + '/InputRouterTop.h', 'w') as file: + file.write('#ifndef TopFunctions_InputRouterTop_h\n') + file.write('#define TopFunctions_InputRouterTop_h\n') + file.write('#include \"InputRouter.h\"\n') + file.write('#include \"InputRouter_parameters.h\"\n') + for dtc_name, _ in irs: + dtcs = {} + dtcs['LinkName'] = "DTC_" + dtc_name + with open(template_name, 'r') as ftemp: + template_string = ftemp.read() + file.write(template_string.format(**dtcs)) + file.write('#endif\n') + os.remove(template_name) # generate all TopLevel definitions InputRouterTop.h -def createDefinitions(wiresFiles='./LUTs/wires.dat', outputDirectory='../TopFunctions/'): - IRs = getNmemsPerIR(wiresFiles) - templateName = createDefinitionsTemplate() - file = open(outputDirectory + '/InputRouterTop.cc', 'w') - file.write('#include \"InputRouterTop.h\"\n') - for dtcName, _ in IRs: - d = {} - d['LinkName'] = "DTC_" + dtcName - with open(templateName, 'r') as ftemp: - templateString = ftemp.read() - file.write(templateString.format(**d)) - file.close() - os.remove(templateName) +def createDefinitions(wiresfiles='./LUTs/wires.dat', output_directory='../TopFunctions/'): + irs = getNmemsPerIR(wiresfiles) + template_name = createDefinitionsTemplate() + with open(output_directory + '/InputRouterTop.cc', 'w') as file: + file.write('#include \"InputRouterTop.h\"\n') + for dtc_name, _ in irs: + dtcs = {} + dtcs['LinkName'] = "DTC_" + dtc_name + with open(template_name, 'r') as ftemp: + template_string = ftemp.read() + file.write(template_string.format(**dtcs)) + os.remove(template_name) parser = argparse.ArgumentParser(description="This script generates InputRouterTop.h, InputRouterTop.cc, and\ InputRouter_parameters.h in the TopFunctions/ directory.", diff --git a/emData/generate_MP.py b/emData/generate_MP.py index 6f940f8ba4d..9084c3d140f 100755 --- a/emData/generate_MP.py +++ b/emData/generate_MP.py @@ -8,16 +8,25 @@ from __future__ import print_function import os import re -import sys import argparse -TF_index = ['L1L2', 'L2L3', 'L3L4', 'L5L6', 'D1D2', 'D3D4', 'L1D1', 'L2D1'] -TF_index = {k:v for v,k in enumerate(TF_index)} +TF_index = {} +TF_index['L1L2'] = 0 +TF_index['L2L3'] = 0 +TF_index['L3L4'] = 1 +TF_index['L5L6'] = 0 +TF_index['D1D2'] = 1 +TF_index['D3D4'] = 1 +TF_index['L1D1'] = 1 +TF_index['L2D1'] = 0 +TF_index['AAAA'] = 0 +TF_index['BBBB'] = 1 + maxTPMems = "constexpr int maxTPMemories[" maxFMMems = "constexpr int maxFMMemories[" -def ASRegion(region): +def asRegion(region): if region in ['L1', 'L2', 'L3']: return 'BARRELPS' elif region in ['L4', 'L5', 'L6']: @@ -27,7 +36,7 @@ def ASRegion(region): else: return 'DISK2S' -def APRegion(region): +def vmStubMERegion(region): if region in ['L1', 'L2', 'L3']: return 'BARRELPS' elif region in ['L4', 'L5', 'L6']: @@ -35,30 +44,34 @@ def APRegion(region): else: return 'DISK' +def getTProjAndVMRegions(module): -def VMStubMERegion(region): - if region in ['L1', 'L2', 'L3']: - return 'BARRELPS' - elif region in ['L4', 'L5', 'L6']: - return 'BARREL2S' - else: - return 'DISK' + tproj_region = "" + vmproj_region = "" + vmstub_region = "" -def getTProjAndVMRegions(module): - if any(psword in module for psword in ["L1","L2","L3"]): TProjRegion = "BARRELPS" - elif any(psword in module for psword in ["L4","L5","L6"]): TProjRegion = "BARREL2S" - else: TProjRegion = "DISK" + if any(psword in module for psword in ["L1","L2","L3"]): + tproj_region = "BARRELPS" + elif any(psword in module for psword in ["L4","L5","L6"]): + tproj_region = "BARREL2S" + else: + tproj_region = "DISK" - if any(psword in module for psword in ["L1","L2","L3","L4","L5","L6"]): VMProjRegion = "BARREL" - else: VMProjRegion = "DISK" + if any(psword in module for psword in ["L1","L2","L3","L4","L5","L6"]): + vmproj_region = "BARREL" + else: + vmproj_region = "DISK" - if any(psword in module for psword in ["L1","L2","L3"]): VMStubRegion = "BARRELPS" - elif any(psword in module for psword in ["L4","L5","L6"]): VMStubRegion = "BARREL2S" - else: VMStubRegion = "DISK" + if any(psword in module for psword in ["L1","L2","L3"]): + vmstub_region = "BARRELPS" + elif any(psword in module for psword in ["L4","L5","L6"]): + vmstub_region = "BARREL2S" + else: + vmstub_region = "DISK" - return TProjRegion, VMProjRegion, VMStubRegion + return tproj_region, vmproj_region, vmstub_region -def FMRegion(region): +def fmRegion(region): if region in ['L1', 'L2', 'L3', 'L4', 'L5', 'L6']: return 'BARREL' else: @@ -79,16 +92,19 @@ def FMRegion(region): FMMems = {} for line in wiresFile: line = line.rstrip() - mpName = re.sub(r".*MP_(......).*", r"MP_\1", line) + mpName = line.split()[-1].split(".")[0] + if not mpName.startswith("MP_"): + mpName = line.split()[-3].split(".")[0] memName = line.split()[0] projtype = "TPROJ_" - if arguments.split : projtype = "MPROJ_" + if arguments.split : + projtype = "MPROJ_" if memName.startswith(projtype): if mpName not in TPMems: TPMems[mpName] = [] TPMems[mpName].append(memName) if memName.startswith("FM_"): - FM = re.sub(r"FM_(....)_......", r"\1", memName) + FM = re.sub(r"FM_(....)_......*", r"\1", memName) if mpName not in FMMems: FMMems[mpName] = [] FMMems[mpName].append(FM) @@ -135,32 +151,32 @@ def FMRegion(region): # Calculate parameters and print out parameters and top function for each MP. for mpName in sorted(TPMems.keys(), key = lambda x: x.startswith('L')): - seed = re.sub(r"MP_(..)....", r"\1", mpName) + seed = mpName[3:5] iMP = re.sub(r"MP_.....(.)", r"\1", mpName) # numbers of memories nTPMem = len(TPMems[mpName]) nFMMem = len(FMMems[mpName]) - FMMask = 0 + fmMask = 0 for FM in FMMems[mpName]: - FMMask = FMMask | (1 << TF_index[FM]) + fmMask = fmMask | (1 << TF_index[FM]) - NPage = 0 - NPageSum = 0 + nPage = 0 + nPageSum = 0 index = 0 for TPROJ in TPMems[mpName]: - print(mpName, TPROJ) npage = len(TPROJ)-17 - NPageSum += npage - print("TPROJ npage", TPROJ, npage) - NPage = NPage | ((npage-1) << (2*index)) + if TPROJ.endswith("_E"): + npage = len(TPROJ)-19 + nPageSum += npage + nPage = nPage | ((npage-1) << (2*index)) index+=1 - + maxTPMems += seed + "PHI" + iMP + "maxTrackletProjections" maxFMMems += seed + "PHI" + iMP + "maxFullMatchCopies" if mpName != sorted(TPMems.keys(), key=lambda x: x.startswith('L'))[-1]: maxTPMems += ",\n " - maxFMMems += ",\n " + maxFMMems += ",\n " # Print out parameters for this MP. parametersFile.write( @@ -168,7 +184,7 @@ def FMRegion(region): "// magic numbers for " + mpName + "\n" "template<> constexpr uint32_t FMMask() {\n" " return 0x%X;\n" - "}\n" % FMMask + "}\n" % fmMask ) parametersFile.write( @@ -176,7 +192,7 @@ def FMRegion(region): "// magic numbers for " + mpName + "\n" "template<> constexpr uint64_t NPage() {\n" " return 0x%X;\n" - "}\n" % NPage + "}\n" % nPage ) parametersFile.write( @@ -184,7 +200,7 @@ def FMRegion(region): "// magic numbers for " + mpName + "\n" "template<> constexpr uint32_t NPageSum() {\n" " return 0x%X;\n" - "}\n" % NPageSum + "}\n" % nPageSum ) TProjRegion, VMProjRegion, VMStubRegion = getTProjAndVMRegions(seed) @@ -199,10 +215,10 @@ def FMRegion(region): "void MatchProcessor_" + seed + "PHI" + iMP + "(\n" " const BXType bx,\n" " const TrackletProjectionMemory<" + TProjRegion + "> projin[" + seed + "PHI" + iMP + "maxTrackletProjections],\n" - " const VMStubMemory<" + VMStubMERegion(seed) + ", " + nrz + ", kNbitsphibin, kNMatchEngines>& instubdata,\n" - " const AllStubMemory<" + ASRegion(seed) + ">* allstub,\n" + " const VMStubMemory<" + vmStubMERegion(seed) + ", " + nrz + ", kNbitsphibin, kNMatchEngines>& instubdata,\n" + " const AllStubMemory<" + asRegion(seed) + ">* allstub,\n" " BXType& bx_o,\n" - " FullMatchMemory<" + FMRegion(seed) + "> fullmatch[" + seed + "PHI" + iMP + "maxFullMatchCopies]\n" + " FullMatchMemory<" + fmRegion(seed) + "> fullmatch[" + seed + "PHI" + iMP + "maxFullMatchCopies]\n" ");\n" ) @@ -212,20 +228,20 @@ def FMRegion(region): "void MatchProcessor_" + seed + "PHI" + iMP + "(\n" " const BXType bx,\n" " const TrackletProjectionMemory<" + TProjRegion + "> projin[" + seed + "PHI" + iMP + "maxTrackletProjections],\n" - " const VMStubMemory<" + VMStubMERegion(seed) + ", " + nrz + ", kNbitsphibin, kNMatchEngines>& instubdata,\n" - " const AllStubMemory<" + ASRegion(seed) + ">* allstub,\n" + " const VMStubMemory<" + vmStubMERegion(seed) + ", " + nrz + ", kNbitsphibin, kNMatchEngines>& instubdata,\n" + " const AllStubMemory<" + asRegion(seed) + ">* allstub,\n" " BXType& bx_o,\n" - " FullMatchMemory<" + FMRegion(seed) + "> fullmatch[" + seed + "PHI" + iMP + "maxFullMatchCopies]\n" + " FullMatchMemory<" + fmRegion(seed) + "> fullmatch[" + seed + "PHI" + iMP + "maxFullMatchCopies]\n" ") {\n" "#pragma HLS inline off\n" "#pragma HLS interface register port=bx_o\n" ) - if nTPMem == 1: + if nTPMem == 0: topFile.write("#pragma HLS resource variable=projin.get_mem() latency=2\n") else: for i in range(nTPMem): topFile.write("#pragma HLS resource variable=projin[" + str(i) + "].get_mem() latency=2\n") - if nFMMem == 1: + if nFMMem == 0: topFile.write("#pragma HLS resource variable=fullmatch.get_mem() latency=2\n") else: for i in range(nFMMem): @@ -233,11 +249,9 @@ def FMRegion(region): topFile.write( "#pragma HLS resource variable=allstub->get_mem() latency=2\n" "#pragma HLS resource variable=instubdata.get_mem() latency=2\n" -# "#pragma HLS resource variable=instubdata.get_mem_entries8A() latency=1\n" -# "#pragma HLS resource variable=instubdata.get_mem_entries8B() latency=1\n" "\n" "MP_" + seed + "PHI" + iMP + ": MatchProcessor<" - "" + TProjRegion + ", " + VMStubRegion + ", " + nrz + ", " + VMProjRegion + ", " + ASRegion(seed) + ", " + FMRegion(seed) + ", " + seed + "PHI" + iMP + "maxTrackletProjections" + ", " + seed + "PHI" + iMP + "maxFullMatchCopies" + ",\n" + "" + TProjRegion + ", " + VMStubRegion + ", " + nrz + ", " + VMProjRegion + ", " + asRegion(seed) + ", " + fmRegion(seed) + ", " + seed + "PHI" + iMP + "maxTrackletProjections" + ", " + seed + "PHI" + iMP + "maxFullMatchCopies" + ",\n" " TF::" + seed + ", " "TF::" + iMP + "> (\n" " bx,\n" diff --git a/emData/generate_PC.py b/emData/generate_PC.py index 882f16eeead..86b8a1866b8 100755 --- a/emData/generate_PC.py +++ b/emData/generate_PC.py @@ -1,13 +1,13 @@ #!/usr/bin/env python3 -# This script generates +# This script generates # ProjectionCalculatorTop.h, and ProjectionCalculatorTop.cc in the -# TopFunctions/ directory. Currently supports all TPs +# TopFunctions/ directory. Currently supports all TPs # from __future__ import absolute_import, print_function -import sys, re, os, argparse -from enum import Enum +import os +import argparse # These enums must match those defined in # TopFunctions/TrackletProcessor.h. @@ -77,164 +77,131 @@ # First, parse the wires file and store the memory names associated with PCs in # dictionaries with the PC names as keys. with open(arguments.wiresFileName, "r") as wiresFile: - tprojMems = {} - for line in wiresFile: - proctype = "TP_" - if arguments.split : proctype = "PC_" - if proctype not in line : - continue - line = line.rstrip() - pcName = line.split(proctype)[1].split(".")[0] - innerLayer = pcName[3:5] - outerLayer = pcName[5:7] - memName = line.split()[0] - - projtype = "TPROJ_" - if arguments.split : projtype = "MPROJ_" - if memName.startswith(projtype): - if pcName not in tprojMems: - tprojMems[pcName] = [] - tprojMems[pcName].append(memName) + tprojMems = {} + for line in wiresFile: + proctype = "PC_" + if proctype not in line : + continue + line = line.rstrip() + pcName = line.split(proctype)[1].split(".")[0] + innerLayer = pcName[3:5] + outerLayer = pcName[5:7] + memName = line.split()[0] + + projtype = "MPROJ_" + if memName.startswith(projtype): + if pcName not in tprojMems: + tprojMems[pcName] = [] + tprojMems[pcName].append(memName) # Open and print out preambles for the parameters and top files. dirname = os.path.dirname(os.path.realpath('__file__')) -#with open(os.path.join(dirname, arguments.outputDirectory, "ProjectionCalculator_parameters.h"), "w") as parametersFile, \ + with open(os.path.join(dirname, arguments.outputDirectory, "ProjectionCalculatorTop.h"), "w") as topHeaderFile, \ open(os.path.join(dirname, arguments.outputDirectory, "ProjectionCalculatorTop.cc"), "w") as topFile: -# parametersFile.write( -# "#ifndef TopFunctions_ProjectionCalculator_parameters_h\n" -# "#define TopFunctions_ProjectionCalculator_parameters_h\n" -# "\n" -# "// This file contains numbers of memories and bit masks that are specific to\n" -# "// each ProjectionCalculator and that come directly from the wiring.\n" -# "//\n" -# "// The validity of each of the barrel TPROJ memories is determined by\n" -# "// TPROJMaskBarrel. The bits of this mask, from least significant to most\n" -# "// significant, represent the memories in the order they are passed to\n" -# "// ProjectionCalculator; e.g., the LSB corresponds to\n" -# "// projout_barrel_ps[TP::L1PHIA]. If a bit is set, the corresponding memory is\n" -# "// valid, if it is not, the corresponding memory is not valid. Likewise, the\n" -# "// validity of each of the disk TPROJ memories is determined by TPROJMaskDisk\n" -# "// in the same way.\n" -# "namespace PC{\n" -# " enum itc {UNDEF_ITC, A = 0, B = 1, C = 2, D = 3, E = 4, F = 5, G = 6, H = 7, I = 8, J = 9, K = 10, L = 11, M = 12, N = 13, O = 14};\n" -# " }\n" -# "template constexpr uint32_t PCPROJMaskBarrel();\n" -# "template constexpr uint32_t PCPROJMaskDisk();\n" -# ) - topHeaderFile.write( - "#ifndef TopFunctions_ProjectionCalculatorTop_h\n" - "#define TopFunctions_ProjectionCalculatorTop_h\n" - "\n" - "#include \"ProjectionCalculator.h\"\n" + + topHeaderFile.write( + "#ifndef TopFunctions_ProjectionCalculatorTop_h\n" + "#define TopFunctions_ProjectionCalculatorTop_h\n" + "\n" + "\n" + "#include \"ProjectionCalculator.h\"\n" ) - topFile.write( - "#include \"ProjectionCalculatorTop.h\"\n" - "\n" - "////////////////////////////////////////////////////////////////////////////////\n" - "// Top functions for various ProjectionCalculators (PC). For each iteration of\n" - "// the main processing loop, a TP retrieves a pair of stub indices from one of\n" - "// the stub-pair memories, and in turn, these indices are used to retrieve one\n" - "// stub each from an inner and an outer all-stub memory. This pair of stubs is\n" - "// used to calculate a rough set of helix parameters, which are written to the\n" - "// tracklet-parameter memory if the tracklet passes cuts on rinv and z0. Rough\n" - "// projections to additional layers and disks are also calculated and are\n" - "// written to the appropriate tracklet-projection memories.\n" - "////////////////////////////////////////////////////////////////////////////////\n" + + topFile.write( + "#include \"ProjectionCalculatorTop.h\"\n" + "\n" + "////////////////////////////////////////////////////////////////////////////////\n" + "// Top functions for various ProjectionCalculators (PC). For each track parameter\n" + "// the projections to additional layers and disks are also calculated and are\n" + "// written to the appropriate tracklet-projection memories.\n" + "////////////////////////////////////////////////////////////////////////////////\n" ) - # Calculate parameters and print out parameters and top function for each TP. - for pcName in sorted(tprojMems): - print(pcName,tprojMems[pcName]) - seed = pcName[0:4] - iTC = pcName[4:] - print("pcName:", pcName, seed, iTC) - # # numbers of memories - # nASMemInner = len(asInnerMems[pcName]) - # nASMemOuter = len(asOuterMems[pcName]) - # nVMSTEMem = len(vmsteMems[pcName]) - # # AS inner and outer masks - # asInnerMask = 0 - # asOuterMask = 0 - # asInnerMems[pcName].sort() - # asOuterMems[pcName].sort() - - # TPROJ masks for barrel and disks - tprojMaskBarrel = 0 - tprojMaskDisk = 0 - for projmem in tprojMems[pcName]: - projlayreg = projmem.split("_")[2] - if projlayreg in ProjoutIndexBarrel: - tprojMaskBarrel = tprojMaskBarrel | (1 << ProjoutIndexBarrel[projlayreg]) - if projlayreg in ProjoutIndexDisk: - tprojMaskDisk = tprojMaskDisk | (1 << ProjoutIndexDisk[projlayreg]) - - # Print out prototype for top function for this PC. + # Calculate parameters and print out parameters and top function for each TP. + for pcName in sorted(tprojMems): + seed = pcName[0:4] + iTC = pcName[4:] + # # numbers of memories + # nASMemInner = len(asInnerMems[pcName]) + # nASMemOuter = len(asOuterMems[pcName]) + # nVMSTEMem = len(vmsteMems[pcName]) + # # AS inner and outer masks + # asInnerMask = 0 + # asOuterMask = 0 + # asInnerMems[pcName].sort() + # asOuterMems[pcName].sort() + + # TPROJ masks for barrel and disks + tprojMaskBarrel = 0 + tprojMaskDisk = 0 + for projmem in tprojMems[pcName]: + projlayreg = projmem.split("_")[2] + if projlayreg in ProjoutIndexBarrel: + tprojMaskBarrel = tprojMaskBarrel | (1 << ProjoutIndexBarrel[projlayreg]) + if projlayreg in ProjoutIndexDisk: + tprojMaskDisk = tprojMaskDisk | (1 << ProjoutIndexDisk[projlayreg]) + + # Print out prototype for top function for this PC. + topHeaderFile.write( + "\n" + "void ProjectionCalculator_" + seed + iTC + "(\n" + " const BXType bx,\n" + " BXType& bx_o,\n" + " TrackletParameters tPar,\n" + " ap_uint<9> trackletIndex,\n" + " bool valid,\n" + " TrackletParameterMemory& tparout,\n" + " TrackletProjectionMemory projout_barrel_ps[],\n" + " TrackletProjectionMemory projout_barrel_2s[],\n" + " TrackletProjectionMemory projout_disk[]\n" + ");\n" + ) + + # Print top function definition for this PC. + topFile.write( + "\n" + "void ProjectionCalculator_" + seed + iTC + "(\n" + " const BXType bx,\n" + " BXType& bx_o,\n" + " TrackletParameters tPar,\n" + " ap_uint<9> trackletIndex,\n" + " bool valid,\n" + " TrackletParameterMemory& tparout,\n" + " TrackletProjectionMemory projout_barrel_ps[TP::N_PROJOUT_BARRELPS],\n" + " TrackletProjectionMemory projout_barrel_2s[TP::N_PROJOUT_BARREL2S],\n" + " TrackletProjectionMemory projout_disk[TP::N_PROJOUT_DISK]\n" + ") {\n" + "#pragma HLS latency min=13 max=13\n" + "#pragma HLS pipeline II=1\n" + "#pragma HLS inline recursive\n" + "#pragma HLS array_partition variable=projout_barrel_ps complete dim=1\n" + "#pragma HLS array_partition variable=projout_barrel_2s complete dim=1\n" + "#pragma HLS array_partition variable=projout_disk complete dim=1\n" + "\n" + "PC_" + seed + iTC + ": ProjectionCalculator<\n" + " TF::" + seed + ",\n" + " TP::" + iTC[0] + ",\n" + " 0x%x, \n 0x%x" %(tprojMaskBarrel, tprojMaskDisk) +\ + " >(\n" + " bx,\n" + " bx_o,\n" + " tPar,\n" + " trackletIndex,\n" + " valid,\n" + " tparout,\n" + " projout_barrel_ps,\n" + " projout_barrel_2s,\n" + " projout_disk\n" + " );\n" + "}\n\n" + ) + + # Print out endif topHeaderFile.write( "\n" - "void ProjectionCalculator_" + seed + iTC + "(\n" - " const BXType bx,\n" - " BXType& bx_o,\n" - " TrackletParameters tPar,\n" - " ap_uint<9> trackletIndex,\n" - " bool valid,\n" - " TrackletParameterMemory& tparout,\n" - " TrackletProjectionMemory projout_barrel_ps[],\n" - " TrackletProjectionMemory projout_barrel_2s[],\n" - " TrackletProjectionMemory projout_disk[]\n" - ");\n" - ) - - # Print out definition of top function for this TP. + "#endif\n" + ) topFile.write( "\n" - "void ProjectionCalculator_" + seed + iTC + "(\n" - " const BXType bx,\n" - " BXType& bx_o,\n" - " TrackletParameters tPar,\n" - " ap_uint<9> trackletIndex,\n" - " bool valid,\n" - " TrackletParameterMemory& tparout,\n" - " TrackletProjectionMemory projout_barrel_ps[TP::N_PROJOUT_BARRELPS],\n" - " TrackletProjectionMemory projout_barrel_2s[TP::N_PROJOUT_BARREL2S],\n" - " TrackletProjectionMemory projout_disk[TP::N_PROJOUT_DISK]\n" - ") {\n" - "#pragma HLS latency min=13 max=13\n" - "#pragma HLS pipeline II=1\n" - "#pragma HLS inline recursive\n" - "#pragma HLS array_partition variable=projout_barrel_ps complete dim=1\n" - "#pragma HLS array_partition variable=projout_barrel_2s complete dim=1\n" - "#pragma HLS array_partition variable=projout_disk complete dim=1\n" - "\n" - "PC_" + seed + iTC + ": ProjectionCalculator<\n" - " TF::" + seed + ",\n" - " TP::" + iTC[0] + ",\n" - " 0x%x, \n 0x%x" %(tprojMaskBarrel, tprojMaskDisk) +\ - " >(\n" - " bx,\n" - " bx_o,\n" - " tPar,\n" - " trackletIndex,\n" - " valid,\n" - " tparout,\n" - " projout_barrel_ps,\n" - " projout_barrel_2s,\n" - " projout_disk\n" - " );\n" - "}\n" - ) - - - # Print out endifs and close files. - # parametersFile.write( - # "\n" - # "#endif\n" - # ) - topHeaderFile.write( - "\n" - "#endif\n" - ) - topFile.write( - "\n" - "////////////////////////////////////////////////////////////////////////////////\n" - ) - + "////////////////////////////////////////////////////////////////////////////////\n" + ) diff --git a/emData/generate_TB.py b/emData/generate_TB.py index b6c68bbbf9d..e4cf14ae680 100755 --- a/emData/generate_TB.py +++ b/emData/generate_TB.py @@ -47,15 +47,14 @@ class ITC(Enum): parser = argparse.ArgumentParser(description="This script generates TrackBuilderTop.h and TrackBuilderTop.cc in the\ TopFunctions/ directory.", epilog="") -parser.add_argument("-o", "--outputDirectory", metavar="DIR", default="../TopFunctions/", type=str, help="The directory in which to write the output files (default=%(default)s)") -parser.add_argument("-w", "--wiresFileName", metavar="WIRES_FILE", default="LUTs/wires.dat", type=str, help="Name and directory of the configuration file for wiring (default = %(default)s)") -parser.add_argument("-sp", "--split", action='store_true', help="Split project so use MPROJ - not TPROJ memories") +parser.add_argument("-o", "--outputDirectory", metavar="DIR", default="../TopFunctions/", type=str, help="The directory in which to write the output files for the TB (default=%(default)s)") +parser.add_argument("-w", "--wiresFileName", metavar="WIRES_FILE", default="LUTs/wires.dat", type=str, help="Name and directory of the configuration file for wiring for the TB (default = %(default)s)") +parser.add_argument("-sp", "--split", action='store_true', help="Split project so use MPAR not TPAR") arguments = parser.parse_args() # Keep in sync with # kTProjITCSize in TrackletAlgorithm/TrackletProjectionMemory.h and # kFMITCSize in TrackletAlgorithm/FullMatchMemory.h -ITC_SIZE = 4 # First, parse the wires file and store the memory names associated with TBs in # dictionaries with the TB names as keys. @@ -64,14 +63,15 @@ class ITC(Enum): barrelFMMems = {} diskFMMems = {} for line in wiresFile: - if " FT_" not in line: + if " TB_" not in line: continue line = line.rstrip() - tbName = re.sub(r".*FT_(....).*", r"FT_\1", line) + tbName = re.sub(r".*TB_(....).*", r"TB_\1", line) seed = tbName.split("_")[1] memName = line.split()[0] partype = "TPAR" - if arguments.split : partype = "MPAR" + if arguments.split: + partype = "MPAR" if memName.startswith(partype): if tbName not in tparMems: tparMems[tbName] = [] @@ -129,7 +129,7 @@ class ITC(Enum): # Calculate parameters and print out top function for each TB. for tbName in sorted(tparMems.keys()): - seed = re.sub(r"FT_(....)", r"\1", tbName) + seed = re.sub(r"TB_(....)", r"\1", tbName) seedNumber = None if seed == "L1L2": seedNumber = 0 @@ -151,16 +151,37 @@ class ITC(Enum): # numbers of memories nTPARMem = [] for i in range(0, 4): - nTPARMem.append(len([tpar for tpar in tparMems[tbName] if len(tpar) == memNameLength[i]])) + nTPARMem.append(len([tpar for tpar in tparMems[tbName] if len(tpar) == memNameLength[i]])) nBarrelFMMem = len(barrelFMMems[tbName]) nDiskFMMem = len(diskFMMems[tbName]) # numbers of output stubs barrelFMs = sorted([fm[0:10] for fm in barrelFMMems[tbName]]) + diskFMs = sorted([fm[0:10] for fm in diskFMMems[tbName]]) nBarrelStubs = len(set(barrelFMs)) nDiskStubs = len({fm[0:10] for fm in diskFMMems[tbName]}) # numbers of memories per stub + layercount = {} + for fm in barrelFMs : + if fm not in layercount: + layercount[fm]=0 + layercount[fm]+=1 + nFMBarrel=0 + for layer, count in layercount.items(): + shift=int(layer[-1])-1 + nFMBarrel+=(count<<(4*shift)) + + diskcount = {} + for fm in diskFMs : + if fm not in diskcount: + diskcount[fm]=0 + diskcount[fm]+=1 + nFMDisk=0 + for disk, count in diskcount.items(): + shift=int(disk[-1])-1 + nFMDisk+=(count<<(4*shift)) + barrelFM0 = barrelFMs[0] if len(barrelFMs) > 0 else "" nBarrelFMMemPerStub0 = barrelFMs.count(barrelFM0) barrelFMs = [fm for fm in barrelFMs if fm != barrelFM0] @@ -170,8 +191,8 @@ class ITC(Enum): # mask for enabling/disabling arrays of TPAR memories tparMask = 0 for i in range(0, 4): - if nTPARMem[i] > 0: - tparMask = tparMask | (1 << i) + if nTPARMem[i] > 0: + tparMask = tparMask | (1 << i) # definition of getMPARNPages function nParentheses = 0 @@ -181,22 +202,22 @@ class ITC(Enum): getMPARNPages += "getMPARNPages(const ITCType &iTC) {\n" getMPARNPages += " return " for i in range(1, maxNPages): - if nTPARMem[i - 1] == 0: - continue - if not first: - getMPARNPages += "(\n " - nParentheses += 1 - mems = [tpar for tpar in tparMems[tbName] if len(tpar) == memNameLength[i - 1]] - pages = "".join([tpar[9:] for tpar in mems]) - pages = [ITC[page].value for page in pages] - getMPARNPages += "(iTC == " + str(pages[0]) - for page in pages[1:]: - getMPARNPages += " || iTC == " + str(page) - getMPARNPages += ") ? " + str(i) + " : " - first = False + if nTPARMem[i - 1] == 0: + continue + if not first: + getMPARNPages += "(\n " + nParentheses += 1 + mems = [tpar for tpar in tparMems[tbName] if len(tpar) == memNameLength[i - 1]] + pages = "".join([tpar[9:] for tpar in mems]) + pages = [ITC[page].value for page in pages] + getMPARNPages += "(iTC == " + str(pages[0]) + for page in pages[1:]: + getMPARNPages += " || iTC == " + str(page) + getMPARNPages += ") ? " + str(i) + " : " + first = False getMPARNPages += str(maxNPages) for i in range(0, nParentheses): - getMPARNPages += ")" + getMPARNPages += ")" getMPARNPages += ";\n}\n" # definition of getMPARMem function @@ -205,23 +226,23 @@ class ITC(Enum): getMPARMem += "getMPARMem(const ITCType &iTC) {\n" getMPARMem += " return " for i in range(0, max(nTPARMem) - 1): - if i != 0: - getMPARMem += "(\n " - nParentheses += 1 - mems = [] - for j in range(0, 4): - allMems = [tpar for tpar in tparMems[tbName] if len(tpar) == memNameLength[j]] - if len(allMems) > i: - mems.append(allMems[i]) - pages = "".join([tpar[9:] for tpar in mems]) - pages = [ITC[page].value for page in pages] - getMPARMem += "(iTC == " + str(pages[0]) - for page in pages[1:]: - getMPARMem += " || iTC == " + str(page) - getMPARMem += ") ? " + str(i) + " : " + if i != 0: + getMPARMem += "(\n " + nParentheses += 1 + mems = [] + for j in range(0, 4): + allMems = [tpar for tpar in tparMems[tbName] if len(tpar) == memNameLength[j]] + if len(allMems) > i: + mems.append(allMems[i]) + pages = "".join([tpar[9:] for tpar in mems]) + pages = [ITC[page].value for page in pages] + getMPARMem += "(iTC == " + str(pages[0]) + for page in pages[1:]: + getMPARMem += " || iTC == " + str(page) + getMPARMem += ") ? " + str(i) + " : " getMPARMem += str(max(nTPARMem) - 1) for i in range(0, nParentheses): - getMPARMem += ")" + getMPARMem += ")" getMPARMem += ";\n}\n" # definition of getMPARPage function @@ -230,18 +251,18 @@ class ITC(Enum): getMPARPage += "getMPARPage(const ITCType &iTC) {\n" getMPARPage += " return " for i in range(0, maxNPages - 1): - if i != 0: - getMPARPage += "(\n " - nParentheses += 1 - pages = "".join([tpar[9 + i] for tpar in tparMems[tbName] if len(tpar) > 9 + i]) - pages = [ITC[page].value for page in pages] - getMPARPage += "(iTC == " + str(pages[0]) - for page in pages[1:]: - getMPARPage += " || iTC == " + str(page) - getMPARPage += ") ? " + str(i) + " : " + if i != 0: + getMPARPage += "(\n " + nParentheses += 1 + pages = "".join([tpar[9 + i] for tpar in tparMems[tbName] if len(tpar) > 9 + i]) + pages = [ITC[page].value for page in pages] + getMPARPage += "(iTC == " + str(pages[0]) + for page in pages[1:]: + getMPARPage += " || iTC == " + str(page) + getMPARPage += ") ? " + str(i) + " : " getMPARPage += str(maxNPages - 1) for i in range(0, nParentheses): - getMPARPage += ")" + getMPARPage += ")" getMPARPage += ";\n}\n" # Print out prototype for top function for this TB. @@ -256,9 +277,9 @@ class ITC(Enum): " const FullMatchMemory barrelFullMatches[],\n" " const FullMatchMemory diskFullMatches[],\n" " BXType &bx_o,\n" - " TrackFit<" + str(nBarrelStubs) + ", " + str(nDiskStubs) + ">::TrackWord trackWord[],\n" - " TrackFit<" + str(nBarrelStubs) + ", " + str(nDiskStubs) + ">::BarrelStubWord barrelStubWords[][kMaxProc],\n" - " TrackFit<" + str(nBarrelStubs) + ", " + str(nDiskStubs) + ">::DiskStubWord diskStubWords[][kMaxProc],\n" + " TrackFit::TrackWord trackWord[],\n" + " TrackFit::BarrelStubWord barrelStubWords[][kMaxProc],\n" + " TrackFit::DiskStubWord diskStubWords[][kMaxProc],\n" " bool &done\n" ");\n" ) @@ -308,9 +329,9 @@ class ITC(Enum): " const FullMatchMemory barrelFullMatches[" + str(nBarrelFMMem) + "],\n" " const FullMatchMemory diskFullMatches[" + str(nDiskFMMem) + "],\n" " BXType &bx_o,\n" - " TrackFit<" + str(nBarrelStubs) + ", " + str(nDiskStubs) + ">::TrackWord trackWord[kMaxProc],\n" - " TrackFit<" + str(nBarrelStubs) + ", " + str(nDiskStubs) + ">::BarrelStubWord barrelStubWords[" + str(nBarrelStubs) + "][kMaxProc],\n" - " TrackFit<" + str(nBarrelStubs) + ", " + str(nDiskStubs) + ">::DiskStubWord diskStubWords[" + str(nDiskStubs) + "][kMaxProc],\n" + " TrackFit::TrackWord trackWord[kMaxProc],\n" + " TrackFit::BarrelStubWord barrelStubWords[trklet::N_LAYER][kMaxProc],\n" + " TrackFit::DiskStubWord diskStubWords[trklet::N_DISK][kMaxProc],\n" " bool &done\n" ") {\n" "#pragma HLS inline recursive\n" @@ -322,8 +343,8 @@ class ITC(Enum): "#pragma HLS array_partition variable=diskFullMatches complete dim=1\n" ) for i in range(0, 4): - for j in range(0, nTPARMem[i]): - topFile.write("#pragma HLS resource variable=trackletParameters" + str(i + 1) + "[" + str(j) + "].get_mem() latency=2\n") + for j in range(0, nTPARMem[i]): + topFile.write("#pragma HLS resource variable=trackletParameters" + str(i + 1) + "[" + str(j) + "].get_mem() latency=2\n") for i in range(0, nBarrelFMMem): topFile.write("#pragma HLS resource variable=barrelFullMatches[" + str(i) + "].get_mem() latency=2\n") for i in range(0, nDiskFMMem): @@ -337,7 +358,7 @@ class ITC(Enum): "#pragma HLS stream variable=diskStubWords depth=1 dim=2\n" "#pragma HLS interface register port=done\n" "\n" - "TB_" + seed + ": TrackBuilder(\n" + "TB_" + seed + ": TrackBuilder(\n" " bx,\n" " trackletParameters1,\n" " trackletParameters2,\n" @@ -363,4 +384,3 @@ class ITC(Enum): "\n" "\n#endif\n" ) - diff --git a/emData/generate_TP.py b/emData/generate_TP.py index 9f1e730e03e..58c2d634658 100755 --- a/emData/generate_TP.py +++ b/emData/generate_TP.py @@ -6,7 +6,9 @@ from __future__ import absolute_import, print_function -import sys, re, os, argparse +import re +import os +import argparse from enum import Enum # These enums must match those defined in @@ -82,291 +84,308 @@ class ProjoutIndexDisk(Enum): # First, parse the wires file and store the memory names associated with TPs in # dictionaries with the TP names as keys. with open(arguments.wiresFileName, "r") as wiresFile: - asInnerMems = {} - asOuterMems = {} - vmsteMems = {} - tprojMems = {} - for line in wiresFile: - # Only barrel-only seeds are supported right now. - if "TP_L1L2" not in line \ - and "TP_L2L3" not in line \ - and "TP_L3L4" not in line \ - and "TP_L5L6" not in line \ - and "TP_L2D1" not in line \ - and "TP_L1D1" not in line \ - and "TP_D1D2" not in line \ - and "TP_D3D4" not in line: - continue - line = line.rstrip() - tpName = re.sub(r".*TP_(.....).*", r"TP_\1", line) - innerLayer = tpName[3:5] - outerLayer = tpName[5:7] - memName = line.split()[0] - if memName.startswith("AS_"): - memLayer= memName[3:5] - if memLayer == innerLayer: - if tpName not in asInnerMems: - asInnerMems[tpName] = [] - asInnerMems[tpName].append(memName) - elif memLayer == outerLayer: - if tpName not in asOuterMems: - asOuterMems[tpName] = [] - asOuterMems[tpName].append(memName) - if memName.startswith("VMSTE_"): - if tpName not in vmsteMems: - vmsteMems[tpName] = [] - vmsteMems[tpName].append(memName) - if memName.startswith("TPROJ_"): - if tpName not in tprojMems: - tprojMems[tpName] = [] - tprojMems[tpName].append(memName) + asInnerMems = {} + asOuterMems = {} + vmsteMems = {} + tprojMems = {} + for line in wiresFile: + # Only barrel-only seeds are supported right now. + tps = ("TP_L1L2", "TP_L2L3", "TP_L3L4", "TP_L5L6", + "TP_L2D1", "TP_L1D1", "TP_D1D2", "TP_D3D4") + noTP = True + for tp in tps: + if tp in line: + noTP = False + if noTP: + continue + line = line.rstrip() + tpName = re.sub(r".*TP_(.....).*", r"TP_\1", line) + innerLayer = tpName[3:5] + outerLayer = tpName[5:7] + memName = line.split()[0] + if memName.startswith("AS_"): + memLayer= memName[3:5] + if memLayer == innerLayer: + if tpName not in asInnerMems: + asInnerMems[tpName] = [] + asInnerMems[tpName].append(memName) + elif memLayer == outerLayer: + if tpName not in asOuterMems: + asOuterMems[tpName] = [] + asOuterMems[tpName].append(memName) + if memName.startswith("VMSTE_"): + if tpName not in vmsteMems: + vmsteMems[tpName] = [] + vmsteMems[tpName].append(memName) + if memName.startswith("TPROJ_"): + if tpName not in tprojMems: + tprojMems[tpName] = [] + tprojMems[tpName].append(memName) # Open and print out preambles for the parameters and top files. dirname = os.path.dirname(os.path.realpath('__file__')) with open(os.path.join(dirname, arguments.outputDirectory, "TrackletProcessor_parameters.h"), "w") as parametersFile, \ open(os.path.join(dirname, arguments.outputDirectory, "TrackletProcessorTop.h"), "w") as topHeaderFile, \ open(os.path.join(dirname, arguments.outputDirectory, "TrackletProcessorTop.cc"), "w") as topFile: - parametersFile.write( - "#ifndef TopFunctions_TrackletProcessor_parameters_h\n" - "#define TopFunctions_TrackletProcessor_parameters_h\n" - "\n" - "#ifndef __SYNTHESIS__\n" - '#include "SWLUTReader.h"\n' - '#ifdef CMSSW_GIT_HASH\n' - '#include \n' - '#endif\n' - "#endif\n" - "// This file contains numbers of memories and bit masks that are specific to\n" - "// each TrackletProcessor and that come directly from the wiring.\n" - "//\n" - "// The validity of each of the barrel TPROJ memories is determined by\n" - "// TPROJMaskBarrel. The bits of this mask, from least significant to most\n" - "// significant, represent the memories in the order they are passed to\n" - "// TrackletProcessor; e.g., the LSB corresponds to\n" - "// projout_barrel_ps[TP::L1PHIA]. If a bit is set, the corresponding memory is\n" - "// valid, if it is not, the corresponding memory is not valid. Likewise, the\n" - "// validity of each of the disk TPROJ memories is determined by TPROJMaskDisk\n" - "// in the same way.\n" - "namespace TP{\n" - "template constexpr uint32_t TPROJMaskBarrel();\n" - "template constexpr uint32_t TPROJMaskDisk();\n" - "template const ap_uint<10>* getLUT();\n" - "template const ap_uint<1>* getPTInnerLUT();\n" - "template const ap_uint<1>* getPTOuterLUT();\n" - "template const ap_int<18>* getDRinvLUT();\n" - "template const ap_int<18>* getInvtLUT();\n" - "template const ap_int<19>* getDRinvForwardLUT();\n" - "template const ap_int<18>* getInvtForwardLUT();\n" - "template const ap_int<19>* getDRinvBackwardLUT();\n" - "template const ap_int<18>* getInvtBackwardLUT();\n" - "template constexpr int nASMemInner();\n" - ) - topHeaderFile.write( - "#ifndef TopFunctions_TrackletProcessorTop_h\n" - "#define TopFunctions_TrackletProcessorTop_h\n" - "\n" - "#include \"TrackletProcessor.h\"\n" - ) - topFile.write( - "#include \"TrackletProcessorTop.h\"\n" - "\n" - "////////////////////////////////////////////////////////////////////////////////\n" - "// Top functions for various TrackletProcessors (TP). For each iteration of\n" - "// the main processing loop, a TC retrieves a pair of stub indices from one of\n" - "// the stub-pair memories, and in turn, these indices are used to retrieve one\n" - "// stub each from an inner and an outer all-stub memory. This pair of stubs is\n" - "// used to calculate a rough set of helix parameters, which are written to the\n" - "// tracklet-parameter memory if the tracklet passes cuts on rinv and z0. Rough\n" - "// projections to additional layers and disks are also calculated and are\n" - "// written to the appropriate tracklet-projection memories.\n" - "////////////////////////////////////////////////////////////////////////////////\n" - ) - - # Calculate parameters and print out parameters and top function for each TP. - seedlist = [] #keeps track of seeds that have been looped over for functions that only exist once per seed type - for tpName in sorted(asInnerMems.keys()): - seed = re.sub(r"TP_(....).", r"\1", tpName) - iTC = re.sub(r"TP_....(.)", r"\1", tpName) - # numbers of memories - nASMemInner = len(asInnerMems[tpName]) - nASMemOuter = len(asOuterMems[tpName]) - nVMSTEMem = len(vmsteMems[tpName]) - # AS inner and outer masks - asInnerMask = 0 - asOuterMask = 0 - asInnerMems[tpName].sort() - asOuterMems[tpName].sort() + parametersFile.write( + "#ifndef TopFunctions_TrackletProcessor_parameters_h\n" + "#define TopFunctions_TrackletProcessor_parameters_h\n" + "\n" + "#ifndef __SYNTHESIS__\n" + '#include "SWLUTReader.h"\n' + '#ifdef CMSSW_GIT_HASH\n' + '#include \n' + '#endif\n' + "#endif\n" + "// This file contains numbers of memories and bit masks that are specific to\n" + "// each TrackletProcessor and that come directly from the wiring.\n" + "//\n" + "// The validity of each of the barrel TPROJ memories is determined by\n" + "// TPROJMaskBarrel. The bits of this mask, from least significant to most\n" + "// significant, represent the memories in the order they are passed to\n" + "// TrackletProcessor; e.g., the LSB corresponds to\n" + "// projout_barrel_ps[TP::L1PHIA]. If a bit is set, the corresponding memory is\n" + "// valid, if it is not, the corresponding memory is not valid. Likewise, the\n" + "// validity of each of the disk TPROJ memories is determined by TPROJMaskDisk\n" + "// in the same way.\n" + "namespace TP{\n" + "template constexpr uint32_t TPROJMaskBarrel();\n" + "template constexpr uint32_t TPROJMaskDisk();\n" + "template const ap_uint<10>* getLUT();\n" + "template const ap_uint<1>* getPTInnerLUT();\n" + "template const ap_uint<1>* getPTOuterLUT();\n" + "template const ap_int<18>* getDRinvLUT();\n" + "template const ap_int<18>* getInvtLUT();\n" + "template const ap_int<19>* getDRinvForwardLUT();\n" + "template const ap_int<18>* getInvtForwardLUT();\n" + "template const ap_int<19>* getDRinvBackwardLUT();\n" + "template const ap_int<18>* getInvtBackwardLUT();\n" + "template constexpr int nASMemInner();\n" + ) + topHeaderFile.write( + "#ifndef TopFunctions_TrackletProcessorTop_h\n" + "#define TopFunctions_TrackletProcessorTop_h\n" + "\n" + "#include \"TrackletProcessor.h\"\n" + ) + topFile.write( + "#include \"TrackletProcessorTop.h\"\n" + "\n" + "////////////////////////////////////////////////////////////////////////////////\n" + "// Top functions for various TrackletProcessors (TP). For each iteration of\n" + "// the main processing loop, a TC retrieves a pair of stub indices from one of\n" + "// the stub-pair memories, and in turn, these indices are used to retrieve one\n" + "// stub each from an inner and an outer all-stub memory. This pair of stubs is\n" + "// used to calculate a rough set of helix parameters, which are written to the\n" + "// tracklet-parameter memory if the tracklet passes cuts on rinv and z0. Rough\n" + "// projections to additional layers and disks are also calculated and are\n" + "// written to the appropriate tracklet-projection memories.\n" + "////////////////////////////////////////////////////////////////////////////////\n" + ) - # TPROJ masks for barrel and disks - tprojMaskBarrel = 0 - for projout in ProjoutIndexBarrel: - projoutName = "TPROJ_" + seed + iTC + "_" + projout.name - projoutIndex = projout.value - if projoutName in tprojMems[tpName]: - tprojMaskBarrel = tprojMaskBarrel | (1 << projoutIndex) - tprojMaskDisk = 0 - for projout in ProjoutIndexDisk: - projoutName = "TPROJ_" + seed + iTC + "_" + projout.name - projoutIndex = projout.value - if projoutName in tprojMems[tpName]: - tprojMaskDisk = tprojMaskDisk | (1 << projoutIndex) - # figure out sizes of LUTs by reading .tab files, do once per seed type - if seed not in seedlist: - LUTSize[seed] = str(sum(1 for _ in open(arguments.LUTsDir+"/TP_{0}.tab".format(seed))) - 2) - regLUTSize[seed] = str(sum(1 for _ in open(arguments.LUTsDir+"/TP_{0}{1}_usereg.tab".format(seed,iTC))) - 2) - innerPTLUTSize[seed] = str(sum(1 for _ in open(arguments.LUTsDir+"/TP_{0}{1}_stubptinnercut.tab".format(seed,iTC))) - 2) - outerPTLUTSize[seed] = str(sum(1 for _ in open(arguments.LUTsDir+"/TP_{0}{1}_stubptoutercut.tab".format(seed,iTC))) - 2) - # Print out parameters for this TP. - parametersFile.write( - ("\n" - "template<> constexpr uint32_t TPROJMaskBarrel() {\n" - " return 0x%X;\n" - "}\n" - "template<> constexpr uint32_t TPROJMaskDisk() {\n" - " return 0x%X;\n" - "}\n" - 'template<> inline const ap_uint<10>* getLUT(){\n' - '#ifndef __SYNTHESIS__\n' - '#ifdef CMSSW_GIT_HASH\n' - ' static std::mutex getLUTMutex_;\n' - ' std::lock_guard lock(getLUTMutex_);\n' - '#endif\n' - ' static ap_uint<10> lut[' + LUTSize[seed] + '];\n' - ' static bool init = 0;\n' - ' if (!init)\n' - ' init = readSWLUT,' + LUTSize[seed] +'>(lut,"'+arguments.LUTsDir+'/TP_' + seed + '.tab");\n' - '#else\n' - ' static ap_uint<10> lut[] =\n' - '#if __has_include("../emData/'+arguments.LUTsDir+'/TP_' + seed + '.tab")\n' - '# include "../emData/'+arguments.LUTsDir+'/TP_' + seed + '.tab"\n' - '#else\n' - ' {};\n' - '#endif\n' - '#endif\n' - ' return lut;\n' - '}\n' - 'template<> inline const ap_uint<1>* getPTInnerLUT(){\n' - '#ifndef __SYNTHESIS__\n' - '#ifdef CMSSW_GIT_HASH\n' - ' static std::mutex getLUTMutex_;\n' - ' std::lock_guard lock(getLUTMutex_);\n' - '#endif\n' - ' static ap_uint<1> lut[' + innerPTLUTSize[seed] + '];\n' - ' static bool init = 0;\n' - ' if (!init)\n' - ' init = readSWLUT,' + innerPTLUTSize[seed] + ' >(lut,"'+arguments.LUTsDir+'/TP_' + seed + iTC + '_stubptinnercut.tab");\n' - '#else\n' - ' static ap_uint<1> lut[] =\n' - '#if __has_include("../emData/'+arguments.LUTsDir+'/TP_' + seed + iTC +'_stubptinnercut.tab")\n' - '# include "../emData/'+arguments.LUTsDir+'/TP_' + seed + iTC + '_stubptinnercut.tab"\n' - '#else\n' - ' {};\n' - '#endif\n' - '#endif\n' - ' return lut;\n' - '}\n' - 'template<> inline const ap_uint<1>* getPTOuterLUT(){\n' - '#ifndef __SYNTHESIS__\n' - '#ifdef CMSSW_GIT_HASH\n' - ' static std::mutex getLUTMutex_;\n' - ' std::lock_guard lock(getLUTMutex_);\n' - '#endif\n' - ' static ap_uint<1> lut[' + outerPTLUTSize[seed] + '];\n' - ' static bool init = 0;\n' - ' if (!init)\n' - ' init = readSWLUT,' + outerPTLUTSize[seed] + '>(lut,"'+arguments.LUTsDir+'/TP_' + seed + iTC + '_stubptoutercut.tab");\n' - '#else\n' - ' static ap_uint<1> lut[] =\n' - '#if __has_include("../emData/'+arguments.LUTsDir+'/TP_' + seed + iTC +'_stubptoutercut.tab")\n' - '# include "../emData/'+arguments.LUTsDir+'/TP_' + seed + iTC + '_stubptoutercut.tab"\n' - '#else\n' - ' {};\n' - '#endif\n' - '#endif\n' - ' return lut;\n' - '}\n' - 'template<> constexpr int nASMemInner(){\n' - ' return ' + str(nASMemInner) + ';\n' - '}\n' -)% (tprojMaskBarrel, tprojMaskDisk) - ) - if seed not in seedlist: - seedlist.append(seed) - # Print out prototype for top function for this TC. - topHeaderFile.write( - "\n" - "void TrackletProcessor_" + seed + iTC + "(\n" - " const BXType bx,\n" - " BXType& bx_o,\n" - " const AllStubInnerMemory()> innerStubs[TP::nASMemInner()],\n" - " const AllStubMemory()>* outerStubs,\n" - " const VMStubMemory(), kNbitsrzbin, kNbitsphibin, kNTEUnitsLayerDisk[TF::"+seed[2:]+"], true>* outerVMStubs,\n" - " TrackletParameterMemory * trackletParameters,\n" - " TrackletProjectionMemory projout_barrel_ps[],\n" - " TrackletProjectionMemory projout_barrel_2s[],\n" - " TrackletProjectionMemory projout_disk[]\n" - ");\n" - ) - - # Print out definition of top function for this TP. - topFile.write( - "\n" - "void TrackletProcessor_" + seed + iTC + "(\n" - " const BXType bx,\n" - " BXType& bx_o,\n" - " const AllStubInnerMemory()> innerStubs[TP::nASMemInner()],\n" - " const AllStubMemory()>* outerStubs ,\n" - " const VMStubMemory(), kNbitsrzbin, kNbitsphibin, kNTEUnitsLayerDisk[TF::"+ seed[2:] +"], true>* outerVMStubs,\n" - " TrackletParameterMemory * trackletParameters,\n" - " TrackletProjectionMemory projout_barrel_ps[TP::N_PROJOUT_BARRELPS],\n" - " TrackletProjectionMemory projout_barrel_2s[TP::N_PROJOUT_BARREL2S],\n" - " TrackletProjectionMemory projout_disk[TP::N_PROJOUT_DISK]\n" - ") {\n" - "#pragma HLS inline recursive\n" - "#pragma HLS interface register port=bx_o\n" - ) - for i in range(0, nASMemInner): - topFile.write("#pragma HLS resource variable=innerStubs[" + str(i) + "].get_mem() latency=2\n") - topFile.write("#pragma HLS resource variable=outerStubs->get_mem() latency=2\n") - topFile.write("#pragma HLS resource variable=outerVMStubs.get_mem() latency=2\n") - topFile.write( - "#pragma HLS array_partition variable=projout_barrel_ps complete dim=1\n" - "#pragma HLS array_partition variable=projout_barrel_2s complete dim=1\n" - "#pragma HLS array_partition variable=projout_disk complete dim=1\n" - "\n" - "static const ap_uint<10>* lut = TP::getLUT();\n" - "\n" - "TP_" + seed + iTC + ": TrackletProcessor<\n" - " TF::" + seed + ",\n" - " TP::" + iTC + ",\n" - " kNTEUnitsLayerDisk[TF::" + seed[2:]+ "],\n" - " TP::nASMemInner(),\n" - " 108>(\n" - " bx,\n" - " bx_o,\n" - " lut,\n" - " innerStubs,\n" - " outerStubs,\n" - " outerVMStubs,\n" - " trackletParameters,\n" - " projout_barrel_ps,\n" - " projout_barrel_2s,\n" - " projout_disk\n" - " );\n" - "}\n" - ) - - # Print out endifs and close files. - parametersFile.write( - "}\n" - "#endif\n" - ) - topHeaderFile.write( - "\n" - "#endif\n" - ) - topFile.write( - "\n" - "////////////////////////////////////////////////////////////////////////////////\n" - ) - + # Calculate parameters and print out parameters and top function for each TP. + seedlist = [] #keeps track of seeds that have been looped over for functions that only exist once per seed type + for tpName in sorted(asInnerMems.keys()): + seed = re.sub(r"TP_(....).", r"\1", tpName) + iTC = re.sub(r"TP_....(.)", r"\1", tpName) + # numbers of memories + nASMemInner = len(asInnerMems[tpName]) + nASMemOuter = len(asOuterMems[tpName]) + nVMSTEMem = len(vmsteMems[tpName]) + # AS inner and outer masks + asInnerMask = 0 + asOuterMask = 0 + asInnerMems[tpName].sort() + asOuterMems[tpName].sort() + + # TPROJ masks for barrel and disks + tprojMaskBarrel = 0 + tprojMaskDisk = 0 + if tpName in tprojMems : + for projout in ProjoutIndexBarrel: + projoutName = "TPROJ_" + seed + iTC + "_" + projout.name + projoutIndex = projout.value + if projoutName in tprojMems[tpName]: + tprojMaskBarrel = tprojMaskBarrel | (1 << projoutIndex) + for projout in ProjoutIndexDisk: + projoutName = "TPROJ_" + seed + iTC + "_" + projout.name + projoutIndex = projout.value + if projoutName in tprojMems[tpName]: + tprojMaskDisk = tprojMaskDisk | (1 << projoutIndex) + else: + #This corresponds to the case where we don't have projections the + #configuration because they are now done in the PC. However, we are + #maintaining the possibility to have projections for compatibility + #with the new emulation code. In any rational world we would set + #these masks below to zero, but this leads to a hard crash in vivado + #documented in email between ryd and ahart on Dec. 10&11 2024. + tprojMaskBarrel = 1 + tprojMaskDisk = 1 + + # figure out sizes of LUTs by reading .tab files, do once per seed type + if seed not in seedlist: + #LUTSize[seed] = str(sum(1 for _ in open(arguments.LUTsDir+"/TP_{0}.tab".format(seed))) - 2) + #regLUTSize[seed] = str(sum(1 for _ in open(arguments.LUTsDir+"/TP_{0}{1}_usereg.tab".format(seed,iTC))) - 2) + #innerPTLUTSize[seed] = str(sum(1 for _ in open(arguments.LUTsDir+"/TP_{0}{1}_stubptinnercut.tab".format(seed,iTC))) - 2) + #outerPTLUTSize[seed] = str(sum(1 for _ in open(arguments.LUTsDir+"/TP_{0}{1}_stubptoutercut.tab".format(seed,iTC))) - 2) + with open(arguments.LUTsDir+"/TP_{0}.tab".format(seed)) as f_tp: + LUTSize[seed] = str(sum(1 for _ in f_tp) - 2) + with open(arguments.LUTsDir+"/TP_{0}{1}_usereg.tab".format(seed,iTC)) as f_usereg: + regLUTSize[seed] = str(sum(1 for _ in f_usereg) - 2) + with open(arguments.LUTsDir+"/TP_{0}{1}_stubptinnercut.tab".format(seed,iTC)) as f_stubptinnercut: + innerPTLUTSize[seed] = str(sum(1 for _ in f_stubptinnercut) - 2) + with open(arguments.LUTsDir+"/TP_{0}{1}_stubptoutercut.tab".format(seed,iTC)) as f_stubptoutercut: + outerPTLUTSize[seed] = str(sum(1 for _ in f_stubptoutercut) - 2) + # Print out parameters for this TP. + parametersFile.write( + ("\n" + "template<> constexpr uint32_t TPROJMaskBarrel() {\n" + " return 0x%X;\n" + "}\n" + "template<> constexpr uint32_t TPROJMaskDisk() {\n" + " return 0x%X;\n" + "}\n" + 'template<> inline const ap_uint<10>* getLUT(){\n' + '#ifndef __SYNTHESIS__\n' + '#ifdef CMSSW_GIT_HASH\n' + ' static std::mutex getLUTMutex_;\n' + ' std::lock_guard lock(getLUTMutex_);\n' + '#endif\n' + ' static ap_uint<10> lut[' + LUTSize[seed] + '];\n' + ' static bool init = 0;\n' + ' if (!init)\n' + ' init = readSWLUT,' + LUTSize[seed] +'>(lut,"'+arguments.LUTsDir+'/TP_' + seed + '.tab");\n' + '#else\n' + ' static ap_uint<10> lut[] =\n' + '#if __has_include("../emData/'+arguments.LUTsDir+'/TP_' + seed + '.tab")\n' + '# include "../emData/'+arguments.LUTsDir+'/TP_' + seed + '.tab"\n' + '#else\n' + ' {};\n' + '#endif\n' + '#endif\n' + ' return lut;\n' + '}\n' + 'template<> inline const ap_uint<1>* getPTInnerLUT(){\n' + '#ifndef __SYNTHESIS__\n' + '#ifdef CMSSW_GIT_HASH\n' + ' static std::mutex getLUTMutex_;\n' + ' std::lock_guard lock(getLUTMutex_);\n' + '#endif\n' + ' static ap_uint<1> lut[' + innerPTLUTSize[seed] + '];\n' + ' static bool init = 0;\n' + ' if (!init)\n' + ' init = readSWLUT,' + innerPTLUTSize[seed] + ' >(lut,"'+arguments.LUTsDir+'/TP_' + seed + iTC + '_stubptinnercut.tab");\n' + '#else\n' + ' static ap_uint<1> lut[] =\n' + '#if __has_include("../emData/'+arguments.LUTsDir+'/TP_' + seed + iTC +'_stubptinnercut.tab")\n' + '# include "../emData/'+arguments.LUTsDir+'/TP_' + seed + iTC + '_stubptinnercut.tab"\n' + '#else\n' + ' {};\n' + '#endif\n' + '#endif\n' + ' return lut;\n' + '}\n' + 'template<> inline const ap_uint<1>* getPTOuterLUT(){\n' + '#ifndef __SYNTHESIS__\n' + '#ifdef CMSSW_GIT_HASH\n' + ' static std::mutex getLUTMutex_;\n' + ' std::lock_guard lock(getLUTMutex_);\n' + '#endif\n' + ' static ap_uint<1> lut[' + outerPTLUTSize[seed] + '];\n' + ' static bool init = 0;\n' + ' if (!init)\n' + ' init = readSWLUT,' + outerPTLUTSize[seed] + '>(lut,"'+arguments.LUTsDir+'/TP_' + seed + iTC + '_stubptoutercut.tab");\n' + '#else\n' + ' static ap_uint<1> lut[] =\n' + '#if __has_include("../emData/'+arguments.LUTsDir+'/TP_' + seed + iTC +'_stubptoutercut.tab")\n' + '# include "../emData/'+arguments.LUTsDir+'/TP_' + seed + iTC + '_stubptoutercut.tab"\n' + '#else\n' + ' {};\n' + '#endif\n' + '#endif\n' + ' return lut;\n' + '}\n' + 'template<> constexpr int nASMemInner(){\n' + ' return ' + str(nASMemInner) + ';\n' + '}\n' + )% (tprojMaskBarrel, tprojMaskDisk) + ) + if seed not in seedlist: + seedlist.append(seed) + # Print out prototype for top function for this TC. + topHeaderFile.write( + "\n" + "void TrackletProcessor_" + seed + iTC + "(\n" + " const BXType bx,\n" + " BXType& bx_o,\n" + " const AllStubInnerMemory()> innerStubs[TP::nASMemInner()],\n" + " const AllStubMemory()>* outerStubs,\n" + " const VMStubMemory(), kNbitsrzbin, kNbitsphibin, kNTEUnitsLayerDisk[TF::"+seed[2:]+"], true>* outerVMStubs,\n" + " TrackletParameterMemory * trackletParameters,\n" + " TrackletProjectionMemory projout_barrel_ps[],\n" + " TrackletProjectionMemory projout_barrel_2s[],\n" + " TrackletProjectionMemory projout_disk[]\n" + ");\n\n" + ) + + # Print out definition of top function for this TP. + topFile.write( + "\n" + "void TrackletProcessor_" + seed + iTC + "(\n" + " const BXType bx,\n" + " BXType& bx_o,\n" + " const AllStubInnerMemory()> innerStubs[TP::nASMemInner()],\n" + " const AllStubMemory()>* outerStubs ,\n" + " const VMStubMemory(), kNbitsrzbin, kNbitsphibin, kNTEUnitsLayerDisk[TF::"+ seed[2:] +"], true>* outerVMStubs,\n" + " TrackletParameterMemory * trackletParameters,\n" + " TrackletProjectionMemory projout_barrel_ps[TP::N_PROJOUT_BARRELPS],\n" + " TrackletProjectionMemory projout_barrel_2s[TP::N_PROJOUT_BARREL2S],\n" + " TrackletProjectionMemory projout_disk[TP::N_PROJOUT_DISK]\n" + ") {\n" + "#pragma HLS inline recursive\n" + "#pragma HLS interface register port=bx_o\n" + ) + for i in range(0, nASMemInner): + topFile.write("#pragma HLS resource variable=innerStubs[" + str(i) + "].get_mem() latency=2\n") + topFile.write("#pragma HLS resource variable=outerStubs->get_mem() latency=2\n") + topFile.write("#pragma HLS resource variable=outerVMStubs.get_mem() latency=2\n") + topFile.write( + "#pragma HLS array_partition variable=projout_barrel_ps complete dim=1\n" + "#pragma HLS array_partition variable=projout_barrel_2s complete dim=1\n" + "#pragma HLS array_partition variable=projout_disk complete dim=1\n" + "\n" + "static const ap_uint<10>* lut = TP::getLUT();\n" + "\n" + "TP_" + seed + iTC + ": TrackletProcessor<\n" + " TF::" + seed + ",\n" + " TP::" + iTC + ",\n" + " kNTEUnitsLayerDisk[TF::" + seed[2:]+ "],\n" + " TP::nASMemInner(),\n" + " 108>(\n" + " bx,\n" + " bx_o,\n" + " lut,\n" + " innerStubs,\n" + " outerStubs,\n" + " outerVMStubs,\n" + " trackletParameters,\n" + " projout_barrel_ps,\n" + " projout_barrel_2s,\n" + " projout_disk\n" + " );\n" + "}\n" + ) + + # Print out endifs and close files. + parametersFile.write( + "}\n" + "#endif\n" + ) + topHeaderFile.write( + "\n" + "#endif\n" + ) + topFile.write( + "\n" + "////////////////////////////////////////////////////////////////////////////////\n" + ) diff --git a/emData/generate_VMRCM.py b/emData/generate_VMRCM.py index 60068197071..3f32f44bcc3 100755 --- a/emData/generate_VMRCM.py +++ b/emData/generate_VMRCM.py @@ -12,8 +12,8 @@ import collections # Constants -num_layers = 6 -num_disks = 5 +numLayers = 6 +numDisks = 5 # Lists of which layer/disk has AllStubInner ans VMSTE memories has_allstub_inner = [True, True, True, False, True, False, True, False, True, False, False] @@ -26,47 +26,45 @@ # One key for every memory type in each layer/disk # Value is a list of all memory names for that key -def getDictOfMemories(wireconfig, vmr_list): +def getDictOfMemories(wireconfig, vmrlist): # Dictionary of all the input and output memories mem_dict = {} # Open wiring file - wires_file = open(wireconfig) - - # Loop over each line in the wiring - for line in wires_file: - # Check if any of the VMRs exist in the line - for vmr in vmr_list: - if vmr in line: - mem_name = line.split()[0] - mem_type = mem_name.split("_")[0] - # Check if memory type is Inner AllStub or IL DISK2S - if "IL_D" in mem_name and "2S" in mem_name: - mem_type = mem_type + "_DISK2S_" + vmr - elif "innerallstubin" in line: - mem_type = mem_type + "I_" + vmr - else: - mem_type = mem_type + "_" + vmr - # Add memory and memory type to dictionary - if mem_type not in mem_dict: - mem_dict[mem_type] = [mem_name] - else: - mem_dict[mem_type].append(mem_name) - break - - # Loop over all memories and add an empty IL DISK2S, AllStub Inner, and VMSTE memory lists if missing in dictionary - for vmr in vmr_list: - if "IL_DISK2S_" + vmr not in mem_dict: - mem_dict["IL_DISK2S_" + vmr] = [] - if "VMSTE_" + vmr not in mem_dict: - mem_dict["VMSTE_" + vmr] = [] - if "AS_" + vmr not in mem_dict: - mem_dict["AS_" + vmr] = [] - if "ASI_" + vmr not in mem_dict: - mem_dict["ASI_" + vmr] = [] - - wires_file.close() + with open(wireconfig) as wires_file: + + # Loop over each line in the wiring + for line in wires_file: + # Check if any of the VMRs exist in the line + for vmr in vmrlist: + if vmr in line: + mem_name = line.split()[0] + mem_type = mem_name.split("_")[0] + # Check if memory type is Inner AllStub or IL DISK2S + if "IL_D" in mem_name and "2S" in mem_name: + mem_type = mem_type + "_DISK2S_" + vmr + elif "innerallstubin" in line: + mem_type = mem_type + "I_" + vmr + else: + mem_type = mem_type + "_" + vmr + # Add memory and memory type to dictionary + if mem_type not in mem_dict: + mem_dict[mem_type] = [mem_name] + else: + mem_dict[mem_type].append(mem_name) + break + + # Loop over all memories and add an empty IL DISK2S, AllStub Inner, and VMSTE memory lists if missing in dictionary + for vmr in vmrlist: + if "IL_DISK2S_" + vmr not in mem_dict: + mem_dict["IL_DISK2S_" + vmr] = [] + if "VMSTE_" + vmr not in mem_dict: + mem_dict["VMSTE_" + vmr] = [] + if "AS_" + vmr not in mem_dict: + mem_dict["AS_" + vmr] = [] + if "ASI_" + vmr not in mem_dict: + mem_dict["ASI_" + vmr] = [] return mem_dict @@ -97,21 +95,19 @@ def getDictOfCopies(mem_list): def getAllVMRs(wireconfig): - vmr_list = [] + vmrlist = [] # Open wiring file - wires_file = open(wireconfig) - - # Loop over each line in the wiring - for line in wires_file: - module_name = line.split(" ")[-1].split(".")[0] - # Add module name if not already in vmr_list - if "VMR" in module_name and module_name not in vmr_list: - vmr_list.append(module_name) + with open(wireconfig) as wires_file: - wires_file.close() + # Loop over each line in the wiring + for line in wires_file: + module_name = line.split(" ")[-1].split(".")[0] + # Add module name if not already in vmr_list + if "VMR" in module_name and module_name not in vmrlist: + vmrlist.append(module_name) - return vmr_list + return vmrlist ################################### # Returns a string of the AllStub Inner memory mask @@ -123,14 +119,14 @@ def getAllVMRs(wireconfig): def getAllStubInnerMaskString(mem_list): as_inner_list = ["OR", "OM", "OL", "BR/DR", "BM/DM", "BL/DL", "BF", "BE", "BD", "BC", "BB", "BA"] - mask = "0b"; + mask = "0b" # Loop over all the different AllStub Inner type for mem_type in as_inner_list: if any(mem_type in mem for mem in mem_list): mask += "1" elif "/" in mem_type: - if any(mem_type.split("/")[0] in mem for mem in mem_list) or any(mem_type.split("/")[1] in mem for mem in mem_list): + if any(mem_type.split("/", maxsplit = 1)[0] in mem for mem in mem_list) or any(mem_type.split("/")[1] in mem for mem in mem_list): mask += "1" else: mask += "0" @@ -159,160 +155,162 @@ def getNumFEInputs(mem_list): def writeParameterFile(vmr_list, mem_dict, output_dir): - parameter_file = open(output_dir + "/VMRouterCM_parameters.h", "w") - - # Write preamble - parameter_file.write( - "#ifndef TopFunctions_VMRouterCM_parameters_h\n" - "#define TopFunctions_VMRouterCM_parameters_h\n" - "\n" - "// Hardcoded number of memories and masks from the wiring.\n" - "// Generated by generate_VMRCM.py\n\n" - ) - - # Declare functions - parameter_file.write( - "// The functions that returns parameters and LUTs\n" - "template const int* getPhiCorrTable();\n" - "template const int* getMETable();\n" - "template const int* getTETable();\n" - "template constexpr regionType getInputType();\n" - "template constexpr regionType getOutputType();\n" - "template constexpr int getNumInputs();\n" - "template constexpr int getNumInputsDisk2S();\n" - "template constexpr int getNumASCopies();\n" - "template constexpr int getNumASInnerCopies();\n" - "template constexpr int getNumTEOCopies();\n" - "template constexpr int getAllStubInnerMask();\n" - "// For Future Emulation\n" - "template constexpr int getNumInputsFE();\n" - "template constexpr int getNumInputsDisk2SFE();\n" - "\n" - "// VMPhiCorr LUTs\n" - ) - - # Write phi correction LUTs functions - for i in range(num_layers): - parameter_file.write( - "template<> inline const int* getPhiCorrTable(){\n" - " static int lut[] = \n" - "#if __has_include(\"../emData/VMRCM/tables/VMPhiCorrL" + str(i+1) + ".tab\")\n# include \"../emData/VMRCM/tables/VMPhiCorrL" + str(i+1) + ".tab\"\n#else\n {};\n#endif\n" - " return lut;\n" - "}\n" - ) - for i in range(num_disks): - parameter_file.write( - "template<> inline const int* getPhiCorrTable(){\n" - " return nullptr;\n" - "}\n" - ) - - # Write ME Tables - parameter_file.write("\n// ME Tables\n") - for i in range(num_layers): - parameter_file.write( - "template<> inline const int* getMETable(){\n" - " static int lut[] =\n" - "#if __has_include(\"../emData/VMRCM/tables/VMRME_L" + str(i+1) + ".tab\")\n# include \"../emData/VMRCM/tables/VMRME_L" + str(i+1) + ".tab\"\n#else\n {};\n#endif\n return lut;\n" - "}\n" - ) - for i in range(num_disks): - parameter_file.write( - "template<> inline const int* getMETable(){\n" - " static int lut[] =\n" - "#if __has_include(\"../emData/VMRCM/tables/VMRME_D" + str(i+1) + ".tab\")\n# include \"../emData/VMRCM/tables/VMRME_D" + str(i+1) + ".tab\"\n#else\n {};\n#endif\n return lut;\n" - "}\n" - ) - - # Write TE Tables - parameter_file.write("\n// TE Tables\n") - for i in range(num_layers): - parameter_file.write( - "template<> inline const int* getTETable(){\n" - " return nullptr;\n" - "}\n" - ) - for i in range(num_disks): - parameter_file.write( - "template<> inline const int* getTETable(){\n" - +(" static int lut[] =\n#if __has_include(\"../emData/VMRCM/tables/VMRTE_D" + str(i+1) + ".tab\")\n# include \"../emData/VMRCM/tables/VMRTE_D" + str(i+1) + ".tab\"\n#else\n {};\n#endif\n return lut;\n" if has_vmste_outer[i+num_layers] else " return nullptr;\n")+ - "}\n" - ) - - # Write InputType functions - parameter_file.write("\n// InputType\n") - for i in range(num_layers): - parameter_file.write( - "template<> constexpr regionType getInputType(){\n" - " return " + ("BARRELPS" if i < 3 else "BARREL2S") + ";\n" - "}\n" - ) - for i in range(num_disks): - parameter_file.write( - "template<> constexpr regionType getInputType(){\n" - " return DISKPS;\n" - "}\n" - ) + with open(output_dir + "/VMRouterCM_parameters.h", "w") as parameter_file: - # Write OutputType functions - parameter_file.write("\n// OutputType\n") - for i in range(num_layers): + # Write preamble parameter_file.write( - "template<> constexpr regionType getOutputType(){\n" - " return " + ("BARRELPS" if i < 3 else "BARREL2S") + ";\n" - "}\n" - ) - for i in range(num_disks): - parameter_file.write( - "template<> constexpr regionType getOutputType(){\n" - " return DISK;\n" - "}\n" + "#ifndef TopFunctions_VMRouterCM_parameters_h\n" + "#define TopFunctions_VMRouterCM_parameters_h\n" + "\n" + "// Hardcoded number of memories and masks from the wiring.\n" + "// Generated by generate_VMRCM.py\n\n" ) - # Write VMR specific functions - for vmr in vmr_list: - - layer_disk_char = vmr.split("_")[1][0] # 'L' or 'D' - layer_disk_num = int(vmr.split("_")[1][1]) - phi_region= vmr.split("PHI")[1] - - # Get the number of copies for the specified TE memory type - mem_copy_dict = getDictOfCopies(mem_dict["VMSTE_" + vmr]) - max_copy_count = max(mem_copy_dict.values()) if mem_copy_dict else 0 - + # Declare functions parameter_file.write( - "\n////////////////\n// " + vmr + " //\n////////////////\n" - "template<> constexpr int getNumInputs(){ // Number of input memories, EXCLUDING DISK2S\n" - " return " + str(len(mem_dict["IL_"+vmr])) + ";\n" - "}\n" - "template<> constexpr int getNumInputsDisk2S(){ // Number of DISK2S input memories\n" - " return " + str(len(mem_dict["IL_DISK2S_"+vmr])) + ";\n" - "}\n" - "template<> constexpr int getNumASCopies(){ // Allstub memory\n" - " return " + str(len(mem_dict["AS_"+vmr])) + ";\n" - "}\n" - "template<> constexpr int getNumASInnerCopies(){ // Allstub Inner memory\n" - " return " + str(len(mem_dict["ASI_"+vmr])) + ";\n" - "}\n" - "template<> constexpr int getNumTEOCopies(){ // TE Outer memories\n" - " return " + str(max_copy_count) + ";\n" - "}\n" - "template<> constexpr int getAllStubInnerMask(){\n" - " return " + getAllStubInnerMaskString(mem_dict["ASI_"+vmr]) + ";\n" - "}\n" + "// The functions that returns parameters and LUTs\n" + "template const int* getPhiCorrTable();\n" + "template const int* getMETable();\n" + "template const int* getTETable();\n" + "template constexpr regionType getInputType();\n" + "template constexpr regionType getOutputType();\n" + "template constexpr int getNumInputs();\n" + "template constexpr int getNumInputsDisk2S();\n" + "template constexpr int getNumASCopies();\n" + "template constexpr int getNumASInnerCopies();\n" + "template constexpr int getNumTEOCopies();\n" + "template constexpr int getAllStubInnerMask();\n" "// For Future Emulation\n" - "template<> constexpr int getNumInputsFE(){ // Number of input memories, EXCLUDING DISK2S\n" - " return " + str(getNumFEInputs(mem_dict["IL_"+vmr])) + ";\n" - "}\n" - "template<> constexpr int getNumInputsDisk2SFE(){ // Number of DISK2S input memories\n" - " return " + str(getNumFEInputs(mem_dict["IL_DISK2S_"+vmr])) + ";\n" - "}\n" + "template constexpr int getNumInputsFE();\n" + "template constexpr int getNumInputsDisk2SFE();\n" + "\n" + "// VMPhiCorr LUTs\n" ) - # End parameter file - parameter_file.write("\n#endif // TopFunctions_VMRouterCM_parameters_h\n") - parameter_file.close() + # Write phi correction LUTs functions + for i in range(numLayers): + parameter_file.write( + "template<> inline const int* getPhiCorrTable(){\n" + " static int lut[] = \n" + "#if __has_include(\"../emData/VMRCM/tables/VMPhiCorrL" + str(i+1) + ".tab\")\n# include \"../emData/VMRCM/tables/VMPhiCorrL" + str(i+1) + ".tab\"\n#else\n {};\n#endif\n" + " return lut;\n" + "}\n" + ) + for i in range(numDisks): + parameter_file.write( + "template<> inline const int* getPhiCorrTable(){\n" + " return nullptr;\n" + "}\n" + ) + + # Write ME Tables + parameter_file.write("\n// ME Tables\n") + for ilayer in range(numLayers): + parameter_file.write( + "template<> inline const int* getMETable(){\n" + " static int lut[] =\n" + "#if __has_include(\"../emData/VMRCM/tables/VMRME_L" + str(ilayer+1) + ".tab\")\n# include \"../emData/VMRCM/tables/VMRME_L" + str(ilayer+1) + ".tab\"\n#else\n {};\n#endif\n return lut;\n" + "}\n" + ) + + for idisk in range(numDisks): + parameter_file.write( + "template<> inline const int* getMETable(){\n" + " static int lut[] =\n" + "#if __has_include(\"../emData/VMRCM/tables/VMRME_D" + str(idisk+1) + ".tab\")\n# include \"../emData/VMRCM/tables/VMRME_D" + str(idisk+1) + ".tab\"\n#else\n {};\n#endif\n return lut;\n" + "}\n" + ) + + # Write TE Tables + parameter_file.write("\n// TE Tables\n") + for ilayer in range(numLayers): + parameter_file.write( + "template<> inline const int* getTETable(){\n" + " return nullptr;\n" + "}\n" + ) + + for idisk in range(numDisks): + parameter_file.write( + "template<> inline const int* getTETable(){\n" + +(" static int lut[] =\n#if __has_include(\"../emData/VMRCM/tables/VMRTE_D" + str(idisk+1) + ".tab\")\n# include \"../emData/VMRCM/tables/VMRTE_D" + str(idisk+1) + ".tab\"\n#else\n {};\n#endif\n return lut;\n" if has_vmste_outer[idisk+numLayers] else " return nullptr;\n")+ + "}\n" + ) + + # Write InputType functions + parameter_file.write("\n// InputType\n") + for ilayer in range(numLayers): + parameter_file.write( + "template<> constexpr regionType getInputType(){\n" + " return " + ("BARRELPS" if ilayer < 3 else "BARREL2S") + ";\n" + "}\n" + ) + + for idisk in range(numDisks): + parameter_file.write( + "template<> constexpr regionType getInputType(){\n" + " return DISKPS;\n" + "}\n" + ) + + # Write OutputType functions + parameter_file.write("\n// OutputType\n") + for ilayer in range(numLayers): + parameter_file.write( + "template<> constexpr regionType getOutputType(){\n" + " return " + ("BARRELPS" if ilayer < 3 else "BARREL2S") + ";\n" + "}\n" + ) + + for idisk in range(numDisks): + parameter_file.write( + "template<> constexpr regionType getOutputType(){\n" + " return DISK;\n" + "}\n" + ) + + # Write VMR specific functions + for vmr in vmr_list: + layer_disk_char = vmr.split("_")[1][0] # 'L' or 'D' + layer_disk_num = int(vmr.split("_")[1][1]) + phi_region= vmr.split("PHI")[1] + + # Get the number of copies for the specified TE memory type + mem_copy_dict = getDictOfCopies(mem_dict["VMSTE_" + vmr]) + max_copy_count = max(mem_copy_dict.values()) if mem_copy_dict else 0 + + parameter_file.write( + "\n////////////////\n// " + vmr + " //\n////////////////\n" + "template<> constexpr int getNumInputs(){ // Number of input memories, EXCLUDING DISK2S\n" + " return " + str(len(mem_dict["IL_"+vmr])) + ";\n" + "}\n" + "template<> constexpr int getNumInputsDisk2S(){ // Number of DISK2S input memories\n" + " return " + str(len(mem_dict["IL_DISK2S_"+vmr])) + ";\n" + "}\n" + "template<> constexpr int getNumASCopies(){ // Allstub memory\n" + " return " + str(len(mem_dict["AS_"+vmr])) + ";\n" + "}\n" + "template<> constexpr int getNumASInnerCopies(){ // Allstub Inner memory\n" + " return " + str(len(mem_dict["ASI_"+vmr])) + ";\n" + "}\n" + "template<> constexpr int getNumTEOCopies(){ // TE Outer memories\n" + " return " + str(max_copy_count) + ";\n" + "}\n" + "template<> constexpr int getAllStubInnerMask(){\n" + " return " + getAllStubInnerMaskString(mem_dict["ASI_"+vmr]) + ";\n" + "}\n" + "// For Future Emulation\n" + "template<> constexpr int getNumInputsFE(){ // Number of input memories, EXCLUDING DISK2S\n" + " return " + str(getNumFEInputs(mem_dict["IL_"+vmr])) + ";\n" + "}\n" + "template<> constexpr int getNumInputsDisk2SFE(){ // Number of DISK2S input memories\n" + " return " + str(getNumFEInputs(mem_dict["IL_DISK2S_"+vmr])) + ";\n" + "}\n" + ) + + # End parameter file + parameter_file.write("\n#endif // TopFunctions_VMRouterCM_parameters_h\n") ################################# # Writes the VMRouterCMTop.h file @@ -322,73 +320,70 @@ def writeTopHeader(vmr, output_dir): # Get layer/disk number and phi region layer = int(vmr.split("_")[1][1] if vmr.split("_")[1][0] == "L" else 0) disk = int(0 if layer else vmr.split("_")[1][1]) - layerdisk = layer-1 if layer else disk+num_layers-1 + layerdisk = layer-1 if layer else disk+numLayers-1 phi_region = vmr.split("PHI")[1] # Top file name file_name = "VMRouterCMTop_" + vmr.split("_")[1] - header_file = open(output_dir + "/" + file_name + ".h", "w") - - # Write preamble - header_file.write( - "#ifndef TopFunctions_" + file_name + "_h\n" +\ - "#define TopFunctions_" + file_name + "_h\n" +\ - "\n" - "#include \"VMRouterCM.h\"\n" - "#include \"VMRouterCM_parameters.h\"\n" - "\n" - "// VMRouterCM Top Function\n" - "// Sort stubs into smaller regions in phi, i.e. Virtual Modules (VMs).\n" - "\n" - "////////////////////////////////////////////\n" - "// Variables for that are specified with regards to the VMR region\n" - "// Some are used by the Test Bench\n" - "\n" - ) - - # Write the configuration - header_file.write( - "#define kLAYER " + str(layer) + " // Which barrel layer number the data is coming from\n" - "#define kDISK " + str(disk) + " // Which disk number the data is coming from, 0 if not disk\n" - "constexpr TF::phiRegion phiRegion = TF::" + phi_region+ "; // Which AllStub/PhiRegion\n" - "\n" - "constexpr TF::layerDisk layerdisk = static_cast((kLAYER) ? kLAYER-1 : trklet::N_LAYER+kDISK-1);\n" - "constexpr regionType inputType = getInputType();\n" - "constexpr regionType outputType = getOutputType();\n" - "// Number of inputs\n" - "constexpr int numInputs = getNumInputs(); // Number of input memories, EXCLUDING DISK2S\n" - "constexpr int numInputsDisk2S = getNumInputsDisk2S(); // Number of DISK2S input memories\n" - "// Maximum number of memory \"copies\" for this Phi region\n" - "constexpr int numASCopies = getNumASCopies(); // Allstub memory\n" - "constexpr int numASInnerCopies = getNumASInnerCopies(); // Allstub Inner memory\n" - "constexpr int numTEOCopies = getNumTEOCopies(); // TE Outer memories\n" - "// Number of bits for the RZ bins \n" - "constexpr int kNbitsrzbinME = kNbitsrzbin%s; // For the VMSME memories\n" % ("MELayer" if layer else "MEDisk") +\ - "\n\n" - ) - - # Write the top function - header_file.write( - "/////////////////////////////////////////////////////\n" - "// VMRouterCM Top Function\n" - "\n" - "void %s(const BXType bx, BXType& bx_o,\n" % file_name +\ - " // Input memories\n" - " const InputStubMemory inputStubs[numInputs],\n" - + (" const InputStubMemory inputStubsDisk2S[numInputsDisk2S],\n" if disk else "") +\ - " // Output memories\n" - " AllStubMemory memoriesAS[numASCopies],\n" - + (" AllStubInnerMemory memoriesASInner[numASInnerCopies],\n" if has_allstub_inner[layerdisk] else "") +\ - " VMStubMemory *memoryME" + (",\n" if has_vmste_outer[layerdisk] else "") - + (" VMStubMemory memoriesTEO[numTEOCopies]\n" if has_vmste_outer[layerdisk] else "") +\ - " );\n" - "\n" - "#endif // TopFunctions_%s_h\n" % file_name - ) + with open(output_dir + "/" + file_name + ".h", "w") as header_file: + + # Write preamble + header_file.write( + "#ifndef TopFunctions_" + file_name + "_h\n" +\ + "#define TopFunctions_" + file_name + "_h\n" +\ + "\n" + "#include \"VMRouterCM.h\"\n" + "#include \"VMRouterCM_parameters.h\"\n" + "\n" + "// VMRouterCM Top Function\n" + "// Sort stubs into smaller regions in phi, i.e. Virtual Modules (VMs).\n" + "\n" + "////////////////////////////////////////////\n" + "// Variables for that are specified with regards to the VMRCM region\n" + "// Some are used by the Test Bench\n" + "\n" + ) - header_file.close() + # Write the configuration + header_file.write( + "#define kLAYER " + str(layer) + " // Which barrel layer number the data is coming from\n" + "#define kDISK " + str(disk) + " // Which disk number the data is coming from, 0 if not disk\n" + "constexpr TF::phiRegion phiRegion = TF::" + phi_region+ "; // Which AllStub/PhiRegion\n" + "\n" + "constexpr TF::layerDisk layerdisk = static_cast((kLAYER) ? kLAYER-1 : trklet::N_LAYER+kDISK-1);\n" + "constexpr regionType inputType = getInputType();\n" + "constexpr regionType outputType = getOutputType();\n" + "// Number of inputs\n" + "constexpr int numInputs = getNumInputs(); // Number of input memories, EXCLUDING DISK2S\n" + "constexpr int numInputsDisk2S = getNumInputsDisk2S(); // Number of DISK2S input memories\n" + "// Maximum number of memory \"copies\" for this Phi region\n" + "constexpr int numASCopies = getNumASCopies(); // Allstub memory\n" + "constexpr int numASInnerCopies = getNumASInnerCopies(); // Allstub Inner memory\n" + "constexpr int numTEOCopies = getNumTEOCopies(); // TE Outer memories\n" + "// Number of bits for the RZ bins \n" + "constexpr int kNbitsrzbinME = kNbitsrzbin%s; // For the VMSME memories\n" % ("MELayer" if layer else "MEDisk") +\ + "\n\n" + ) + # Write the top function + header_file.write( + "/////////////////////////////////////////////////////\n" + "// VMRouterCM Top Function\n" + "\n" + "void %s(const BXType bx, BXType& bx_o,\n" % file_name +\ + " // Input memories\n" + " const InputStubMemory inputStubs[numInputs],\n" + + (" const InputStubMemory inputStubsDisk2S[numInputsDisk2S],\n" if disk else "") +\ + " // Output memories\n" + " AllStubMemory memoriesAS[numASCopies],\n" + + (" AllStubInnerMemory memoriesASInner[numASInnerCopies],\n" if has_allstub_inner[layerdisk] else "") +\ + " VMStubMemory *memoryME" + (",\n" if has_vmste_outer[layerdisk] else "") + + (" VMStubMemory memoriesTEO[numTEOCopies]\n" if has_vmste_outer[layerdisk] else "") +\ + " );\n" + "\n" + "#endif // TopFunctions_%s_h\n" % file_name + ) # Writes the VMRouterCMTop.cc file def writeTopFile(vmr, num_inputs, num_inputs_disk2s, output_dir): @@ -396,94 +391,91 @@ def writeTopFile(vmr, num_inputs, num_inputs_disk2s, output_dir): # Get layer/disk number layer = int(vmr.split("_")[1][1] if vmr.split("_")[1][0] == "L" else 0) disk = int(0 if layer else vmr.split("_")[1][1]) - layerdisk = layer-1 if layer else disk+num_layers-1 + layerdisk = layer-1 if layer else disk+numLayers-1 # Top file name file_name = "VMRouterCMTop_" + vmr.split("_")[1] - top_file = open(output_dir + "/" + file_name + ".cc", "w") - - # Write the top function - top_file.write( - "#include \"" + file_name + ".h\"\n\n" +\ - "// VMRouterCM Top Function\n" - "// Sort stubs into smaller regions in phi, i.e. Virtual Modules (VMs).\n" - "\n" - "void %s(\n" % file_name +\ - " const BXType bx, BXType& bx_o,\n" - " // Input memories\n" - " const InputStubMemory inputStubs[numInputs],\n" - + (" const InputStubMemory inputStubsDisk2S[numInputsDisk2S],\n" if disk else "") +\ - " // Output memories\n" - " AllStubMemory memoriesAS[numASCopies],\n" - + (" AllStubInnerMemory memoriesASInner[numASInnerCopies],\n" if has_allstub_inner[layerdisk] else "") +\ - " VMStubMemory *memoryME" + (",\n" if has_vmste_outer[layerdisk] else "") - + (" VMStubMemory memoriesTEO[numTEOCopies]\n" if has_vmste_outer[layerdisk] else "") +\ - " ) {\n" - "\n" - "// Takes 2 clock cycles before one gets data, used at high frequencies\n" - ) - - # Write pragmas - for i in range(num_inputs): - top_file.write("#pragma HLS resource variable=inputStubs[%s].get_mem() latency=2\n" % str(i)) - for i in range(num_inputs_disk2s): - top_file.write("#pragma HLS resource variable=inputStubsDisk2S[%s].get_mem() latency=2\n" % str(i)) - - top_file.write( - "#pragma HLS interface register port=bx_o\n" - "\n" - " ///////////////////////////\n" - " // Open Lookup tables\n" - "\n" - " // LUT with the corrected r/z. It is corrected for the average r (z) of the barrel (disk).\n" - " // Includes both coarse r/z position (bin), and finer region each r/z bin is divided into.\n" - " // Indexed using r and z position bits\n" - " static const int* METable = getMETable();\n" - " static const int* TETable = getTETable();\n" - "\n" - " // LUT with phi corrections to project the stub to the average radius in a layer.\n" - " // Only used by layers.\n" - " // Indexed using phi and bend bits\n" - " static const int* phiCorrTable = getPhiCorrTable();\n" - "\n" - " // Masks of which AllStubInner memories that are being used in this phi region; represented by a \"1\"\n" - " // First three bits (LSB) are the six A-F for Barrel, then the three after that are L,M,R for Barrel and disk, last three are L,M,R for Overlap\n" - " // NOTE: read from right to left (OR, OM, OL, BR/DR, BM/DM, BL/DL, BF, BE, BD, BC, BB, BA)\n" - " static const ap_uint maskASI = getAllStubInnerMask();\n" - "\n" - " /////////////////////////\n" - " // Main function\n" - "\n" - " VMRouterCM(\n" - " bx, bx_o,\n" - " // LUTs\n" - " METable,\n" - " TETable,\n" - " phiCorrTable,\n" - " // Input memories\n" - " inputStubs,\n" - + (" inputStubsDisk2S,\n" if disk else " nullptr,\n") +\ - " // AllStub memories\n" - " memoriesAS,\n" - " maskASI,\n" - + (" memoriesASInner,\n" if has_allstub_inner[layerdisk] else " nullptr,\n") +\ - " // ME memories\n" - " memoryME,\n" - " // TEOuter memories\n" - + (" memoriesTEO\n" if has_vmste_outer[layerdisk] else " nullptr\n") +\ - " );\n" - "\n" - " return;\n" - "}\n" - ) - - top_file.close() + with open(output_dir + "/" + file_name + ".cc", "w") as top_file: + + # Write the top function + top_file.write( + "#include \"" + file_name + ".h\"\n\n" +\ + "// VMRouterCM Top Function\n" + "// Sort stubs into smaller regions in phi, i.e. Virtual Modules (VMs).\n" + "\n" + "void %s(\n" % file_name +\ + " const BXType bx, BXType& bx_o,\n" + " // Input memories\n" + " const InputStubMemory inputStubs[numInputs],\n" + + (" const InputStubMemory inputStubsDisk2S[numInputsDisk2S],\n" if disk else "") +\ + " // Output memories\n" + " AllStubMemory memoriesAS[numASCopies],\n" + + (" AllStubInnerMemory memoriesASInner[numASInnerCopies],\n" if has_allstub_inner[layerdisk] else "") +\ + " VMStubMemory *memoryME" + (",\n" if has_vmste_outer[layerdisk] else "") + + (" VMStubMemory memoriesTEO[numTEOCopies]\n" if has_vmste_outer[layerdisk] else "") +\ + " ) {\n" + "\n" + "// Takes 2 clock cycles before one gets data, used at high frequencies\n" + ) + # Write pragmas + for i in range(num_inputs): + top_file.write("#pragma HLS resource variable=inputStubs[%s].get_mem() latency=2\n" % str(i)) + for i in range(num_inputs_disk2s): + top_file.write("#pragma HLS resource variable=inputStubsDisk2S[%s].get_mem() latency=2\n" % str(i)) + + top_file.write( + "#pragma HLS interface register port=bx_o\n" + "\n" + " ///////////////////////////\n" + " // Open Lookup tables for VMRCM\n" + "\n" + " // LUT with the corrected r/z. It is corrected for the average r (z) of the barrel (disk).\n" + " // Includes both coarse r/z position (bin), and finer region each r/z bin is divided into.\n" + " // Indexed using r and z position bits\n" + " static const int* METable = getMETable();\n" + " static const int* TETable = getTETable();\n" + "\n" + " // LUT with phi corrections to project the stub to the average radius in a layer.\n" + " // Only used by layers.\n" + " // Indexed using phi and bend bits\n" + " static const int* phiCorrTable = getPhiCorrTable();\n" + "\n" + " // Masks of which AllStubInner memories that are being used in this phi region; represented by a \"1\"\n" + " // First three bits (LSB) are the six A-F for Barrel, then the three after that are L,M,R for Barrel and disk, last three are L,M,R for Overlap\n" + " // NOTE: read from right to left (OR, OM, OL, BR/DR, BM/DM, BL/DL, BF, BE, BD, BC, BB, BA)\n" + " static const ap_uint maskASI = getAllStubInnerMask();\n" + "\n" + " /////////////////////////\n" + " // Main function\n" + "\n" + " VMRouterCM(\n" + " bx, bx_o,\n" + " // LUTs\n" + " METable,\n" + " TETable,\n" + " phiCorrTable,\n" + " // Input memories\n" + " inputStubs,\n" + + (" inputStubsDisk2S,\n" if disk else " nullptr,\n") +\ + " // AllStub memories\n" + " memoriesAS,\n" + " maskASI,\n" + + (" memoriesASInner,\n" if has_allstub_inner[layerdisk] else " nullptr,\n") +\ + " // ME memories\n" + " memoryME,\n" + " // TEOuter memories\n" + + (" memoriesTEO\n" if has_vmste_outer[layerdisk] else " nullptr\n") +\ + " );\n" + "\n\n" + " return;\n" + "}\n" + ) ############################### -# Main execution - +# Main execution generate_VMRCM +############################### if __name__ == "__main__": parser = argparse.ArgumentParser( @@ -510,23 +502,23 @@ def writeTopFile(vmr, num_inputs, num_inputs_disk2s, output_dir): # Get a list of the Units Under Test if args.all: - vmr_list = getAllVMRs(args.wireconfig) + vmrList = getAllVMRs(args.wireconfig) else: - vmr_list = args.uut - vmr_list.sort() + vmrList = args.uut + vmrList.sort() # Dictionary of all memories sorted by type and Unit Under Test - mem_dict = getDictOfMemories(args.wireconfig, vmr_list) + memDict = getDictOfMemories(args.wireconfig, vmrList) # Loop over all Units Under Test - for vmr in vmr_list: + for aVMR in vmrList: # Check that the Unit Under Test is a VMR - if "VMR" not in vmr: + if "VMR" not in aVMR: raise IndexError("Unit under test has to be a VMR.") # Create and write the files - writeTopHeader(vmr, args.outputdir) - writeTopFile(vmr, len(mem_dict["IL_"+vmr]), len(mem_dict["IL_DISK2S_"+vmr]), args.outputdir) + writeTopHeader(aVMR, args.outputdir) + writeTopFile(aVMR, len(memDict["IL_"+aVMR]), len(memDict["IL_DISK2S_"+aVMR]), args.outputdir) # Write parameters file - writeParameterFile(vmr_list, mem_dict, args.outputdir) + writeParameterFile(vmrList, memDict, args.outputdir) diff --git a/emData/generate_VMSMER.py b/emData/generate_VMSMER.py index d40b3af54fd..5290acc2d7d 100755 --- a/emData/generate_VMSMER.py +++ b/emData/generate_VMSMER.py @@ -7,185 +7,182 @@ # Supports all VMRs, but creates separate top function files foe each VMR specified. import argparse -import collections -# Constants -num_layers = 6 -num_disks = 5 +################################### +# Returns number of allstubs outputs a VMSMER has + +def getNAllStubMem(wireconfig, vmr): + + allstub_count = 0 + + # Open wiring file + with open(wireconfig) as wires_file: + + # Loop over each line in the wiring + for line in wires_file: + module_name = line.split(" ")[-3].split(".")[0] + if module_name == vmr and "AS" in line: + allstub_count+=1 + + + return allstub_count ################################### -# Returns a list of all VMRs in the given wiring +# Returns a list of all VMSMER in the given wiring def getAllVMRs(wireconfig): vmr_list = [] # Open wiring file - wires_file = open(wireconfig) - - # Loop over each line in the wiring - for line in wires_file: - module_name = line.split(" ")[-1].split(".")[0] - # Add module name if not already in vmr_list - if "VMSMER" in module_name and module_name not in vmr_list: - vmr_list.append(module_name) + with open(wireconfig) as wires_file: - wires_file.close() + # Loop over each line in the wiring + for line in wires_file: + module_name = line.split(" ")[-1].split(".")[0] + # Add module name if not already in vmr_list + if "VMSMER" in module_name and module_name not in vmr_list: + vmr_list.append(module_name) return vmr_list ################################# # Writes the VMStubMERouterTop.h file -def writeTopHeader(vmr, output_dir): +def writeTopHeader(vmr, noutcopy, output_dir): # Get layer/disk number and phi region layer = int(vmr.split("_")[1][1] if vmr.split("_")[1][0] == "L" else 0) disk = int(0 if layer else vmr.split("_")[1][1]) - layerdisk = layer-1 if layer else disk+num_layers-1 phi_region = vmr.split("PHI")[1] # Top file name file_name = "VMStubMERouterTop_" + vmr.split("_")[1] - header_file = open(output_dir + "/" + file_name + ".h", "w") - - # Write preamble - header_file.write( - "#ifndef TopFunctions_" + file_name + "_h\n" +\ - "#define TopFunctions_" + file_name + "_h\n" +\ - "\n" - "#include \"VMSMERouter.h\"\n" - "#include \"VMRouterCM_parameters.h\"\n" - "\n" - "// VMStubMERouter Top Function\n" - "// Sort AllStubs into smaller regions in phi, i.e. Virtual Modules (VMs). By writing VMStubME memories.\n" - "\n" - "////////////////////////////////////////////\n" - "// Variables for that are specified with regards to the VMR region\n" - "// Some are used by the Test Bench\n" - "\n" - ) - - # Write the configuration - header_file.write( - "#define kLAYER " + str(layer) + " // Which barrel layer number the data is coming from\n" - "#define kDISK " + str(disk) + " // Which disk number the data is coming from, 0 if not disk\n" - "constexpr TF::phiRegion phiRegion = TF::" + phi_region+ "; // Which AllStub/PhiRegion\n" - "\n" - "constexpr TF::layerDisk layerdisk = static_cast((kLAYER) ? kLAYER-1 : trklet::N_LAYER+kDISK-1);\n" - "constexpr regionType inType = (kDISK ==0) ? getInputType() : DISKPS;\n" - "constexpr regionType outType = (kDISK ==0) ? getInputType() : DISK;\n" - "// Number of bits for the RZ bins \n" - "constexpr int kNbitsrzbinME = kNbitsrzbin%s; // For the VMSME memories\n" % ("MELayer" if layer else "MEDisk") +\ - "\n\n" - ) - - # Write the top function - header_file.write( - "/////////////////////////////////////////////////////\n" - "// VMStubMERouter Top Function \n" - "\n" - "void %s(const BXType bx, BXType& bx_o,\n" % file_name +\ - " // Input memories\n" - " AllStub& allStub,\n" - " // Output memories\n" - " VMStubMemory *memoryME,\n" - " AllStubMemory& memoriesAS,\n" - " // Index of AllStub\n" - " unsigned int index,\n" - " // Bool if valid stub\n" - " bool valid\n" - " );\n" - "\n" - "#endif // TopFunctions_%s_h\n" % file_name - ) - - header_file.close() - + with open(output_dir + "/" + file_name + ".h", "w") as header_file: + + # Write preamble + header_file.write( + "#ifndef TopFunctions_" + file_name + "_h\n" +\ + "#define TopFunctions_" + file_name + "_h\n" +\ + "\n" + "#include \"VMSMERouter.h\"\n" + "#include \"VMRouterCM_parameters.h\"\n" + "\n" + "// VMStubMERouter Top Function\n" + "// Sort AllStubs into smaller regions in phi, i.e. Virtual Modules (VMs). By writing VMStubME memories.\n" + "\n" + "////////////////////////////////////////////\n" + "// Variables for that are specified with regards to the VMSMER region\n" + "// Some are used by the Test Bench\n" + "\n" + ) + + # Write the configuration + header_file.write( + "#define kLAYER " + str(layer) + " // Which barrel layer number the data is coming from\n" + "#define kDISK " + str(disk) + " // Which disk number the data is coming from, 0 if not disk\n" + "#define NOutCopy " + str(noutcopy) + " // Numberof copies of AS and VMSMER memories (assumed to be the same)\n" + "constexpr TF::phiRegion phiRegion = TF::" + phi_region+ "; // Which AllStub/PhiRegion\n" + "\n" + "constexpr TF::layerDisk layerdisk = static_cast((kLAYER) ? kLAYER-1 : trklet::N_LAYER+kDISK-1);\n" + "constexpr regionType inType = (kDISK ==0) ? getInputType() : DISKPS;\n" + "constexpr regionType outType = (kDISK ==0) ? getInputType() : DISK;\n" + "// Number of bits for the RZ bins used but VMSMER\n" + "constexpr int kNbitsrzbinME = kNbitsrzbin%s; // For the VMSME memories\n" % ("MELayer" if layer else "MEDisk") +\ + "\n\n" + ) + + # Write the top function for VMStubMERouter + header_file.write( + "/////////////////////////////////////////////////////\n" + "// VMStubMERouter Top Function \n" + "\n" + "void %s(const BXType bx, BXType& bx_o,\n" % file_name +\ + " // Input memories\n" + " AllStub& allStub,\n" + " // Output memories\n" + " VMStubMemory memoryME[NOutCopy],\n" + " AllStubMemory memoriesAS[NOutCopy],\n" + " // Index of AllStub\n" + " unsigned int index,\n" + " // Bool if valid stub\n" + " bool valid\n" + " );\n" + "\n" + "#endif // TopFunctions_%s_h\n" % file_name + ) # Writes the VMRouterCMTop.cc file def writeTopFile(vmr, output_dir): - # Get layer/disk number - layer = int(vmr.split("_")[1][1] if vmr.split("_")[1][0] == "L" else 0) - disk = int(0 if layer else vmr.split("_")[1][1]) - layerdisk = layer-1 if layer else disk+num_layers-1 - - LD = "" - # Top file name file_name = "VMStubMERouterTop_" + vmr.split("_")[1] - top_file = open(output_dir + "/" + file_name + ".cc", "w") - - # Write the top function - top_file.write( - "#include \"" + file_name + ".h\"\n\n" +\ - "// VMStubMERouter Top Function\n" - "// Sort AllStubs into smaller regions in phi, i.e. Virtual Modules (VMs). By writing VMStubME memories.\n" - "\n" - "void %s(\n" % file_name +\ - " const BXType bx, BXType& bx_o,\n" - " // Input memories\n" - " AllStub& allStub,\n" - " // Output memories\n" - " VMStubMemory *memoryME,\n" - " AllStubMemory& memoriesAS,\n" - " // Index of AllStub\n" - " unsigned int index,\n" - " // Bool if valid stub\n" - " bool valid\n" - " ) {\n" - "\n" - "// Takes 2 clock cycles before one gets data, used at high frequencies\n" - ) - - top_file.write( - "#pragma HLS interface ap_ctrl_none port=return\n" - "#pragma HLS pipeline II=1\n" -# "#pragma HLS interface register port=bx_o\n" - "\n" - " ///////////////////////////\n" - " // Open Lookup tables\n" - "\n" - " // LUT with the corrected r/z. It is corrected for the average r (z) of the barrel (disk).\n" - " // Includes both coarse r/z position (bin), and finer region each r/z bin is divided into.\n" - " // Indexed using r and z position bits\n" - " static const int* METable = getMETable();\n" - "\n" - " // LUT with phi corrections to project the stub to the average radius in a layer.\n" - " // Only used by layers.\n" - " // Indexed using phi and bend bits\n" - " static const int* phiCorrTable = getPhiCorrTable();\n" - "\n" - " /////////////////////////\n" - " // Main function\n" - "\n" - " VMSMERouter%s(\n" %LD +\ - " bx, bx_o,\n" - " // LUTs\n" - " METable,\n" - " phiCorrTable,\n" - " // Input memories\n" - " allStub,\n" - " // Output memories\n" - " memoryME,\n" - " memoriesAS,\n" - " // Index of AllStub\n" - " index,\n" - " valid\n" - " );\n" - "\n" - " return;\n" - "}\n" - ) - - top_file.close() - + with open(output_dir + "/" + file_name + ".cc", "w") as top_file: + + # Write the top function + top_file.write( + "#include \"" + file_name + ".h\"\n\n" +\ + "// VMStubMERouter Top Function\n" + "// Sort AllStubs into smaller regions in phi, i.e. Virtual Modules (VMs). By writing VMStubME memories.\n" + "\n" + "void %s(\n" % file_name +\ + " const BXType bx, BXType& bx_o,\n" + " // Input memories\n" + " AllStub& allStub,\n" + " // Output memories\n" + " VMStubMemory memoryME[NOutCopy],\n" + " AllStubMemory memoriesAS[NOutCopy],\n" + " // Index of AllStub\n" + " unsigned int index,\n" + " // Bool if valid stub\n" + " bool valid\n" + " ) {\n" + "\n" + "// Takes 2 clock cycles before one gets data, used at high frequencies\n" + ) + + top_file.write( + "#pragma HLS interface ap_ctrl_none port=return\n" + "#pragma HLS pipeline II=1\n" + "\n" + " ///////////////////////////\n" + " // Open Lookup tables\n" + "\n" + " // LUT with the corrected r/z for VMSMER. It is corrected for the average r (z) of the barrel (disk).\n" + " // Includes both coarse r/z position (bin), and finer region each r/z bin is divided into.\n" + " // Indexed using r and z position bits\n" + " static const int* METable = getMETable();\n" + "\n" + " // LUT with phi corrections for VMSMER to project the stub to the average radius in a layer.\n" + " // Only used by layers.\n" + " // Indexed using phi and bend bits\n" + " static const int* phiCorrTable = getPhiCorrTable();\n" + "\n" + " /////////////////////////\n" + " // Main function\n" + "\n" + " VMSMERouter(\n" + " bx, bx_o,\n" + " // LUTs\n" + " METable,\n" + " phiCorrTable,\n" + " // Input memories\n" + " allStub,\n" + " // Output memories\n" + " memoryME,\n" + " memoriesAS,\n" + " // Index of AllStub\n" + " index,\n" + " valid\n" + " );\n\n" + " return;\n" + "}\n\n" + ) ############################### -# Main execution +# Main execution generate_VMSMER if __name__ == "__main__": @@ -213,17 +210,19 @@ def writeTopFile(vmr, output_dir): # Get a list of the Units Under Test if args.all: - vmr_list = getAllVMRs(args.wireconfig) + vmrList = getAllVMRs(args.wireconfig) else: - vmr_list = args.uut - vmr_list.sort() + vmrList = args.uut + vmrList.sort() # Loop over all Units Under Test - for vmr in vmr_list: + for aVMR in vmrList: # Check that the Unit Under Test is a VMR - if "VMSMER" not in vmr: + if "VMSMER" not in aVMR: raise IndexError("Unit under test has to be a VMSMER.") + nallstubmem = getNAllStubMem(args.wireconfig, aVMR) + # Create and write the files - writeTopHeader(vmr, args.outputdir) - writeTopFile(vmr, args.outputdir) + writeTopHeader(aVMR, nallstubmem, args.outputdir) + writeTopFile(aVMR, args.outputdir) diff --git a/emData/project_generation_scripts b/emData/project_generation_scripts index 91256ad3c11..53fc560b9e7 160000 --- a/emData/project_generation_scripts +++ b/emData/project_generation_scripts @@ -1 +1 @@ -Subproject commit 91256ad3c11e5322fa019a484a4f7781756db9fe +Subproject commit 53fc560b9e736b63b8730e4cb8586e7500c1af58 diff --git a/project/script_IR.tcl b/project/script_IR.tcl index 150ebb97a56..452557e4a00 100644 --- a/project/script_IR.tcl +++ b/project/script_IR.tcl @@ -34,31 +34,32 @@ array set modules_to_test { 35 {2S_6_B} } -# 12 {negPS10G_1_A} -# 13 {negPS10G_1_B} -# 14 {negPS10G_2_A} -# 15 {negPS10G_2_B} -# 16 {negPS10G_3_A} -# 17 {negPS10G_3_B} -# 18 {negPS10G_4_A} -# 19 {negPS10G_4_B} -# 20 {negPS_1_A} -# 21 {negPS_1_B} -# 22 {negPS_2_A} -# 23 {negPS_2_B} - -# 36 {neg2S_1_A} -# 37 {neg2S_1_B} -# 38 {neg2S_2_A} -# 39 {neg2S_2_B} -# 40 {neg2S_3_A} -# 41 {neg2S_3_B} -# 42 {neg2S_4_A} -# 43 {neg2S_4_B} -# 44 {neg2S_5_A} -# 45 {neg2S_5_B} -# 46 {neg2S_6_A} -# 47 {neg2S_6_B} + #12 {negPS10G_1_A} + #13 {negPS10G_1_B} + #14 {negPS10G_2_A} + #15 {negPS10G_2_B} + #16 {negPS10G_3_A} + #17 {negPS10G_3_B} + #18 {negPS10G_4_A} + #19 {negPS10G_4_B} + #20 {negPS_1_A} + #21 {negPS_1_B} + #22 {negPS_2_A} + #23 {negPS_2_B} + + #36 {neg2S_1_A} + #37 {neg2S_1_B} + #38 {neg2S_2_A} + #39 {neg2S_2_B} + #40 {neg2S_3_A} + #41 {neg2S_3_B} + #42 {neg2S_4_A} + #43 {neg2S_4_B} + #44 {neg2S_5_A} + #45 {neg2S_5_B} + #46 {neg2S_6_A} + #47 {neg2S_6_B} + # module_to_export must correspond to the default macros set at the top of the # test bench; otherwise, the C/RTL cosimulation will fail diff --git a/project/script_MP.tcl b/project/script_MP.tcl index 8536b95bf81..f2039a60b41 100644 --- a/project/script_MP.tcl +++ b/project/script_MP.tcl @@ -31,6 +31,21 @@ set modules_to_test { {MP_D5PHIC} } +#Add these if using extra MPs +# {MP_L3PHIB_E} +# {MP_L4PHIB_E} +# {MP_L5PHIB_E} +# {MP_L6PHIB_E} +# {MP_D3PHIB_E} +# {MP_D4PHIB_E} +# {MP_L3PHIC_E} +# {MP_L4PHIC_E} +# {MP_L5PHIC_E} +# {MP_L6PHIC_E} +# {MP_D3PHIC_E} +# {MP_D4PHIC_E} + + # module_to_export must correspond to the default macros set at the top of the # test bench; otherwise, the C/RTL cosimulation will fail set module_to_export MP_D1PHIC @@ -48,8 +63,9 @@ add_files -tb ../emData/MP/ foreach i $modules_to_test { set layerDisk [string range $i 3 4] - set iMP [string range $i 8 9] - set top_func [join [list "MatchProcessor_" $layerDisk "PHI" $iMP] ""] + set iMP [string range $i 8 8] + set extra [string range $i 9 10] + set top_func [join [list "MatchProcessor_" $layerDisk "PHI" $iMP $extra] ""] puts [join [list "======== TESTING " $i " ========"] ""] puts [join [list "layerDisk = " $layerDisk] ""] puts [join [list "iMP = " $iMP] ""] diff --git a/project/script_TB.tcl b/project/script_TB.tcl index ff7064ea036..04ed042543d 100644 --- a/project/script_TB.tcl +++ b/project/script_TB.tcl @@ -9,18 +9,12 @@ source env_hls.tcl # FIXME: FT_D1D2 is excluded for now because it currently produces extra # entries compared to the emulation set modules_to_test { - {FT_L1L2} - {FT_L2L3} - {FT_L3L4} - {FT_L5L6} - {FT_D1D2} - {FT_D3D4} - {FT_L1D1} - {FT_L2D1} + {TB_AAAA} + {TB_BBBB} } # module_to_export must correspond to the default macros set at the top of the # test bench; otherwise, the C/RTL cosimulation will fail -set module_to_export FT_L1L2 +set module_to_export TB_AAAA # create new project (deleting any existing one of same name) open_project -reset trackBuilder @@ -31,7 +25,7 @@ add_files ../TopFunctions/CombinedConfig_FPGA2/TrackBuilderTop.cc -cflags "$CFLA add_files -tb ../TestBenches/TrackBuilder_test.cpp -cflags "$CFLAGS" # data files -add_files -tb ../emData/FT/ +add_files -tb ../emData/TB/ foreach i $modules_to_test { puts [join [list "======== TESTING " $i " ========"] ""]