rs, sys: bump capstone to 6.0.0-Alpha5

Author: jiegec

CHANGELOG.md

@@ -28,7 +28,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 ### Changed
 - `InsnDetail::regs_read()`/`InsnDetail::regs_write()` return more of the accessed registers
-- Bump bundled capstone to 6.0.0-Alpha4
+- Bump bundled capstone to 6.0.0-Alpha5
 - Rename ARM64 to AARCH64, SYSZ to SYSTEMZ to follow upstream changes
 - AArch64 support is rewritten to follow upstream changes
 - Endian must be specified for Sparc/SystemZ, since little endian support is added

capstone-sys/CHANGELOG.md

@@ -19,7 +19,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Rename ARM64 to AARCH64, SYSZ to SYSTEMZ to follow upstream changes
 
 ### Changed
-- Bump bundled capstone to 6.0.0-Alpha4
+- Bump bundled capstone to 6.0.0-Alpha5
 - Change `cs_regs_access()` `regs_read`/`regs_write` args to take `*mut cs_regs` (instead of `*mut u16`)
     - makes it more clear that args should be fixed size arrays
 

capstone-sys/capstone/.github/workflows/build-wheels-publish.yml

@@ -63,7 +63,7 @@ jobs:
           # windows - x86
           # - { os: windows-latest, arch: x86, cibw_build: 'cp*', cibw_skip: '*36* *37*' }
           # windows - arm64
-          - { os: windows-latest, arch: ARM64, cibw_build: 'cp*', cibw_skip: '*36* *37* *38*' }
+          - { os: windows-11-arm, arch: ARM64, cibw_build: 'cp*', cibw_skip: '*36* *37* *38* *39* *310*' }
 
     steps:
       - uses: actions/checkout@v4
@@ -106,17 +106,16 @@ jobs:
         uses: docker/setup-qemu-action@v3
 
       - name: '🚧 cibuildwheel run'
-        uses: pypa/cibuildwheel@v2.23.3
+        uses: pypa/cibuildwheel@v3.0.1
         env:
           CIBW_BUILD_FRONTEND: build
           CIBW_BUILD: ${{ matrix.cibw_build }}
           CIBW_SKIP: ${{ matrix.cibw_skip }}
           CIBW_ARCHS: ${{ matrix.arch }}
           CIBW_ENVIRONMENT: DEBUG=${{ env.CAPSTONE_DEBUG }}
           CIBW_ENVIRONMENT_PASS_LINUX: DEBUG
-          # https://cibuildwheel.pypa.io/en/stable/faq/#windows-arm64
           # https://github.com/pypa/cibuildwheel/pull/1169
-          CIBW_TEST_SKIP: "*-win_arm64 cp38-macosx_*:arm64"
+          CIBW_TEST_SKIP: "cp38-macosx_*:arm64"
           CIBW_TEST_COMMAND: >
             python -m pip install {package}/cstest_py &&
             python {project}/suite/run_tests.py

capstone-sys/capstone/ChangeLog

@@ -1,5 +1,49 @@
 This file details the changelog of Capstone.
 
+-----------------------------
+Version 6.0.0-Alpha5: August 3rd, 2025
+
+## What's Changed
+* Apple AArch64 proprietary by @Rot127 in https://github.com/capstone-engine/capstone/pull/2692
+* Add jump group for generic jirl by @jiegec in https://github.com/capstone-engine/capstone/pull/2698
+* LoongArch: Compute absolute address for address operand by @jiegec in https://github.com/capstone-engine/capstone/pull/2699
+* Fix LoongArch ld/st instructions register info by @jiegec in https://github.com/capstone-engine/capstone/pull/2701
+* ARM: fix typo, cspr -> cpsr by @jiegec in https://github.com/capstone-engine/capstone/pull/2716
+* Fix arm pop reg access by @jiegec in https://github.com/capstone-engine/capstone/pull/2718
+* Fix missing sp register read in ret instruction by @jiegec in https://github.com/capstone-engine/capstone/pull/2719
+* Fix missing operand for smstart, due to space replaced by tab by @jiegec in https://github.com/capstone-engine/capstone/pull/2720
+* Add flag for the SoftFail case of the LLVM disassembler. by @Rot127 in https://github.com/capstone-engine/capstone/pull/2707
+* Remove unused files. by @Rot127 in https://github.com/capstone-engine/capstone/pull/2709
+* clang-format: change license to BSD-3-Clause by @tmfink in https://github.com/capstone-engine/capstone/pull/2724
+* Use cs_ac_type for operand access mode in all arches and use cs_xtensa_op_type for Xtensa operand type by @jiegec in https://github.com/capstone-engine/capstone/pull/2721
+* Make SStream respect the CS_OPT_UNSIGNED flag. by @Rot127 in https://github.com/capstone-engine/capstone/pull/2723
+* Make assertion hit warnings optional in release builds. by @Rot127 in https://github.com/capstone-engine/capstone/pull/2729
+* Update source list before installing valgrind. by @Rot127 in https://github.com/capstone-engine/capstone/pull/2730
+* Add x30 implicit read to the RET alias. by @Rot127 in https://github.com/capstone-engine/capstone/pull/2739
+* Print immediate only memory operands for AArch64. by @Rot127 in https://github.com/capstone-engine/capstone/pull/2732
+* Add warning about naive search and replace to patch reg names. by @Rot127 in https://github.com/capstone-engine/capstone/pull/2728
+* Enable to generate legacy MC tests for the fuzzer. by @Rot127 in https://github.com/capstone-engine/capstone/pull/2733
+* Auto-Sync update Sparc LLVM-18 by @Rot127 in https://github.com/capstone-engine/capstone/pull/2704
+* Python binding: Use ABI3 wheels by @Antelox in https://github.com/capstone-engine/capstone/pull/2742
+* Update Auto-Sync to Python 3.13 and tree-sitter-py 24.0 by @Rot127 in https://github.com/capstone-engine/capstone/pull/2705
+* Fix for Risc-V C.SRLI decoding (issue #2731) by @h01G3r in https://github.com/capstone-engine/capstone/pull/2745
+* HPPA fix mem operands access and instruction printing by @R33v0LT in https://github.com/capstone-engine/capstone/pull/2746
+* Handle zero case of R1 operand field by @Rot127 in https://github.com/capstone-engine/capstone/pull/2743
+* Fix comisd memory operand size: xmmword -> qword by @jiegec in https://github.com/capstone-engine/capstone/pull/2750
+* Fix missing repne for movsd op by @jiegec in https://github.com/capstone-engine/capstone/pull/2752
+* Explain more details about CC change. by @Rot127 in https://github.com/capstone-engine/capstone/pull/2753
+* Add a test for FCC conditions for none FPU instructions. by @Rot127 in https://github.com/capstone-engine/capstone/pull/2758
+* Print register access type and registers accessed in cstool_mips.c by @jiegec in https://github.com/capstone-engine/capstone/pull/2762
+* Fix duplication of memory operand by @Rot127 in https://github.com/capstone-engine/capstone/pull/2761
+* Python binding: Windows ARM64 build by @Antelox in https://github.com/capstone-engine/capstone/pull/2760
+* Implement cs_regs_access for Alpha architecture by @jiegec in https://github.com/capstone-engine/capstone/pull/2763
+* Fix decoding of the FCC fields of FBPcc (format 2_3). by @Rot127 in https://github.com/capstone-engine/capstone/pull/2764
+
+## New Contributors
+* @h01G3r made their first contribution in https://github.com/capstone-engine/capstone/pull/2745
+
+**Full Changelog**: https://github.com/capstone-engine/capstone/compare/6.0.0-Alpha4...6.0.0-Alpha5
+
 -----------------------------
 Version 6.0.0-Alpha4: April 11th, 2025
 

capstone-sys/capstone/Mapping.c

@@ -331,31 +331,31 @@ const cs_ac_type mapping_get_op_access(MCInst *MI, unsigned OpNum,
 }
 
 /// Returns the operand at detail->arch.operands[op_count + offset]
-/// Or NULL if detail is not set.
-#define DEFINE_get_detail_op(arch, ARCH) \
+/// Or NULL if detail is not set or the offset would be out of bounds.
+#define DEFINE_get_detail_op(arch, ARCH, ARCH_UPPER) \
 	cs_##arch##_op *ARCH##_get_detail_op(MCInst *MI, int offset) \
 	{ \
 		if (!MI->flat_insn->detail) \
 			return NULL; \
 		int OpIdx = MI->flat_insn->detail->arch.op_count + offset; \
-		assert(OpIdx >= 0 && OpIdx < MAX_MC_OPS); \
+		if (OpIdx < 0 || OpIdx >= NUM_##ARCH_UPPER##_OPS) { return NULL; } \
 		return &MI->flat_insn->detail->arch.operands[OpIdx]; \
 	}
 
-DEFINE_get_detail_op(arm, ARM);
-DEFINE_get_detail_op(ppc, PPC);
-DEFINE_get_detail_op(tricore, TriCore);
-DEFINE_get_detail_op(aarch64, AArch64);
-DEFINE_get_detail_op(alpha, Alpha);
-DEFINE_get_detail_op(hppa, HPPA);
-DEFINE_get_detail_op(loongarch, LoongArch);
-DEFINE_get_detail_op(mips, Mips);
-DEFINE_get_detail_op(riscv, RISCV);
-DEFINE_get_detail_op(systemz, SystemZ);
-DEFINE_get_detail_op(xtensa, Xtensa);
-DEFINE_get_detail_op(bpf, BPF);
-DEFINE_get_detail_op(arc, ARC);
-DEFINE_get_detail_op(sparc, Sparc);
+DEFINE_get_detail_op(arm, ARM, ARM);
+DEFINE_get_detail_op(ppc, PPC, PPC);
+DEFINE_get_detail_op(tricore, TriCore, TRICORE);
+DEFINE_get_detail_op(aarch64, AArch64, AARCH64);
+DEFINE_get_detail_op(alpha, Alpha, ALPHA);
+DEFINE_get_detail_op(hppa, HPPA, HPPA);
+DEFINE_get_detail_op(loongarch, LoongArch, LOONGARCH);
+DEFINE_get_detail_op(mips, Mips, MIPS);
+DEFINE_get_detail_op(riscv, RISCV, RISCV);
+DEFINE_get_detail_op(systemz, SystemZ, SYSTEMZ);
+DEFINE_get_detail_op(xtensa, Xtensa, XTENSA);
+DEFINE_get_detail_op(bpf, BPF, BPF);
+DEFINE_get_detail_op(arc, ARC, ARC);
+DEFINE_get_detail_op(sparc, Sparc, SPARC);
 
 /// Returns true if for this architecture the
 /// alias operands should be filled.

capstone-sys/capstone/arch/Alpha/AlphaMapping.c

@@ -182,4 +182,48 @@ bool Alpha_getInstruction(csh handle, const uint8_t *code,
 	return Result != MCDisassembler_Fail;
 }
 
+#ifndef CAPSTONE_DIET
+void Alpha_reg_access(const cs_insn *insn, cs_regs regs_read,
+			  uint8_t *regs_read_count, cs_regs regs_write,
+			  uint8_t *regs_write_count)
+{
+	uint8_t i;
+	uint8_t read_count, write_count;
+	cs_alpha *alpha = &(insn->detail->alpha);
+
+	read_count = insn->detail->regs_read_count;
+	write_count = insn->detail->regs_write_count;
+
+	// implicit registers
+	memcpy(regs_read, insn->detail->regs_read,
+	       read_count * sizeof(insn->detail->regs_read[0]));
+	memcpy(regs_write, insn->detail->regs_write,
+	       write_count * sizeof(insn->detail->regs_write[0]));
+
+	// explicit registers
+	for (i = 0; i < alpha->op_count; i++) {
+		cs_alpha_op *op = &(alpha->operands[i]);
+		switch ((int)op->type) {
+		case ALPHA_OP_REG:
+			if ((op->access & CS_AC_READ) &&
+			    !arr_exist(regs_read, read_count, op->reg)) {
+				regs_read[read_count] = (uint16_t)op->reg;
+				read_count++;
+			}
+			if ((op->access & CS_AC_WRITE) &&
+			    !arr_exist(regs_write, write_count, op->reg)) {
+				regs_write[write_count] = (uint16_t)op->reg;
+				write_count++;
+			}
+			break;
+		default:
+			break;
+		}
+	}
+
+	*regs_read_count = read_count;
+	*regs_write_count = write_count;
+}
+#endif
+
 #endif

capstone-sys/capstone/arch/Alpha/AlphaMapping.h

@@ -32,4 +32,8 @@ void Alpha_set_detail_op_imm(MCInst *MI, unsigned OpNum, alpha_op_type ImmType,
 							 int64_t Imm);
 void Alpha_set_detail_op_reg(MCInst *MI, unsigned OpNum, alpha_op_type Reg);
 
+void Alpha_reg_access(const cs_insn *insn, cs_regs regs_read,
+			uint8_t *regs_read_count, cs_regs regs_write,
+			uint8_t *regs_write_count);
+
 #endif

capstone-sys/capstone/arch/Alpha/AlphaModule.c

@@ -26,6 +26,9 @@ cs_err ALPHA_global_init(cs_struct *ud)
 	ud->insn_id = Alpha_get_insn_id;
 	ud->insn_name = Alpha_insn_name;
 	ud->group_name = Alpha_group_name;
+#ifndef CAPSTONE_DIET
+	ud->reg_access = Alpha_reg_access;
+#endif
 
 	return CS_ERR_OK;
 }

capstone-sys/capstone/arch/Mips/MipsMapping.c

@@ -303,7 +303,7 @@ static void Mips_set_detail_op_reg(MCInst *MI, unsigned OpNum, mips_reg Reg,
 		return;
 	}
 
-	CS_ASSERT((map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_REG);
+	CS_ASSERT(is_reglist || (map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_REG);
 	Mips_get_detail_op(MI, 0)->type = MIPS_OP_REG;
 	Mips_get_detail_op(MI, 0)->reg = Reg;
 	Mips_get_detail_op(MI, 0)->is_reglist = is_reglist;
@@ -319,8 +319,19 @@ static void Mips_set_detail_op_operand(MCInst *MI, unsigned OpNum)
 		Mips_set_detail_op_imm(MI, OpNum, value);
 	} else if (op_type == CS_OP_REG) {
 		Mips_set_detail_op_reg(MI, OpNum, value, false);
-	} else
-		printf("Operand type %d not handled!\n", op_type);
+	} else {
+		// Register list which ends with a memory operand
+		// Gives very large MCInst operand numbers but don't
+		// have the respective Capstone type in the mapping table.
+		if (MCOperand_isImm(MCInst_getOperand(MI, OpNum))) {
+			Mips_get_detail_op(MI, 0)->type = MIPS_OP_MEM;
+			Mips_get_detail_op(MI, 0)->mem.disp = value;
+		} else if (MCOperand_isReg(MCInst_getOperand(MI, OpNum))) {
+			Mips_get_detail_op(MI, 0)->mem.base = value;
+		} else {
+			printf("Operand type %d not handled!\n", op_type);
+		}
+	}
 }
 
 static void Mips_set_detail_op_jump(MCInst *MI, unsigned OpNum)

capstone-sys/capstone/arch/Sparc/SparcMapping.c

@@ -66,7 +66,12 @@ static void Sparc_add_bit_details(MCInst *MI, const uint8_t *Bytes,
 		break;
 	}
 	case SPARC_INSN_FORM_F2_3:
-		detail->cc_field = 0x4 | get_insn_field_r(insn, 20, 21);
+		detail->cc_field = get_insn_field_r(insn, 20, 21);
+		if (get_insn_field_r(insn, 22, 24) == 1) {
+			// BPcc and FBPcc encode their fields in two bits.
+			// BPcc needs the upper bit set to match our CC field enum.
+			detail->cc_field |= 0x4;
+		}
 		break;
 	case SPARC_INSN_FORM_TRAPSP:
 		detail->cc_field = 0x4 | get_insn_field_r(insn, 11, 12);
@@ -400,6 +405,10 @@ static inline bool is_single_reg_mem_case(MCInst *MI, unsigned OpNo)
 	if (map_get_op_type(MI, OpNo) != CS_OP_MEM_REG) {
 		return false;
 	}
+	cs_sparc_op *prev_op = Sparc_get_detail_op(MI, -1);
+	if (prev_op && prev_op->type == SPARC_OP_MEM) {
+		return false;
+	}
 	if (MI->size == 1) {
 		return true;
 	} else if (MI->size > OpNo + 1 && Sparc_get_detail(MI)->operands[0].type != SPARC_OP_MEM) {
@@ -450,6 +459,11 @@ void Sparc_add_cs_detail_0(MCInst *MI, sparc_op_group op_group, unsigned OpNo)
 		break;
 	}
 	case Sparc_OP_GROUP_MemOperand: {
+		cs_sparc_op *prev_op = Sparc_get_detail_op(MI, -1);
+		if (prev_op && prev_op->type == SPARC_OP_MEM) {
+			// Already added.
+			break;
+		}
 		MCOperand *Op1 = MCInst_getOperand(MI, (OpNo));
 		MCOperand *Op2 = MCInst_getOperand(MI, (OpNo + 1));
 		if (!MCOperand_isReg(Op1) ||