diff --git a/__init__.py b/pyreil/__init__.py similarity index 95% rename from __init__.py rename to pyreil/__init__.py index 1fb5760..2035ea6 100644 --- a/__init__.py +++ b/pyreil/__init__.py @@ -25,4 +25,5 @@ http://www.zynamics.com/binnavi/manual/html/reil_language.htm """ -from reil.definitions import * \ No newline at end of file +from pyreil import x86 +from pyreil import native diff --git a/definitions.py b/pyreil/definitions.py similarity index 99% rename from definitions.py rename to pyreil/definitions.py index 798c743..4343fd3 100644 --- a/definitions.py +++ b/pyreil/definitions.py @@ -14,7 +14,7 @@ # See the License for the specific language governing permissions and # limitations under the License. -"""reil.definitions +"""pyreil.definitions This module contains the basic definitions for the REIL instructions that are used by this library. diff --git a/error.py b/pyreil/error.py similarity index 97% rename from error.py rename to pyreil/error.py index cab2309..558f8e3 100644 --- a/error.py +++ b/pyreil/error.py @@ -15,7 +15,7 @@ # limitations under the License. """ -reil.error +pyreil.error This module contains exception definitions for various generic error conditions that can occur during translation. @@ -28,4 +28,4 @@ class TranslationError(Exception): class IllegalInstruction(Exception): - pass \ No newline at end of file + pass diff --git a/native.py b/pyreil/native.py similarity index 96% rename from native.py rename to pyreil/native.py index cb30d93..dde8758 100644 --- a/native.py +++ b/pyreil/native.py @@ -14,7 +14,7 @@ # See the License for the specific language governing permissions and # limitations under the License. -"""reil.native +"""pyreil.native This module contains the basic definitions for the native instructions produced by this library. @@ -35,4 +35,4 @@ def __init__(self, address, mnemonic, il_instructions, ends_basic_block=False, s self.size = size def __str__(self): - return '{:08x} {:1} {}'.format(self.address, self.ends_basic_block, self.mnemonic) \ No newline at end of file + return '{:08x} {:1} {}'.format(self.address, self.ends_basic_block, self.mnemonic) diff --git a/shorthand.py b/pyreil/shorthand.py similarity index 98% rename from shorthand.py rename to pyreil/shorthand.py index 8c42890..b5c9cd5 100644 --- a/shorthand.py +++ b/pyreil/shorthand.py @@ -14,14 +14,14 @@ # See the License for the specific language governing permissions and # limitations under the License. -"""reil.shorthand +"""pyreil.shorthand This module contains shorthand functions for creating various REIL instructions and operands. """ -import reil.definitions as reil +import pyreil.definitions as reil def imm(value, size): @@ -319,4 +319,4 @@ def sys_(input0=None): first input operand. """ - return reil.Instruction(reil.SYS, input0, None, None) \ No newline at end of file + return reil.Instruction(reil.SYS, input0, None, None) diff --git a/x86/__init__.py b/pyreil/x86/__init__.py similarity index 92% rename from x86/__init__.py rename to pyreil/x86/__init__.py index 14cb151..b4771f1 100644 --- a/x86/__init__.py +++ b/pyreil/x86/__init__.py @@ -14,7 +14,7 @@ # See the License for the specific language governing permissions and # limitations under the License. -"""reil.x86 - x86 and x86_64 translators +"""pyreil.x86 - x86 and x86_64 translators This module generates REIL (reverse engineering intermediate language) IL from x86 and x86_64 machine code. @@ -26,4 +26,6 @@ http://www.intel.com/content/dam/www/public/us/en/documents/manuals /64-ia-32-architectures-software-developer-instruction-set-reference -manual-325383.pdf -""" \ No newline at end of file +""" + +from pyreil.x86.translator import translate diff --git a/x86/arithmetic.py b/pyreil/x86/arithmetic.py similarity index 98% rename from x86/arithmetic.py rename to pyreil/x86/arithmetic.py index 00f0b4f..194ea48 100644 --- a/x86/arithmetic.py +++ b/pyreil/x86/arithmetic.py @@ -14,7 +14,7 @@ # See the License for the specific language governing permissions and # limitations under the License. -"""reil.x86.arithmetic - x86 and x86_64 translators +"""pyreil.x86.arithmetic - x86 and x86_64 translators This module generates REIL (reverse engineering intermediate language) IL from x86 and x86_64 machine code. @@ -23,13 +23,11 @@ such as add, mul, div """ -import reil.error -from reil.shorthand import * - -import reil.x86.conditional as conditional -import reil.x86.operand as operand -from reil.x86.utilities import * +from pyreil.shorthand import * +from pyreil.x86 import operand +from pyreil.x86 import conditional +from pyreil.x86.utilities import * # Helpers diff --git a/x86/bitwise.py b/pyreil/x86/bitwise.py similarity index 97% rename from x86/bitwise.py rename to pyreil/x86/bitwise.py index bd580f9..10b5e60 100644 --- a/x86/bitwise.py +++ b/pyreil/x86/bitwise.py @@ -14,7 +14,7 @@ # See the License for the specific language governing permissions and # limitations under the License. -"""reil.x86.bitwise - x86 and x86_64 translators +"""pyreil.x86.bitwise - x86 and x86_64 translators This module generates REIL (reverse engineering intermediate language) IL from x86 and x86_64 machine code. @@ -23,16 +23,15 @@ all about twiddling bits and bytes """ + import capstone import capstone.x86 -import reil -import reil.error -from reil.shorthand import * +from pyreil.shorthand import * -import reil.x86.conditional as conditional -import reil.x86.operand as operand -from reil.x86.utilities import * +from pyreil.x86 import operand +from pyreil.x86 import conditional +from pyreil.x86.utilities import * def _shift_set_flags(ctx, result): @@ -416,4 +415,4 @@ def x86_shrd(ctx, i): _shift_set_flags(ctx, result) - operand.set(ctx, i, 0, result) \ No newline at end of file + operand.set(ctx, i, 0, result) diff --git a/x86/conditional.py b/pyreil/x86/conditional.py similarity index 98% rename from x86/conditional.py rename to pyreil/x86/conditional.py index c28bff8..4254503 100644 --- a/x86/conditional.py +++ b/pyreil/x86/conditional.py @@ -22,7 +22,7 @@ This file contains helpers for x86 conditional instructions """ -from reil.shorthand import * +from pyreil.shorthand import * A = 0 AE = 1 @@ -142,4 +142,4 @@ def condition(ctx, cc): # sign (SF == 1) ctx.emit( bisnz_ (r('sf', 8), cond)) - return cond \ No newline at end of file + return cond diff --git a/x86/control_flow.py b/pyreil/x86/control_flow.py similarity index 94% rename from x86/control_flow.py rename to pyreil/x86/control_flow.py index 4ab5ae6..d3bcbce 100644 --- a/x86/control_flow.py +++ b/pyreil/x86/control_flow.py @@ -14,7 +14,7 @@ # See the License for the specific language governing permissions and # limitations under the License. -"""reil.x86.control_flow - x86 and x86_64 translators +"""pyreil.x86.control_flow - x86 and x86_64 translators This module generates REIL (reverse engineering intermediate language) IL from x86 and x86_64 machine code. @@ -23,10 +23,12 @@ such as call, jmp and ret. """ -import reil.x86.conditional as conditional -import reil.x86.operand as operand -from reil.shorthand import * +from pyreil.shorthand import * + +from pyreil.x86 import operand +from pyreil.x86 import conditional + # Helpers @@ -170,4 +172,4 @@ def x86_ret(ctx, i): imm(ctx.word_size // 8, ctx.word_size), ctx.stack_ptr)) - ctx.emit( jcc_ (imm(1, 8), return_address)) \ No newline at end of file + ctx.emit( jcc_ (imm(1, 8), return_address)) diff --git a/x86/logic.py b/pyreil/x86/logic.py similarity index 91% rename from x86/logic.py rename to pyreil/x86/logic.py index 183c16f..13288e5 100644 --- a/x86/logic.py +++ b/pyreil/x86/logic.py @@ -14,7 +14,7 @@ # See the License for the specific language governing permissions and # limitations under the License. -"""reil.x86.logic - x86 and x86_64 translators +"""pyreil.x86.logic - x86 and x86_64 translators This module generates REIL (reverse engineering intermediate language) IL from x86 and x86_64 machine code. @@ -23,13 +23,12 @@ such as and, or, xor """ -import reil.error -from reil.shorthand import * - -import reil.x86.conditional as conditional -import reil.x86.operand as operand -from reil.x86.utilities import * +from pyreil.x86 import operand +from pyreil.x86 import conditional +from pyreil.x86.utilities import * +import pyreil.error +from pyreil.shorthand import * # Helpers @@ -122,4 +121,4 @@ def x86_xor(ctx, i): _logic_set_flags(ctx, result) - operand.set(ctx, i, 0, result, clear=True) \ No newline at end of file + operand.set(ctx, i, 0, result, clear=True) diff --git a/x86/memory.py b/pyreil/x86/memory.py similarity index 97% rename from x86/memory.py rename to pyreil/x86/memory.py index 2182a97..54cf62e 100644 --- a/x86/memory.py +++ b/pyreil/x86/memory.py @@ -14,7 +14,7 @@ # See the License for the specific language governing permissions and # limitations under the License. -"""reil.x86.memory - x86 and x86_64 translators +"""pyreil.x86.memory - x86 and x86_64 translators This module generates REIL (reverse engineering intermediate language) IL from x86 and x86_64 machine code. @@ -25,15 +25,12 @@ import capstone -import reil.error -from reil import * -from reil.shorthand import * - -import reil.x86.arithmetic as arithmetic -import reil.x86.conditional as conditional -import reil.x86.operand as operand -from reil.x86.utilities import * +from pyreil.shorthand import * +from pyreil.x86 import operand +from pyreil.x86 import arithmetic +from pyreil.x86 import conditional +from pyreil.x86.utilities import * def conditional_mov(ctx, i, condition): c = conditional.condition(ctx, condition) @@ -456,4 +453,4 @@ def x86_stosq(ctx, i): def x86_stosw(ctx, i): - x86_stos(ctx, i, 16) \ No newline at end of file + x86_stos(ctx, i, 16) diff --git a/x86/misc.py b/pyreil/x86/misc.py similarity index 97% rename from x86/misc.py rename to pyreil/x86/misc.py index 42a4c3e..16d4287 100644 --- a/x86/misc.py +++ b/pyreil/x86/misc.py @@ -14,7 +14,7 @@ # See the License for the specific language governing permissions and # limitations under the License. -"""reil.x86.misc - x86 and x86_64 translators +"""pyreil.x86.misc - x86 and x86_64 translators This module generates REIL (reverse engineering intermediate language) IL from x86 and x86_64 machine code. @@ -23,13 +23,12 @@ haven't categorised as anything yet """ -import reil.error -from reil.shorthand import * - -import reil.x86.conditional as conditional -import reil.x86.operand as operand -from reil.x86.utilities import * +import pyreil.error +from pyreil.shorthand import * +from pyreil.x86 import operand +from pyreil.x86 import conditional +from pyreil.x86.utilities import * def conditional_set(ctx, i, condition): c = conditional.condition(ctx, condition) @@ -399,4 +398,4 @@ def x86_xchg(ctx, i): def x86_rdtsc(ctx, i): - ctx.emit( nop_ ()) \ No newline at end of file + ctx.emit( nop_ ()) diff --git a/x86/operand.py b/pyreil/x86/operand.py similarity index 98% rename from x86/operand.py rename to pyreil/x86/operand.py index 22a858f..c66000e 100644 --- a/x86/operand.py +++ b/pyreil/x86/operand.py @@ -14,7 +14,7 @@ # See the License for the specific language governing permissions and # limitations under the License. -"""reil.x86.operands - x86 and x86_64 translators +"""pyreil.x86.operands - x86 and x86_64 translators This module generates REIL (reverse engineering intermediate language) IL from x86 and x86_64 machine code. @@ -25,11 +25,10 @@ import capstone -from reil.error import * -from reil.shorthand import * - -from reil.x86.utilities import * +from pyreil.error import * +from pyreil.shorthand import * +from pyreil.x86.utilities import * def _memory_address(ctx, i, opnd): @@ -565,4 +564,4 @@ def set(ctx, i, index, value, clear=False, sign_extend=False): else: raise TranslationError( - 'Unsupported operand type!') \ No newline at end of file + 'Unsupported operand type!') diff --git a/x86/sse.py b/pyreil/x86/sse.py similarity index 95% rename from x86/sse.py rename to pyreil/x86/sse.py index 9201924..0df555f 100644 --- a/x86/sse.py +++ b/pyreil/x86/sse.py @@ -14,7 +14,7 @@ # See the License for the specific language governing permissions and # limitations under the License. -"""reil.x86.sse - x86 and x86_64 translators +"""pyreil.x86.sse - x86 and x86_64 translators This module generates REIL (reverse engineering intermediate language) IL from x86 and x86_64 machine code. @@ -23,18 +23,11 @@ the streaming-simd extensions """ -import itertools +from pyreil.shorthand import * -import capstone -import capstone.x86 - -import reil.error -from reil.shorthand import * - -import reil.x86.conditional as conditional -import reil.x86.memory as memory -import reil.x86.operand as operand -from reil.x86.utilities import * +from pyreil.x86 import memory +from pyreil.x86 import operand +from pyreil.x86.utilities import * def unpack(ctx, value, size): parts = [] @@ -331,4 +324,4 @@ def x86_pxor(ctx, i): ctx.emit( xor_ (a, b, value)) - operand.set(ctx, i, 0, value) \ No newline at end of file + operand.set(ctx, i, 0, value) diff --git a/x86/translator.py b/pyreil/x86/translator.py similarity index 97% rename from x86/translator.py rename to pyreil/x86/translator.py index 70d4400..aeb099f 100644 --- a/x86/translator.py +++ b/pyreil/x86/translator.py @@ -14,7 +14,7 @@ # See the License for the specific language governing permissions and # limitations under the License. -"""reil.x86.sse - x86 and x86_64 translators +"""pyreil.x86.sse - x86 and x86_64 translators This module generates REIL (reverse engineering intermediate language) IL from x86 and x86_64 machine code. @@ -26,17 +26,16 @@ import capstone -import reil.native as native -import reil.definitions as reil -from reil.shorthand import * +import pyreil.native as native +from pyreil.shorthand import * -import reil.x86.arithmetic as arithmetic -import reil.x86.bitwise as bitwise -import reil.x86.control_flow as control_flow -import reil.x86.logic as logic -import reil.x86.memory as memory -import reil.x86.misc as misc -import reil.x86.sse as sse +from pyreil.x86 import arithmetic +from pyreil.x86 import bitwise +from pyreil.x86 import control_flow +from pyreil.x86 import logic +from pyreil.x86 import memory +from pyreil.x86 import misc +from pyreil.x86 import sse opcode_handlers = { @@ -405,4 +404,4 @@ def translate(code_bytes, base_address, x86_64=False): ends_basic_block(i), i.size) if ends_basic_block(i): - done = True \ No newline at end of file + done = True diff --git a/x86/utilities.py b/pyreil/x86/utilities.py similarity index 93% rename from x86/utilities.py rename to pyreil/x86/utilities.py index c931986..d3ae6ec 100644 --- a/x86/utilities.py +++ b/pyreil/x86/utilities.py @@ -14,14 +14,13 @@ # See the License for the specific language governing permissions and # limitations under the License. -"""reil.x86.utilities - x86 and x86_64 translation utility functions. +"""pyreil.x86.utilities - x86 and x86_64 translation utility functions. This module contains all the silly little utility functions that didn't belong anywhere else. """ -import reil.definitions as reil -from reil.shorthand import * +from pyreil.shorthand import * def carry_bit(size): """The mask required for the carry bit on a computation with a diff --git a/setup.py b/setup.py new file mode 100644 index 0000000..f4a2d13 --- /dev/null +++ b/setup.py @@ -0,0 +1,10 @@ +from setuptools import setup, find_packages + +setup( + name='pyreil', + description='REIL translation library.', + author='Mark Brand', + author_email='c01db33f@gmail.com', + packages=find_packages(), + install_requires=['capstone'], +)